Meson GXL USB3 PHY and OTG detection driver

PATCH New Martin Blumenstingl 5 participants 9 messages Sep 24, 2017 – Nov 7, 2017

Subsystems (3)

Device tree bindings Arm/Amlogic Meson SoC support Generic PHY framework

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Martin Blumenstingl

author reviewer

2017-09-24 19:49 UTC #0 lore raw

cover Meson GXL USB3 PHY and OTG detection driver

Amlogic Meson GXL SoCs use a dwc3 controller with two USB2 ports, Meson GXM SoCs use the same dwc3 controller but with three USB3 ports enabled. Neither of these SoCs has any USB3 port enabled in the dwc3 registers.
The first USB2 port on both SoCs supports host and peripheral (also called "device") mode.

The dwc3 controller supports host mode only. Peripheral mode is implemented through an additional dwc2 controller (which only enables device mode). The USB3 PHY has register bits which allow a driver to detect the current mode - however this is currently not implemented as the dwc2 controller seems to hang during reset (and I do not have a use-case where I need peripheral/device mode).

While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized, otherwise some boards (probably those where the bootloader does not initialize the USB3 PHY) show errors with high-speed USB devices connected to any of the USB2 ports. Configuring the USB_R1_U3H_FLADJ_30MHZ_REG_MASK register as it's done by Amlogic's vendor GPL kernel sources makes these error go away.

Thanks to Jerome Brunet for reporting the errors and Neil Armstrong for discovering that initializing the USB3 PHY fixes these USB errors!

Martin Blumenstingl (2):
dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL
SoCs
phy: amlogic: add USB3 PHY support for Meson GXL and GXM

 .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt |  19 +++
 drivers/phy/amlogic/Kconfig                        |  12 ++
 drivers/phy/amlogic/Makefile                       |   1 +
 drivers/phy/amlogic/phy-meson-gxl-usb3.c           | 177 +++++++++++++++++++++
 4 files changed, 209 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
 create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c

Signature · 1 line

2.14.1

Martin Blumenstingl

author reviewer

2017-09-24 19:49 UTC #1 lore raw

PATCH 1/2 dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL SoCs

Amlogic Meson GXL SoCs use a dwc3 controller with two (GXM - a variant for GXL, has three) USB2 ports. The first USB2 port supports host and peripheral (also called "device") mode.
While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized, otherwise some boards (probably those where the bootloader does not initialize the USB3 PHY) show errors with high-speed USB devices connected to any of the USB2 ports.

Signed-off-by Martin Blumenstingl <[email protected]>

---
 .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt    | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt

Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt new file +19 -0

new file mode 100644
index 000000000000..2b7c3715d52d
@@ -0,0 +1,19 @@
+* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding
+
+Required properties:
+- compatible:	Should be "amlogic,meson-gxl-usb3-phy"
+- reg:		The base address and length of the registers
+- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)
+
+Optional properties:
+- interrupts:	the interrupt specifier for the OTG detection
+- phy-supply:	see phy-bindings.txt in this directory
+
+
+Example:
+	usb3_phy0: phy at 78080 {
+		compatible = "amlogic,meson-gxl-usb3-phy";
+		#phy-cells = <0>;
+		reg = <0x0 0x78080 0x0 0x20>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+	};

Signature · 1 line

2.14.1

Rob Herring

maintainer

2017-10-05 20:02 UTC #2 lore raw

PATCH 1/2 dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL SoCs

Quoted 8 lines · Martin Blumenstingl

Amlogic Meson GXL SoCs use a dwc3 controller with two (GXM - a variant for GXL, has three) USB2 ports. The first USB2 port supports host and peripheral (also called "device") mode.
While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized, otherwise some boards (probably those where the bootloader does not initialize the USB3 PHY) show errors with high-speed USB devices connected to any of the USB2 ports.

Quoted 5 lines

Signed-off-by Martin Blumenstingl <[email protected]>

---
 .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt    | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt

Acked-by Rob Herring <[email protected]>

Martin Blumenstingl

author reviewer

2017-09-24 19:50 UTC #3 lore raw

PATCH 2/2 phy: amlogic: add USB3 PHY support for Meson GXL and GXM

In reply to Martin Blumenstingl

This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).

Unfortunately there is no documentation for this PHY in the public S905X datasheet (published for example by Khadas). What we know so far about this PHY:
- even though the Meson GXL and GXM SoCs do not expose an USB3 port (the dwc3 controller only has USB2 ports enabled) we need to initialize the USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this initialization high-speed USB devices (especially USB hard disks and thumb drives, slower devices like mice do not seem to be affected)
- it is responsible for the OTG detection and for switching the first USB2 PHY between host and peripheral (aka device) mode. an interrupt can be used to detect changes between host and device mode.

The whole OTG detection logic is currently not implemented.

Signed-off-by Martin Blumenstingl <[email protected]>

---
 drivers/phy/amlogic/Kconfig              |  12 +++
 drivers/phy/amlogic/Makefile             |   1 +
 drivers/phy/amlogic/phy-meson-gxl-usb3.c | 177 +++++++++++++++++++++++++++++++
 3 files changed, 190 insertions(+)
 create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c

drivers/phy/amlogic/Kconfig +12 -0

index cb8f4501652b..2f690d24203a 100644
@@ -25,3 +25,15 @@ config PHY_MESON_GXL_USB2
 	  Enable this to support the Meson USB2 PHYs found in Meson
 	  GXL and GXM SoCs.
 	  If unsure, say N.
+
+config PHY_MESON_GXL_USB3
+	tristate "Meson GXL and GXM USB3 PHY drivers"
+	default ARCH_MESON
+	depends on OF && (ARCH_MESON || COMPILE_TEST)
+	depends on USB_SUPPORT
+	select GENERIC_PHY
+	select REGMAP_MMIO
+	help
+	  Enable this to support the Meson USB3 PHY and OTG detection
+	  IP block found in Meson GXL and GXM SoCs.
+	  If unsure, say N.

drivers/phy/amlogic/Makefile +1 -0

index cfdc98715c30..4fd8848c194d 100644
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PHY_MESON8B_USB2)		+= phy-meson8b-usb2.o
 obj-$(CONFIG_PHY_MESON_GXL_USB2)	+= phy-meson-gxl-usb2.o
+obj-$(CONFIG_PHY_MESON_GXL_USB3)	+= phy-meson-gxl-usb3.o

drivers/phy/amlogic/phy-meson-gxl-usb3.c new file +177 -0

177 lines not on this page · raw message

Signature · 1 line

2.14.1

Kishon Vijay Abraham I

2017-11-07 05:53 UTC #4 lore raw

PATCH 2/2 phy: amlogic: add USB3 PHY support for Meson GXL and GXM

Hi,

Quoted 15 lines · Martin Blumenstingl

This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
Unfortunately there is no documentation for this PHY in the public S905X datasheet (published for example by Khadas). What we know so far about this PHY:
- even though the Meson GXL and GXM SoCs do not expose an USB3 port (the dwc3 controller only has USB2 ports enabled) we need to initialize the USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this initialization high-speed USB devices (especially USB hard disks and thumb drives, slower devices like mice do not seem to be affected)
- it is responsible for the OTG detection and for switching the first USB2 PHY between host and peripheral (aka device) mode. an interrupt can be used to detect changes between host and device mode.

Quoted 1 line

The whole OTG detection logic is currently not implemented.

Is this an independent instance of the phy? The programming model looks similar to phy-meson-gxl-usb2.c..

I'm just thinking if we should have only a phy-meson-gxl-usb.c and have both usb2 and usb3 phy programming there?

Thanks
Kishon

Martin Blumenstingl

author reviewer

2017-11-07 21:29 UTC #5 lore raw

PATCH 2/2 phy: amlogic: add USB3 PHY support for Meson GXL and GXM

Hi Kishon,

thank you for reviewing this!

Quoted 18 lines · Kishon Vijay Abraham I

Hi,
Quoted 15 lines · Martin Blumenstingl
This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout).
Unfortunately there is no documentation for this PHY in the public S905X datasheet (published for example by Khadas). What we know so far about this PHY:
- even though the Meson GXL and GXM SoCs do not expose an USB3 port (the dwc3 controller only has USB2 ports enabled) we need to initialize the USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this initialization high-speed USB devices (especially USB hard disks and thumb drives, slower devices like mice do not seem to be affected)
- it is responsible for the OTG detection and for switching the first USB2 PHY between host and peripheral (aka device) mode. an interrupt can be used to detect changes between host and device mode.

Quoted 4 lines

Quoted 1 line
The whole OTG detection logic is currently not implemented.
Is this an independent instance of the phy? The programming model looks similar to phy-meson-gxl-usb2.c..

there are up to four USB2 PHYs in these SoCs but only one USB3 PHY. from what I can tell both PHY types are different (both use a totally different register layout)

Quoted 2 lines

I'm just thinking if we should have only a phy-meson-gxl-usb.c and have both usb2 and usb3 phy programming there?

I can try that, but I think it would make the result harder to read (as the only parts that can be re-used are in the priv memory allocation, creating the regmap and the PHY registration in the _probe function)
so I would prefer to keep both PHYs as separate drivers in separate files

Regards
Martin

Jerome Brunet

reviewer

2017-10-02 13:27 UTC #6 lore raw

cover Meson GXL USB3 PHY and OTG detection driver

In reply to Martin Blumenstingl

Quoted 21 lines · Martin Blumenstingl

Amlogic Meson GXL SoCs use a dwc3 controller with two USB2 ports, Meson GXM SoCs use the same dwc3 controller but with three USB3 ports enabled. Neither of these SoCs has any USB3 port enabled in the dwc3 registers.
The first USB2 port on both SoCs supports host and peripheral (also called "device") mode.
The dwc3 controller supports host mode only. Peripheral mode is implemented through an additional dwc2 controller (which only enables device mode). The USB3 PHY has register bits which allow a driver to detect the current mode - however this is currently not implemented as the dwc2 controller seems to hang during reset (and I do not have a use-case where I need peripheral/device mode).
While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized, otherwise some boards (probably those where the bootloader does not initialize the USB3 PHY) show errors with high-speed USB devices connected to any of the USB2 ports. Configuring the USB_R1_U3H_FLADJ_30MHZ_REG_MASK register as it's done by Amlogic's vendor GPL kernel sources makes these error go away.

Quoted 3 lines

Thanks to Jerome Brunet for reporting the errors and Neil Armstrong for discovering that initializing the USB3 PHY fixes these USB errors!

This series works well on the libretech-cc (le potato) For the series:

Tested-by Jerome Brunet <[email protected]>

Quoted 16 lines

Martin Blumenstingl (2):
dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL
SoCs
phy: amlogic: add USB3 PHY support for Meson GXL and GXM

 .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt |  19 +++
 drivers/phy/amlogic/Kconfig                        |  12 ++
 drivers/phy/amlogic/Makefile                       |   1 +
 drivers/phy/amlogic/phy-meson-gxl-usb3.c           | 177
+++++++++++++++++++++
 4 files changed, 209 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-
phy.txt
 create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c

Neil Armstrong

2017-10-19 09:57 UTC #7 lore raw

cover Meson GXL USB3 PHY and OTG detection driver

In reply to Martin Blumenstingl

Quoted 30 lines · Martin Blumenstingl

Amlogic Meson GXL SoCs use a dwc3 controller with two USB2 ports, Meson GXM SoCs use the same dwc3 controller but with three USB3 ports enabled. Neither of these SoCs has any USB3 port enabled in the dwc3 registers.
The first USB2 port on both SoCs supports host and peripheral (also called "device") mode.
The dwc3 controller supports host mode only. Peripheral mode is implemented through an additional dwc2 controller (which only enables device mode). The USB3 PHY has register bits which allow a driver to detect the current mode - however this is currently not implemented as the dwc2 controller seems to hang during reset (and I do not have a use-case where I need peripheral/device mode).
While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized, otherwise some boards (probably those where the bootloader does not initialize the USB3 PHY) show errors with high-speed USB devices connected to any of the USB2 ports. Configuring the USB_R1_U3H_FLADJ_30MHZ_REG_MASK register as it's done by Amlogic's vendor GPL kernel sources makes these error go away.
Thanks to Jerome Brunet for reporting the errors and Neil Armstrong for discovering that initializing the USB3 PHY fixes these USB errors!
Martin Blumenstingl (2):
dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL
SoCs
phy: amlogic: add USB3 PHY support for Meson GXL and GXM

Quoted 8 lines

 .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt |  19 +++
 drivers/phy/amlogic/Kconfig                        |  12 ++
 drivers/phy/amlogic/Makefile                       |   1 +
 drivers/phy/amlogic/phy-meson-gxl-usb3.c           | 177 +++++++++++++++++++++
 4 files changed, 209 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
 create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c

Tested-by Neil Armstrong <[email protected]>

Martin Blumenstingl

author reviewer

2017-11-05 21:35 UTC #8 lore raw

cover Meson GXL USB3 PHY and OTG detection driver

In reply to Martin Blumenstingl

Hi Kishon,

Quoted 21 lines · Martin Blumenstingl

Amlogic Meson GXL SoCs use a dwc3 controller with two USB2 ports, Meson GXM SoCs use the same dwc3 controller but with three USB3 ports enabled. Neither of these SoCs has any USB3 port enabled in the dwc3 registers.
The first USB2 port on both SoCs supports host and peripheral (also called "device") mode.
The dwc3 controller supports host mode only. Peripheral mode is implemented through an additional dwc2 controller (which only enables device mode). The USB3 PHY has register bits which allow a driver to detect the current mode - however this is currently not implemented as the dwc2 controller seems to hang during reset (and I do not have a use-case where I need peripheral/device mode).
While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized, otherwise some boards (probably those where the bootloader does not initialize the USB3 PHY) show errors with high-speed USB devices connected to any of the USB2 ports. Configuring the USB_R1_U3H_FLADJ_30MHZ_REG_MASK register as it's done by Amlogic's vendor GPL kernel sources makes these error go away.

Quoted 7 lines

Thanks to Jerome Brunet for reporting the errors and Neil Armstrong for discovering that initializing the USB3 PHY fixes these USB errors!
Martin Blumenstingl (2):
dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL
SoCs

I need to update the dt-bindings patch as there is an interrupt which seems to exist on all hardware revisions (but this interrupt is not described in the binding yet)
so please do NOT take this series until I re-spin it so I can add the mandatory interrupt (if we add it later we can only add it optionally)

Quoted 1 line

phy: amlogic: add USB3 PHY support for Meson GXL and GXM

could you please give your feedback on this one?

Quoted 9 lines

 .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt |  19 +++
 drivers/phy/amlogic/Kconfig                        |  12 ++
 drivers/phy/amlogic/Makefile                       |   1 +
 drivers/phy/amlogic/phy-meson-gxl-usb3.c           | 177 +++++++++++++++++++++
 4 files changed, 209 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
 create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c

Quoted 3 lines

--
2.14.1

Regards,
Martin