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Patch "clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle" has been added to the 4.13-stable tree

PATCH [email protected] 1 participant 1 message Oct 10, 2017

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This is a note to let you know that I've just added the patch titled

clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle

to the 4.13-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
clk-samsung-exynos4-enable-vpll-and-epll-clocks-for-suspend-resume-cycle.patch
and it can be found in the queue-4.13 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From 5dcbeca615ef12047a5f4097b91030cbf995b1d2 Mon Sep 17 00:00:00 2001

From: Marek Szyprowski <[email protected]>
Date: Tue, 19 Sep 2017 12:01:08 +0200
Subject: clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle

From: Marek Szyprowski <[email protected]>

commit 5dcbeca615ef12047a5f4097b91030cbf995b1d2 upstream.

Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that VPLL and EPPL clocks were always enabled because the enable bit was never touched. Those clocks have to be enabled during suspend/resume cycle, because otherwise board fails to enter sleep mode. This patch enables them unconditionally before entering system suspend state. System restore function will set them to the previous state saved in the register cache done before that unconditional enable.

Fixes 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks")
---
 drivers/clk/samsung/clk-exynos4.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)
drivers/clk/samsung/clk-exynos4.c +15 -0
@@ -294,6 +294,18 @@ static const struct samsung_clk_reg_dump
 #define PLL_ENABLED	(1 << 31)
 #define PLL_LOCKED	(1 << 29)
 
+static void exynos4_clk_enable_pll(u32 reg)
+{
+	u32 pll_con = readl(reg_base + reg);
+	pll_con |= PLL_ENABLED;
+	writel(pll_con, reg_base + reg);
+
+	while (!(pll_con & PLL_LOCKED)) {
+		cpu_relax();
+		pll_con = readl(reg_base + reg);
+	}
+}
+
 static void exynos4_clk_wait_for_pll(u32 reg)
 {
 	u32 pll_con;
@@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void)
 	samsung_clk_save(reg_base, exynos4_save_pll,
 				ARRAY_SIZE(exynos4_clk_pll_regs));
 
+	exynos4_clk_enable_pll(EPLL_CON0);
+	exynos4_clk_enable_pll(VPLL_CON0);
+
 	if (exynos4_soc == EXYNOS4210) {
 		samsung_clk_save(reg_base, exynos4_save_soc,
 					ARRAY_SIZE(exynos4210_clk_save));

Patches currently in stable-queue which might be from [email protected] are

queue-4.13/clk-samsung-exynos4-enable-vpll-and-epll-clocks-for-suspend-resume-cycle.patch