ARM: boards: phytec-som-am335x: Add unified MLO

index 77f436f..b1576ee 100644
@@ -46,6 +46,94 @@ static const struct am33xx_cmd_control physom_cmd = {
 	.invert_clkout2	= 0x0,
 };
 
+/* Module family for the unified MLO
+ *
+ * NONE:        Unified MLO is not supported
+ * PHYCORE_R2:  Unified MLO for PCM-060, PCM-062
+ */
+enum {
+	NONE,
+	PHYCORE_R2,
+};
+
+/* @brief Supplies default ram timings for all ram sizes
+ *
+ * Returns generic ram timings for module families to find the correct
+ * ram size.
+ *
+ * @return struct am335x_sdram_timings* or NULL
+ */
+
+static noinline struct am335x_sdram_timings* get_minimal_timings(
+							int module_family)
+{
+	struct am335x_sdram_timings *timing;
+
+	switch (module_family) {
+	case PHYCORE_R2:
+		timing = &physom_timings[PHYCORE_R2_MT41K512M16HA125IT_1024MB];
+		break;
+	default:
+		timing = NULL;
+	}
+
+	return timing;
+}
+
+/* @brief Converts ramsizes to ram timings for phyCORE-R2 modules
+ *
+ * Returns ram timings for a given ram size or NULL, if this size is
+ * not supported.
+ *
+ * @return struct am335x_sdram_timings* or NULL
+ */
+
+static noinline struct am335x_sdram_timings* convert_phycore_r2_timings(
+								u32 ramsize)
+{
+	struct am335x_sdram_timings *timing;
+
+	switch (ramsize) {
+	case SZ_256M:
+		timing = &physom_timings[PHYCORE_R2_MT41K128M16JT_256MB];
+		break;
+	case SZ_512M:
+		timing = &physom_timings[PHYCORE_R2_MT41K256M16TW107IT_512MB];
+		break;
+	case SZ_1G:
+		timing = &physom_timings[PHYCORE_R2_MT41K512M16HA125IT_1024MB];
+		break;
+	default:
+		timing = NULL;
+	}
+
+	return timing;
+}
+
+/* @brief Converts a module family and ram size to ram timings
+ *
+ * Returns ram timings for a given ram size and module family or NULL,
+ * if the ram size or module family is not supported.
+ *
+ * @return struct am335x_sdram_timings* or NULL
+ */
+
+static noinline struct am335x_sdram_timings* get_timings_by_size(
+						int module_family, u32 ramsize)
+{
+	struct am335x_sdram_timings *timing;
+
+	switch (module_family) {
+	case PHYCORE_R2:
+		timing = convert_phycore_r2_timings(ramsize);
+		break;
+	default:
+		timing = NULL;
+	}
+
+	return timing;
+}
+
 /**
  * @brief The basic entry point for board initialization.
  *

@@ -55,9 +143,10 @@ static const struct am33xx_cmd_control physom_cmd = {
  *
  * @return void
  */
-static noinline void physom_board_init(int sdram, void *fdt)
+static noinline void physom_board_init(void *fdt, int sdram, int module_family)
 {
-	struct am335x_sdram_timings *timing = &physom_timings[sdram];
+	struct am335x_sdram_timings *timing = NULL;
+	u32 ramsize;
 
 	/*
 	 * WDT1 is already running when the bootloader gets control

@@ -71,6 +160,24 @@ static noinline void physom_board_init(int sdram, void *fdt)
 
 	am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400);
 
+	if (module_family == NONE) {
+		timing = &physom_timings[sdram];
+	} else {
+		/* Load generic DDR3 ram timings to find the ram size */
+		timing = get_minimal_timings(module_family);
+		if (!timing)
+			hang();
+		am335x_sdram_init(DDR_IOCTRL, &physom_cmd,
+				&timing->regs,
+				&timing->data);
+
+		/* Find the ram size and set up the correct ram timings */
+		ramsize = get_ram_size((long *) 0x80000000, SZ_1G);
+		timing = get_timings_by_size(module_family, ramsize);
+		if (!timing)
+			hang();
+	}
+
 	am335x_sdram_init(DDR_IOCTRL, &physom_cmd,
 			&timing->regs,
 			&timing->data);

@@ -83,7 +190,8 @@ static noinline void physom_board_init(int sdram, void *fdt)
 	am335x_barebox_entry(fdt);
 }
 
-static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void *fdt)
+static noinline void physom_board_entry(unsigned long bootinfo, int sdram,
+					void *fdt, int module_family)
 {
 	am33xx_save_bootinfo((void *)bootinfo);
 

@@ -95,26 +203,34 @@ static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void
 	 */
 	relocate_to_current_adr();
 	setup_c();
-
-	physom_board_init(sdram, fdt);
+	physom_board_init(fdt, sdram, module_family);
 }
 
-#define PHYTEC_ENTRY_MLO(name, fdt_name, sdram)			\
-	ENTRY_FUNCTION(name, bootinfo, r1, r2)			\
-	{							\
+#define PHYTEC_ENTRY_UNIFIED_MLO(name, fdt_name, module_family)		\
+	ENTRY_FUNCTION(name, bootinfo, r1, r2)				\
+	{								\
+		extern char __dtb_z_##fdt_name##_start[];		\
+		void *fdt = __dtb_z_##fdt_name##_start -		\
+			get_runtime_offset();				\
+		physom_board_entry(bootinfo, 0, fdt, module_family);	\
+	}
+
+#define PHYTEC_ENTRY_MLO(name, fdt_name, sdram)				\
+	ENTRY_FUNCTION(name, bootinfo, r1, r2)				\
+	{								\
 		extern char __dtb_z_##fdt_name##_start[];		\
 		void *fdt = __dtb_z_##fdt_name##_start -		\
-			get_runtime_offset();			\
-		physom_board_entry(bootinfo, sdram, fdt);	\
+			get_runtime_offset();				\
+		physom_board_entry(bootinfo, sdram, fdt, NONE);		\
 	}
 
-#define PHYTEC_ENTRY(name, fdt_name)				\
-	ENTRY_FUNCTION(name, r0, r1, r2)			\
-	{							\
+#define PHYTEC_ENTRY(name, fdt_name)					\
+	ENTRY_FUNCTION(name, r0, r1, r2)				\
+	{								\
 		extern char __dtb_z_##fdt_name##_start[];		\
 		void *fdt = __dtb_z_##fdt_name##_start -		\
-			get_runtime_offset();			\
-		am335x_barebox_entry(fdt);			\
+			get_runtime_offset();				\
+		am335x_barebox_entry(fdt);				\
 	}
 
 /* phycore-som */

@@ -122,9 +238,7 @@ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_128mb, am335x_phytec_phycore_s
 PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J128M16125IT_256MB);
 PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J256M16HA15EIT_512MB);
 PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB);
-PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K256M16TW107IT_512MB);
-PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K128M16JT_256MB);
-PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_1024mb,  am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K512M16HA125IT_1024MB);
+PHYTEC_ENTRY_UNIFIED_MLO(start_am33xx_phytec_phycore_r2_sram, am335x_phytec_phycore_som_mlo, PHYCORE_R2);
 PHYTEC_ENTRY(start_am33xx_phytec_phycore_nand_sdram, am335x_phytec_phycore_som_nand);
 PHYTEC_ENTRY(start_am33xx_phytec_phycore_emmc_sdram, am335x_phytec_phycore_som_emmc);
 PHYTEC_ENTRY(start_am33xx_phytec_phycore_nand_no_spi_sdram, am335x_phytec_phycore_som_nand_no_spi);

index 81aaec2..14b54aa 100644
@@ -132,6 +132,7 @@ struct variable_type {
 struct state_variable {
 	struct state *state;
 	struct list_head list;
+	struct variable_type *type;
 	const char *name;
 	unsigned int start;
 	unsigned int size;

index 56bcd95..e6571be 100644
@@ -116,6 +116,7 @@ static struct state_variable *state_uint8_create(struct state *state,
 	}
 
 	su32->param = param;
+	su32->var.type = state_find_type_by_name("uint8");
 	su32->var.size = sizeof(uint8_t);
 #ifdef __LITTLE_ENDIAN
 	su32->var.raw = &su32->value;

@@ -144,6 +145,7 @@ static struct state_variable *state_uint32_create(struct state *state,
 	}
 
 	su32->param = param;
+	su32->var.type = state_find_type_by_name("uint32");
 	su32->var.size = sizeof(uint32_t);
 	su32->var.raw = &su32->value;
 	su32->var.state = state;

@@ -234,6 +236,7 @@ static struct state_variable *state_enum32_create(struct state *state,
 
 	enum32->names = xzalloc(sizeof(char *) * num_names);
 	enum32->num_names = num_names;
+	enum32->var.type = state_find_type_by_name("enum32");
 	enum32->var.size = sizeof(uint32_t);
 	enum32->var.raw = &enum32->value;
 	enum32->var.state = state;

@@ -307,6 +310,7 @@ static struct state_variable *state_mac_create(struct state *state,
 
 	mac = xzalloc(sizeof(*mac));
 
+	mac->var.type = state_find_type_by_name("mac");
 	mac->var.size = ARRAY_SIZE(mac->value);
 	mac->var.raw = mac->value;
 	mac->var.state = state;

@@ -420,6 +424,7 @@ static struct state_variable *state_string_create(struct state *state,
 		return ERR_PTR(-EILSEQ);
 
 	string = xzalloc(sizeof(*string) + start_size[1]);
+	string->var.type = state_find_type_by_name("string");
 	string->var.size = start_size[1];
 	string->var.raw = &string->raw;
 	string->var.state = state;

index 266d211..063e03e 100644
@@ -693,6 +693,29 @@ int state_get_name(const struct state *state, char const **name)
 	return 0;
 }
 
+int state_read_mac(struct state *state, const char *name, u8 *buf)
+{
+	struct state_variable *svar;
+	struct state_mac *mac;
+	int i;
+
+	if (!state || !name || !buf)
+		return -EINVAL;
+
+	svar = state_find_var(state, name);
+	if (IS_ERR(svar))
+		return PTR_ERR(svar);
+
+	if (!strcmp(svar->type->type_name, "mac")) {
+		mac = to_state_mac(svar);
+		for (i = 0; i < 6; i++)
+			buf[i] = mac->value[i];
+		return 6;
+	}
+
+	return 0;
+}
+
 void state_info(void)
 {
 	struct state *state;

index 63164f9..f1882ae 100644
@@ -23,4 +23,6 @@ int state_load(struct state *state);
 int state_save(struct state *state);
 void state_info(void);
 
+int state_read_mac(struct state *state, const char *name, u8 *buf);
+
 #endif /* __STATE_H */

index dc3b84a..9f74981 100644
@@ -21,10 +21,12 @@
 #include <bootsource.h>
 #include <common.h>
 #include <nand.h>
+#include <net.h>
 #include <init.h>
 #include <io.h>
 #include <linux/sizes.h>
 #include <envfs.h>
+#include <state.h>
 #include <asm/armlinux.h>
 #include <generated/mach-types.h>
 #include <linux/phy.h>

@@ -65,8 +67,16 @@ static char *nandslots[] = {
 	"/dev/nand0.barebox_backup.bb",
 };
 
+#define ETH_COUNT 2
+static const char *eth_names[ETH_COUNT] = {"mac0", "mac1"};
+
 static int physom_devices_init(void)
 {
+	struct state *state;
+	u8 mac[6];
+	int state_ret;
+	int state_i;
+
 	if (!of_machine_is_compatible("phytec,am335x-som"))
 		return 0;
 

@@ -114,6 +124,17 @@ static int physom_devices_init(void)
 				ARRAY_SIZE(nandslots));
 	am33xx_bbu_emmc_mlo_register_handler("MLO.emmc", "/dev/mmc1");
 
+	if (IS_ENABLED(CONFIG_STATE)) {
+		state = state_by_name("am335x_phytec_mac_state");
+		if (state)
+			for (state_i = 0; state_i < 2; state_i++) {
+				state_ret = state_read_mac(state,
+						      eth_names[state_i], &mac[0]);
+				if (state_ret == 6)
+					eth_register_ethaddr(state_i, mac);
+			}
+	}
+
 	if (IS_ENABLED(CONFIG_SHELL_NONE))
 		return am33xx_of_register_bootdevice();