Skip to contentSkip to conversation

ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs

PATCH New Heiko Stuebner 1 participant 2 messages Mar 21, 2017 – Mar 22, 2017

Subsystems (2)
Device tree bindings Arm Rockchip
lore
Share & tools
lore

Heiko Stuebner

author maintainer
#0 lore raw

PATCH 1/1 ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs

According to [0] pointed out by Marc Zyngier in a report about a similar error message, PPIs 11 and 13 are edge triggered on Cortex-A9 socs including the rk3066 and rk3188 which currently mark them as level triggered.

Until some time ago the gic did not care but commit 992345a58e0c ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") introduced a warning for that case.

Fix the warning on these socs by describing the interrupts correctly and also using the binding constants for easier reading in the future.

[0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/boot/dts/rk3188.dtsi | 4 ++--
 arch/arm/boot/dts/rk3xxx.dtsi | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/boot/dts/rk3188.dtsi +2 -2
index cf91254d0a43..fa1bdb8875ae 100644
@@ -529,11 +529,11 @@
 };
 
 &global_timer {
-	interrupts = <GIC_PPI 11 0xf04>;
+	interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 };
 
 &local_timer {
-	interrupts = <GIC_PPI 13 0xf04>;
+	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 };
 
 &i2c0 {
arch/arm/boot/dts/rk3xxx.dtsi +2 -2
index 4480534d1b46..39e3f8bded1c 100644
@@ -132,14 +132,14 @@
 	global_timer: global-timer at 1013c200 {
 		compatible = "arm,cortex-a9-global-timer";
 		reg = <0x1013c200 0x20>;
-		interrupts = <GIC_PPI 11 0x304>;
+		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 		clocks = <&cru CORE_PERI>;
 	};
 
 	local_timer: local-timer at 1013c600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x1013c600 0x20>;
-		interrupts = <GIC_PPI 13 0x304>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 		clocks = <&cru CORE_PERI>;
 	};
Signature · 1 line
2.11.0
author maintainer
#1 lore raw

PATCH 1/1 ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs

Am Mittwoch, 22. M?rz 2017, 00:14:28 CET schrieb Heiko Stuebner:

Quoted 9 lines

According to [0] pointed out by Marc Zyngier in a report about a similar error message, PPIs 11 and 13 are edge triggered on Cortex-A9 socs including the rk3066 and rk3188 which currently mark them as level triggered.

Until some time ago the gic did not care but commit 992345a58e0c ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") introduced a warning for that case.

Quoted 6 lines

Fix the warning on these socs by describing the interrupts correctly and also using the binding constants for easier reading in the future.

[0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html

Signed-off-by Heiko Stuebner <[email protected]>

applied for 4.12