FSL PCI: Configure PCIe reference ratio
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform.
--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/pci/fsl_pci_init.c +6 -0
@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data); +#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */
Signature · 1 line
2.13.5
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);
drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */
Mingkai,
Do you ack this change? This presumes the PCIe clock derives from CCB bus clock.
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 45 lines
-----Original Message-----
From: York Sun
Sent: Friday, September 15, 2017 5:15 AM
To: Joakim Tjernlund <[email protected]>; Mingkai Hu <[email protected]>; u-boot @ lists . denx . de <[email protected]>; Roy Zang <[email protected]>
Subject: Re: [PATCH] FSL PCI: Configure PCIe reference ratioQuoted 29 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +6
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose ,cfg_addr ,cfg_data ); +#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) {Quoted 2 lines
pi = &pci->pit[2]; /*
0xDC0*/Mingkai,
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Do you ack this change? This presumes the PCIe clock derives from CCB bus clock.
gd->bus_clk indicates the platform clock while PCIe clock could be CCB or CCB/2. For example, it's CCB/2 for T1040/T1020, CCB for P2020.
I suggest to add the PCIe clock in gd to handle this difference, just like what we've done for other IP clocks.
Thanks,
Mingkai
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
In reply to Joakim TjernlundQuoted 19 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);
drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */
Ping?
Jocke
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 33 lines · Joakim Tjernlund
Quoted 19 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 37 lines · York Sun
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Quoted 33 lines · Joakim Tjernlund
Quoted 19 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.
Jocke
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 38 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 33 lines · Joakim Tjernlund
Quoted 19 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.
I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a Kconfig option and select the divisor by SoC?
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 47 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 43 lines · Joakim Tjernlund
Quoted 41 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 33 lines · Joakim Tjernlund
Quoted 19 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
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Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?
No, this is not something that needs Kconfig, just add the PEX_CCB_DIV #define in relevant PPC CPU, like in config_mpc85xx.h
Jocke
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 53 lines · Joakim Tjernlund
Quoted 52 lines · York Sun
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Quoted 47 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 33 lines · Joakim Tjernlund
Quoted 19 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.
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I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.h
So what should be in Kconfig, and what shouldn't? This is per SoC macro. Sounds like CONFIG_SYS_ in old days.
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 59 lines · York Sun
Quoted 57 lines · Joakim Tjernlund
Quoted 55 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 38 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 33 lines · Joakim Tjernlund
Quoted 19 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?
Quoted 6 lines
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No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.hSo what should be in
Kconfig, and what shouldn't? This is per SoC macro. Sounds likeCONFIG_SYS_in old days.
I must confess, I am not up to date with Kconfig stuff. I based my suggestion on what already exists in config_mpc85xx.h:
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#endif
#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_MAX_CPUS 2
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
....
etc.
Seems like a good place to put another CPU constant.
Anyhow, that patch stands of its own I think. Where to put all constants is another patch for NXP.
Jocke
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 32 lines · Joakim Tjernlund
Quoted 31 lines · York Sun
Quoted 29 lines · Joakim Tjernlund
Quoted 28 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 24 lines · Joakim Tjernlund
Quoted 23 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 19 lines · Joakim Tjernlund
Quoted 18 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
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drivers/pci/fsl_pci_init.c +6
-0pci_setup_indirect (hose, cfg_addr, cfg_data); +#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif
I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +0
-0block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?Quoted 6 lines
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No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.hSo what should be in
Kconfig, and what shouldn't? This is per SoC macro. Sounds likeCONFIG_SYS_in old days.I must confess, I am not up to date with
Kconfigstuff. I based my suggestion on what already exists inconfig_mpc85xx.h:
#elifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)||\defined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_E5500
#defineCONFIG_FSL_CORENET/* Freescale CoreNet platform */
#defineCONFIG_SYS_FSL_QORIQ_CHASSIS2/* Freescale Chassis generation 2 */
#defineCONFIG_SYS_FSL_CORES_PER_CLUSTER1
#defineCONFIG_SYS_FSL_QMAN_V3/* QMAN version 3 */
#ifdefCONFIG_SYS_FSL_DDR4
#defineCONFIG_SYS_FSL_DDRC_GEN4
#endif
#ifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)
#defineCONFIG_MAX_CPUS4
#elifdefined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_MAX_CPUS2
#endif
#defineCONFIG_SYS_FSL_NUM_CC_PLLS2
#defineCONFIG_SYS_FSL_CLUSTER_CLOCKS{ 1, 1, 1, 1 }
#defineCONFIG_SYS_FSL_NUM_LAWS16
#defineCONFIG_SYS_FSL_SRDS_1
#defineCONFIG_SYS_FSL_SEC_COMPAT5
#defineCONFIG_SYS_NUM_FMAN1
#defineCONFIG_SYS_NUM_FM1_DTSEC5
....
etc.
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Seems like a good place to put another CPU constant.
Yeah. We have been moving things out of header files and into Kconfig. I would avoid adding new macro to header files.
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Anyhow, that patch stands of its own I think. Where to put all constants is another patch for NXP.
Yes, we can add another patch to define this option for SoCs.
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 37 lines · York Sun
Quoted 34 lines · Joakim Tjernlund
Quoted 33 lines · York Sun
Quoted 31 lines · Joakim Tjernlund
Quoted 30 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 26 lines · Joakim Tjernlund
Quoted 25 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 21 lines · Joakim Tjernlund
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +0
-0block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?Quoted 6 lines
Quoted 3 lines
No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.hSo what should be in
Kconfig, and what shouldn't? This is per SoC macro. Sounds likeCONFIG_SYS_in old days.I must confess, I am not up to date with
Kconfigstuff. I based my suggestion on what already exists inconfig_mpc85xx.h:
#elifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)||\defined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_E5500
#defineCONFIG_FSL_CORENET/* Freescale CoreNet platform */
#defineCONFIG_SYS_FSL_QORIQ_CHASSIS2/* Freescale Chassis generation 2 */ #defineCONFIG_SYS_FSL_CORES_PER_CLUSTER1
#defineCONFIG_SYS_FSL_QMAN_V3/* QMAN version 3 */
#ifdefCONFIG_SYS_FSL_DDR4
#defineCONFIG_SYS_FSL_DDRC_GEN4
#endif
#ifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)
#defineCONFIG_MAX_CPUS4
#elifdefined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_MAX_CPUS2
#endif
#defineCONFIG_SYS_FSL_NUM_CC_PLLS2
#defineCONFIG_SYS_FSL_CLUSTER_CLOCKS{ 1, 1, 1, 1 }
#defineCONFIG_SYS_FSL_NUM_LAWS16
#defineCONFIG_SYS_FSL_SRDS_1#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5....
etc.
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Seems like a good place to put another CPU constant.
Yeah. We have been moving things out of header files and into
Kconfig. I would avoid adding new macro to header files.
OK, I am happy if don't have to manually select the constant.
Quoted 5 lines
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Anyhow, that patch stands of its own I think. Where to put all constants is another patch for NXP.
Yes, we can add another patch to define this option for SoCs.
:)
Jocke
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 50 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
Quoted 34 lines · Joakim Tjernlund
Quoted 33 lines · York Sun
Quoted 31 lines · Joakim Tjernlund
Quoted 30 lines · York Sun
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Quoted 26 lines · Joakim Tjernlund
Quoted 25 lines · York Sun
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Quoted 21 lines · Joakim Tjernlund
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);Quoted 11 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
Quoted 2 lines
I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
The only case we don't need to set this register is when the actual clock is 333MHz. I wonder why we didn't have a problem so far. Maybe we just didn't realize it.
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 54 lines · York Sun
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Quoted 50 lines · Joakim Tjernlund
Quoted 48 lines · York Sun
Quoted 32 lines · Joakim Tjernlund
Quoted 31 lines · York Sun
Quoted 29 lines · Joakim Tjernlund
Quoted 28 lines · York Sun
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Quoted 24 lines · Joakim Tjernlund
Quoted 23 lines · York Sun
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Quoted 19 lines · Joakim Tjernlund
Quoted 18 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)Quoted 8 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
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drivers/pci/fsl_pci_init.c +6
-0pci_setup_indirect (hose, cfg_addr, cfg_data); +#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
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I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
The only case we don't need to set this register is when the actual clock is 333MHz. I wonder why we didn't have a problem so far. Maybe we just didn't realize it.
Have you tried higher PCI speeds? I remember a board we had didn't work with higher speeds so we settled for less than max. Don't hav the board handy now.
Jocke
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 59 lines · Joakim Tjernlund
Quoted 58 lines · York Sun
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Quoted 52 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
Quoted 34 lines · Joakim Tjernlund
Quoted 33 lines · York Sun
Quoted 31 lines · Joakim Tjernlund
Quoted 30 lines · York Sun
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Quoted 26 lines · Joakim Tjernlund
Quoted 25 lines · York Sun
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Quoted 21 lines · Joakim Tjernlund
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);Quoted 11 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
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drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
Quoted 7 lines
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The only case we don't need to set this register is when the actual clock is 333MHz. I wonder why we didn't have a problem so far. Maybe we just didn't realize it.
Have you tried higher PCI speeds? I remember a board we had didn't work with higher speeds so we settled for less than max. Don't hav the board handy now.
No, I haven't.
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
In reply to Joakim TjernlundQuoted 119 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
Quoted 34 lines · Joakim Tjernlund
Quoted 33 lines · York Sun
Quoted 31 lines · Joakim Tjernlund
Quoted 30 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 26 lines · Joakim Tjernlund
Quoted 25 lines · York Sun
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Quoted 21 lines · Joakim Tjernlund
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);Quoted 11 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
Quoted 6 lines
drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
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drivers/pci/fsl_pci_init.c +0
-0block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?Quoted 6 lines
Quoted 3 lines
No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.hSo what should be in
Kconfig, and what shouldn't? This is per SoC macro. Sounds likeCONFIG_SYS_in old days.I must confess, I am not up to date with
Kconfigstuff. I based my suggestion on what already exists inconfig_mpc85xx.h:
#elifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)||\defined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_E5500
#defineCONFIG_FSL_CORENET/* Freescale CoreNet platform */
#defineCONFIG_SYS_FSL_QORIQ_CHASSIS2/* Freescale Chassis generation 2 */ #defineCONFIG_SYS_FSL_CORES_PER_CLUSTER1
#defineCONFIG_SYS_FSL_QMAN_V3/* QMAN version 3 */
#ifdefCONFIG_SYS_FSL_DDR4
#defineCONFIG_SYS_FSL_DDRC_GEN4
#endif
#ifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)
#defineCONFIG_MAX_CPUS4
#elifdefined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_MAX_CPUS2
#endif
#defineCONFIG_SYS_FSL_NUM_CC_PLLS2
#defineCONFIG_SYS_FSL_CLUSTER_CLOCKS{ 1, 1, 1, 1 }
#defineCONFIG_SYS_FSL_NUM_LAWS16
#defineCONFIG_SYS_FSL_SRDS_1#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5....
etc.Quoted 5 lines
Quoted 2 lines
Seems like a good place to put another CPU constant.
Yeah. We have been moving things out of header files and into
Kconfig. I would avoid adding new macro to header files.OK, I am happy if don't have to manually select the constant.
Quoted 1 line
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Anyhow, that patch stands of its own I think. Where to put all constants is another patch for NXP.
Yes, we can add another patch to define this option for SoCs.
:)
Jocke,
Where are we on this patch? Do we have any patch to define PEX_CCB_DIV to activate this new code?
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 126 lines · York Sun
Quoted 124 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
Quoted 34 lines · Joakim Tjernlund
Quoted 33 lines · York Sun
Quoted 31 lines · Joakim Tjernlund
Quoted 30 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 26 lines · Joakim Tjernlund
Quoted 25 lines · York Sun
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Quoted 21 lines · Joakim Tjernlund
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);Quoted 11 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
Quoted 6 lines
drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
Quoted 57 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
Quoted 6 lines
drivers/pci/fsl_pci_init.c +0
-0block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
Quoted 9 lines
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?Quoted 6 lines
Quoted 3 lines
No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.hSo what should be in
Kconfig, and what shouldn't? This is per SoC macro. Sounds likeCONFIG_SYS_in old days.I must confess, I am not up to date with
Kconfigstuff. I based my suggestion on what already exists inconfig_mpc85xx.h:
#elifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)||\defined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_E5500
#defineCONFIG_FSL_CORENET/* Freescale CoreNet platform */
#defineCONFIG_SYS_FSL_QORIQ_CHASSIS2/* Freescale Chassis generation 2 */ #defineCONFIG_SYS_FSL_CORES_PER_CLUSTER1
#defineCONFIG_SYS_FSL_QMAN_V3/* QMAN version 3 */
#ifdefCONFIG_SYS_FSL_DDR4
#defineCONFIG_SYS_FSL_DDRC_GEN4
#endif
#ifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)
#defineCONFIG_MAX_CPUS4
#elifdefined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_MAX_CPUS2
#endif
#defineCONFIG_SYS_FSL_NUM_CC_PLLS2
#defineCONFIG_SYS_FSL_CLUSTER_CLOCKS{ 1, 1, 1, 1 }
#defineCONFIG_SYS_FSL_NUM_LAWS16
#defineCONFIG_SYS_FSL_SRDS_1#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5....
etc.Quoted 5 lines
Quoted 2 lines
Seems like a good place to put another CPU constant.
Yeah. We have been moving things out of header files and into
Kconfig. I would avoid adding new macro to header files.OK, I am happy if don't have to manually select the constant.
Quoted 5 lines
Quoted 3 lines
Anyhow, that patch stands of its own I think. Where to put all constants is another patch for NXP.
Yes, we can add another patch to define this option for SoCs.
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:)
Jocke,
Where are we on this patch? Do we have any patch to define
PEX_CCB_DIVto activate this new code?
I think we are at me thinking we should add my simple patch:
+#ifdef PEX_CCB_DIV
+ /* Configure the PCIE controller core clock ratio */
+ pci_hose_write_config_dword(hose, dev, 0x440,>
+ ((gd->bus_clk / 1000000) *
+ (16 / PEX_CCB_DIV)) / 333);
+#endif
and then NXP find a suitable place to add PEX_CCB_DIV #define for each CPU/SOC. I am not working on such a patch anyhow.
Jocke
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 142 lines · Joakim Tjernlund
Quoted 126 lines · York Sun
Quoted 124 lines · Joakim Tjernlund
Quoted 37 lines · York Sun
Quoted 34 lines · Joakim Tjernlund
Quoted 33 lines · York Sun
Quoted 31 lines · Joakim Tjernlund
Quoted 30 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 26 lines · Joakim Tjernlund
Quoted 25 lines · York Sun
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
Quoted 21 lines · Joakim Tjernlund
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>--- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/pci/fsl_pci_init.c +0
-0@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect (hose, cfg_addr, cfg_data);Quoted 11 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 330
Quoted 6 lines
drivers/pci/fsl_pci_init.c +6
-0+#ifdef PEX_CCB_DIV +/* Configure the PCIE controller core clock ratio */ +pci_hose_write_config_dword (hose, dev,0x440 , + ((gd->bus_clk /1000000 ) * + (16 /PEX_CCB_DIV )) /333 ); +#endif I took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
Quoted 57 lines
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drivers/pci/fsl_pci_init.c void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) · line 333
Quoted 6 lines
drivers/pci/fsl_pci_init.c +0
-0block_rev =in_be32 (&pci->block_rev1);if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2 ];/* 0xDC0 */ Ping?
Quoted 9 lines
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?Quoted 6 lines
Quoted 3 lines
No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.hSo what should be in
Kconfig, and what shouldn't? This is per SoC macro. Sounds likeCONFIG_SYS_in old days.I must confess, I am not up to date with
Kconfigstuff. I based my suggestion on what already exists inconfig_mpc85xx.h:
#elifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)||\defined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_E5500
#defineCONFIG_FSL_CORENET/* Freescale CoreNet platform */
#defineCONFIG_SYS_FSL_QORIQ_CHASSIS2/* Freescale Chassis generation 2 */ #defineCONFIG_SYS_FSL_CORES_PER_CLUSTER1
#defineCONFIG_SYS_FSL_QMAN_V3/* QMAN version 3 */
#ifdefCONFIG_SYS_FSL_DDR4
#defineCONFIG_SYS_FSL_DDRC_GEN4
#endif
#ifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)
#defineCONFIG_MAX_CPUS4
#elifdefined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_MAX_CPUS2
#endif
#defineCONFIG_SYS_FSL_NUM_CC_PLLS2
#defineCONFIG_SYS_FSL_CLUSTER_CLOCKS{ 1, 1, 1, 1 }
#defineCONFIG_SYS_FSL_NUM_LAWS16
#defineCONFIG_SYS_FSL_SRDS_1#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5....
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Seems like a good place to put another CPU constant.
Yeah. We have been moving things out of header files and into
Kconfig. I would avoid adding new macro to header files.OK, I am happy if don't have to manually select the constant.
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Anyhow, that patch stands of its own I think. Where to put all constants is another patch for NXP.
Yes, we can add another patch to define this option for SoCs.
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:)
Jocke,
Where are we on this patch? Do we have any patch to define
PEX_CCB_DIVto activate this new code?I think we are at me thinking we should add my simple patch:
(quoted diff) +6
-0+#ifdef PEX_CCB_DIV + /* Configure the PCIE controller core clock ratio */ + pci_hose_write_config_dword(hose, dev, 0x440,> + ((gd->bus_clk / 1000000) * + (16 / PEX_CCB_DIV)) / 333); +#endif
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and then NXP find a suitable place to add
PEX_CCB_DIV#define for each CPU/SOC. I am not working on such a patch anyhow.
OK. I tend to accept this patch and have Mingkai to follow up on defining PEX_CCB_DIV for SoCs in need.
York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
York, did this go anywhere?
Jocke
Quoted 152 lines · York Sun
Quoted 142 lines · Joakim Tjernlund
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Quoted 26 lines · Joakim Tjernlund
Quoted 25 lines · York Sun
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Quoted 21 lines · Joakim Tjernlund
Quoted 20 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.Signed-off-by: Joakim Tjernlund <[email protected]>
---
drivers/pci/fsl_pci_init.c | 6 ++++++
1 file changed, 6 insertions(+)diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 52792dcd59..4d00b3f26c 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)pci_setup_indirect(hose, cfg_addr, cfg_data);
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+#ifdef PEX_CCB_DIV
+ /* Configure the PCIE controller core clock ratio */
+ pci_hose_write_config_dword(hose, dev, 0x440,
+ ((gd->bus_clk / 1000000) *
+ (16 / PEX_CCB_DIV)) / 333);
+#endifI took another look at this patch. Would it be appropriate to alway write to this register with correct clock?
I sure hope so, the docs I have only mentions this reg having a default value which needs to be changed in most cases I guess.
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block_rev = in_be32(&pci->block_rev1);
if (PEX_IP_BLK_REV_2_2 <= block_rev) {
pi = &pci->pit[2]; /* 0xDC0 */Ping?
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Jocke
I believe Mingkai's last comment was "to add the PCIe clock in gd".
Right, I seem to have forgotten to comment on that ...
Why add that complexity/bloat? This is a constant defined by the CPU/SOC so it makes perfect sense to just #define it.I am leaning to agree with you. The clock is either CCB clock, or CCB/2. Would it be better if you use a
Kconfigoption and select the divisor by SoC?Quoted 6 lines
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No, this is not something that needs
Kconfig, just add thePEX_CCB_DIV#define in relevant PPC CPU, like inconfig_mpc85xx.hSo what should be in
Kconfig, and what shouldn't? This is per SoC macro. Sounds likeCONFIG_SYS_in old days.I must confess, I am not up to date with
Kconfigstuff. I based my suggestion on what already exists inconfig_mpc85xx.h:
#elifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)||\defined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_E5500
#defineCONFIG_FSL_CORENET/* Freescale CoreNet platform */
#defineCONFIG_SYS_FSL_QORIQ_CHASSIS2/* Freescale Chassis generation 2 */ #defineCONFIG_SYS_FSL_CORES_PER_CLUSTER1
#defineCONFIG_SYS_FSL_QMAN_V3/* QMAN version 3 */
#ifdefCONFIG_SYS_FSL_DDR4
#defineCONFIG_SYS_FSL_DDRC_GEN4
#endif
#ifdefined(CONFIG_PPC_T1040)||defined(CONFIG_PPC_T1042)
#defineCONFIG_MAX_CPUS4
#elifdefined(CONFIG_PPC_T1020)||defined(CONFIG_PPC_T1022)
#defineCONFIG_MAX_CPUS2
#endif
#defineCONFIG_SYS_FSL_NUM_CC_PLLS2
#defineCONFIG_SYS_FSL_CLUSTER_CLOCKS{ 1, 1, 1, 1 }
#defineCONFIG_SYS_FSL_NUM_LAWS16
#defineCONFIG_SYS_FSL_SRDS_1#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5....
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Seems like a good place to put another CPU constant.
Yeah. We have been moving things out of header files and into
Kconfig. I would avoid adding new macro to header files.OK, I am happy if don't have to manually select the constant.
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Anyhow, that patch stands of its own I think. Where to put all constants is another patch for NXP.
Yes, we can add another patch to define this option for SoCs.
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:)
Jocke,
Where are we on this patch? Do we have any patch to define
PEX_CCB_DIVto activate this new code?I think we are at me thinking we should add my simple patch:
(quoted diff) +6
-0+#ifdef PEX_CCB_DIV + /* Configure the PCIE controller core clock ratio */ + pci_hose_write_config_dword(hose, dev, 0x440,> + ((gd->bus_clk / 1000000) * + (16 / PEX_CCB_DIV)) / 333); +#endifQuoted 3 lines
and then NXP find a suitable place to add
PEX_CCB_DIV#define for each CPU/SOC. I am not working on such a patch anyhow.OK. I tend to accept this patch and have Mingkai to follow up on defining
PEX_CCB_DIVfor SoCs in need.York
PATCH 1/1 FSL PCI: Configure PCIe reference ratio
Quoted 1 line · Joakim Tjernlund
York, did this go anywhere?
No, I didn't hear from Mingkai. I am OK with this patch and will merge it.
York
York Sun
AppliedPATCH 1/1 FSL PCI: Configure PCIe reference ratio
In reply to Joakim TjernlundQuoted 9 lines · Joakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds
PEX_CCB_DIV#define which can be defined for each type of CPU/platform.Signed-off-by Joakim Tjernlund <[email protected]>---
Applied to fsl-qoriq master, awaiting upstream.
Thanks.
York