Add FPGA driver, SDRAM driver, generic firmware loader and booting U-Boot.

index ac6f504..3cb0bcd 100644
@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,
 	   "(Xilinx only)\n"
 #endif
 #if defined(CONFIG_CMD_FPGA_LOADFS)
-	   "Load device from filesystem (FAT by default) (Xilinx only)\n"
+	   "Load device from filesystem (FAT by default)\n"
 	   "  loadfs [dev] [address] [image size] [blocksize] <interface>\n"
 	   "        [<dev[:part]>] <filename>\n"
 #endif

index 135a357..a03e835 100644
@@ -23,25 +23,31 @@ static const struct altera_fpga {
 	enum altera_family	family;
 	const char		*name;
 	int			(*load)(Altera_desc *, const void *, size_t);
+	int (*loadfs)(Altera_desc *, const void *, size_t, fpga_fs_info *);
 	int			(*dump)(Altera_desc *, const void *, size_t);
 	int			(*info)(Altera_desc *);
 } altera_fpga[] = {
 #if defined(CONFIG_FPGA_ACEX1K)
-	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
-	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
+	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+	 ACEX1K_info },
+	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
+	 ACEX1K_info },
 #elif defined(CONFIG_FPGA_CYCLON2)
-	{ Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
-	{ Altera_CYC2,   "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
+	{ Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
+	{ Altera_CYC2,   "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_II)
-	{ Altera_StratixII, "StratixII", StratixII_load,
+	{ Altera_StratixII, "StratixII", StratixII_load, NULL,
 	  StratixII_dump, StratixII_info },
 #endif
 #if defined(CONFIG_FPGA_STRATIX_V)
-	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
+	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL, NULL },
 #endif
-#if defined(CONFIG_FPGA_SOCFPGA)
-	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
+#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS)
+	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, socfpga_loadfs, NULL,
+	 NULL },
+#elif defined(CONFIG_FPGA_SOCFPGA)
+	{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL, NULL },
 #endif
 };
 

@@ -174,3 +180,21 @@ int altera_info(Altera_desc *desc)
 
 	return FPGA_SUCCESS;
 }
+
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo)
+{
+	const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
+
+	if (!fpga)
+		return FPGA_FAIL;
+
+	debug_cond(FPGA_DEBUG, "%s: Launching the %s FS Loader...\n",
+		   __func__, fpga->name);
+	if (fpga->loadfs)
+		return fpga->loadfs(desc, buf, bsize, fpga_fsinfo);
+
+	return -EINVAL;
+}
+#endif

index e0fb1b4..42e901e 100644
@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
 			fpga_no_sup((char *)__func__, "Xilinx devices");
 #endif
 			break;
+#if defined(CONFIG_FPGA_ALTERA)
+		case fpga_altera:
+			ret_val = altera_loadfs(desc->devdesc, buf, size,
+						fpga_fsinfo);
+#else
+			fpga_no_sup((char *)__func__, "Altera devices");
+#endif
+			break;
 		default:
 			printf("%s: Invalid or unsupported device type %d\n",
 			       __func__, desc->devtype);

index d768fb1..8920016 100644
@@ -56,8 +56,10 @@ int fpga_count(void);
 const fpga_desc *const fpga_get_desc(int devnum);
 int fpga_load(int devnum, const void *buf, size_t bsize,
 	      bitstream_type bstype);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
 int fpga_fsload(int devnum, const void *buf, size_t size,
 		fpga_fs_info *fpga_fsinfo);
+#endif
 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
 		       bitstream_type bstype);
 int fpga_dump(int devnum, const void *buf, size_t bsize);

index b57e0b0..183d05a 100644
@@ -114,7 +114,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
 	return -ENODEV;
 }
 
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
 {
 #if CONFIG_IS_ENABLED(DM_MMC)
 	struct udevice *dev;

index 308ce7b..912983a 100644
@@ -10,6 +10,7 @@
 /* Platform-specific defines */
 #include <linux/compiler.h>
 #include <asm/spl.h>
+#include <mmc.h>
 
 /* Value in r0 indicates we booted from U-Boot */
 #define UBOOT_NOT_LOADED_FROM_SPL	0x13578642

@@ -72,6 +73,7 @@ void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(const u32 boot_device);
 void spl_set_bd(void);
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
 
 /**
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure

299 lines not on this page · raw message

new file mode 100644
index 0000000..dacc1f3
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+#ifndef _FS_LOADER_H_
+#define _FS_LOADER_H_
+
+#include <linux/types.h>
+
+struct firmware {
+	size_t size;		/* Size of a file */
+	const u8 *data;		/* Buffer for file */
+	const char *name;	/* Filename */
+	u32 offset;		/* Offset of reading a file */
+	void *priv;		/* Firmware loader private fields */
+};
+
+struct device_location {
+	char *name;	/* Such as mmc, usb,and sata. */
+	char *devpart;  /* Use the load command dev:part conventions */
+	char *mtdpart;	/* MTD partition for ubi part */
+	char *ubivol;	/* UBI volume-name for ubifsmount */
+};
+
+int request_firmware_into_buf(struct firmware **firmware_p,
+			      const char *name,
+			      struct device_location *location,
+			      void *buf, size_t size, u32 offset);
+#endif

index 5c1a68a..e076bda 100644
@@ -112,13 +112,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
 	unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 
-	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
-	 * timeout at 1000ms
+	/*
+	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+	 * de-asserted, timeout at 1000ms
 	 */
 	return wait_for_bit(__func__,
 			    &fpga_manager_base->imgcfg_stat,
 			    mask,
-			    false, FPGA_TIMEOUT_MSEC, false);
+			    true, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)

index 9cbf696..afcf7d8 100644
@@ -8,6 +8,9 @@
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
+#include <asm/cache.h>
+#include <fs_loader.h>
+
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK		BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK	BIT(1)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 		BIT(2)

@@ -89,11 +92,40 @@ struct socfpga_fpga_manager {
 	u32  imgcfg_fifo_status;
 };
 
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+enum rbf_type {unknown, periph_section, core_section};
+enum rbf_security {invalid, unencrypted, encrypted};
+
+struct rbf_info {
+	enum rbf_type section;
+	enum rbf_security security;
+};
+
+struct flash_info {
+	struct device_location dev;
+	char *filename;
+	int fstype;
+	u32 remaining;
+	u32 offset;
+	struct rbf_info rbfinfo;
+	struct image_header header;
+};
+#endif
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core);
+const char *get_cff_devpart(const void *fdt, int *len);
+int fs_flash_preinit(struct flash_info *flashinfo, u32 *buffer,
+		     u32 *buffer_sizebytes);
+int fs_flash_read(struct flash_info *flashinfo, u32 *buffer,
+		  u32 *buffer_sizebytes);
+#endif
+void set_flash_devpart(char *name, char *devpart);
 
 #endif /* __ASSEMBLY__ */
 

405 lines not on this page · raw message

index 48d3eb7..0597e8a 100644
@@ -84,6 +84,10 @@ typedef struct {
 extern int altera_load(Altera_desc *desc, const void *image, size_t size);
 extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
 extern int altera_info(Altera_desc *desc);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo);
+#endif
 
 /* Board specific implementation specific function types
  *********************************************************************/

@@ -111,6 +115,8 @@ typedef struct {
 
 #ifdef CONFIG_FPGA_SOCFPGA
 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+int socfpga_loadfs(Altera_desc *desc, const void *buf, size_t bsize,
+		   fpga_fs_info *fpga_fsinfo);
 #endif
 
 #ifdef CONFIG_FPGA_STRATIX_V

index b11228f..137e073 100644
@@ -8,435 +8,9 @@
 
 #ifndef __ASSEMBLY__
 
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
-	u32	ctrl_cfg;
-	u32	dram_timing1;
-	u32	dram_timing2;
-	u32	dram_timing3;
-	u32	dram_timing4;	/* 0x10 */
-	u32	lowpwr_timing;
-	u32	dram_odt;
-	u32	extratime1;
-	u32	__padding0[3];
-	u32	dram_addrw;	/* 0x2c */
-	u32	dram_if_width;	/* 0x30 */
-	u32	dram_dev_width;
-	u32	dram_sts;
-	u32	dram_intr;
-	u32	sbe_count;	/* 0x40 */
-	u32	dbe_count;
-	u32	err_addr;
-	u32	drop_count;
-	u32	drop_addr;	/* 0x50 */
-	u32	lowpwr_eq;
-	u32	lowpwr_ack;
-	u32	static_cfg;
-	u32	ctrl_width;	/* 0x60 */
-	u32	cport_width;
-	u32	cport_wmap;
-	u32	cport_rmap;
-	u32	rfifo_cmap;	/* 0x70 */
-	u32	wfifo_cmap;
-	u32	cport_rdwr;
-	u32	port_cfg;
-	u32	fpgaport_rst;	/* 0x80 */
-	u32	__padding1;
-	u32	fifo_cfg;
-	u32	protport_default;
-	u32	prot_rule_addr;	/* 0x90 */
-	u32	prot_rule_id;
-	u32	prot_rule_data;
-	u32	prot_rule_rdwr;
-	u32	__padding2[3];
-	u32	mp_priority;	/* 0xac */
-	u32	mp_weight0;	/* 0xb0 */
-	u32	mp_weight1;
-	u32	mp_weight2;
-	u32	mp_weight3;
-	u32	mp_pacing0;	/* 0xc0 */
-	u32	mp_pacing1;
-	u32	mp_pacing2;
-	u32	mp_pacing3;
-	u32	mp_threshold0;	/* 0xd0 */
-	u32	mp_threshold1;
-	u32	mp_threshold2;
-	u32	__padding3[29];
-	u32	phy_ctrl0;	/* 0x150 */
-	u32	phy_ctrl1;
-	u32	phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
-	u32	ctrl_cfg;
-	u32	dram_timing1;
-	u32	dram_timing2;
-	u32	dram_timing3;
-	u32	dram_timing4;
-	u32	lowpwr_timing;
-	u32	dram_odt;
-	u32	extratime1;
-	u32	dram_addrw;
-	u32	dram_if_width;
-	u32	dram_dev_width;
-	u32	dram_intr;
-	u32	lowpwr_eq;
-	u32	static_cfg;
-	u32	ctrl_width;
-	u32	cport_width;
-	u32	cport_wmap;
-	u32	cport_rmap;
-	u32	rfifo_cmap;
-	u32	wfifo_cmap;
-	u32	cport_rdwr;
-	u32	port_cfg;
-	u32	fpgaport_rst;
-	u32	fifo_cfg;
-	u32	mp_priority;
-	u32	mp_weight0;
-	u32	mp_weight1;
-	u32	mp_weight2;
-	u32	mp_weight3;
-	u32	mp_pacing0;
-	u32	mp_pacing1;
-	u32	mp_pacing2;
-	u32	mp_pacing3;
-	u32	mp_threshold0;
-	u32	mp_threshold1;
-	u32	mp_threshold2;
-	u32	phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
-	u8	activate_0_and_1;
-	u8	activate_0_and_1_wait1;
-	u8	activate_0_and_1_wait2;
-	u8	activate_1;
-	u8	clear_dqs_enable;
-	u8	guaranteed_read;
-	u8	guaranteed_read_cont;
-	u8	guaranteed_write;
-	u8	guaranteed_write_wait0;
-	u8	guaranteed_write_wait1;
-	u8	guaranteed_write_wait2;
-	u8	guaranteed_write_wait3;
-	u8	idle;
-	u8	idle_loop1;
-	u8	idle_loop2;
-	u8	init_reset_0_cke_0;
-	u8	init_reset_1_cke_0;
-	u8	lfsr_wr_rd_bank_0;
-	u8	lfsr_wr_rd_bank_0_data;
-	u8	lfsr_wr_rd_bank_0_dqs;
-	u8	lfsr_wr_rd_bank_0_nop;
-	u8	lfsr_wr_rd_bank_0_wait;
-	u8	lfsr_wr_rd_bank_0_wl_1;
-	u8	lfsr_wr_rd_dm_bank_0;
-	u8	lfsr_wr_rd_dm_bank_0_data;
-	u8	lfsr_wr_rd_dm_bank_0_dqs;
-	u8	lfsr_wr_rd_dm_bank_0_nop;
-	u8	lfsr_wr_rd_dm_bank_0_wait;
-	u8	lfsr_wr_rd_dm_bank_0_wl_1;
-	u8	mrs0_dll_reset;
-	u8	mrs0_dll_reset_mirr;
-	u8	mrs0_user;
-	u8	mrs0_user_mirr;
-	u8	mrs1;
-	u8	mrs1_mirr;
-	u8	mrs2;
-	u8	mrs2_mirr;
-	u8	mrs3;
-	u8	mrs3_mirr;
-	u8	precharge_all;
-	u8	read_b2b;
-	u8	read_b2b_wait1;
-	u8	read_b2b_wait2;
-	u8	refresh_all;
-	u8	rreturn;
-	u8	sgle_read;
-	u8	zqcl;
-
-	u8	true_mem_data_mask_width;
-	u8	mem_address_mirroring;
-	u8	mem_data_mask_width;
-	u8	mem_data_width;
-	u8	mem_dq_per_read_dqs;
-	u8	mem_dq_per_write_dqs;
-	u8	mem_if_read_dqs_width;
-	u8	mem_if_write_dqs_width;
-	u8	mem_number_of_cs_per_dimm;
-	u8	mem_number_of_ranks;
-	u8	mem_virtual_groups_per_read_dqs;
-	u8	mem_virtual_groups_per_write_dqs;
-};
-
-struct socfpga_sdram_io_config {
-	u16	delay_per_opa_tap;
-	u8	delay_per_dchain_tap;
-	u8	delay_per_dqs_en_dchain_tap;
-	u8	dll_chain_length;
-	u8	dqdqs_out_phase_max;
-	u8	dqs_en_delay_max;
-	u8	dqs_en_delay_offset;
-	u8	dqs_en_phase_max;
-	u8	dqs_in_delay_max;
-	u8	dqs_in_reserve;
-	u8	dqs_out_reserve;
-	u8	io_in_delay_max;
-	u8	io_out1_delay_max;
-	u8	io_out2_delay_max;
-	u8	shift_dqs_en_when_shift_dqs;
-};
-
-struct socfpga_sdram_misc_config {
-	u32	reg_file_init_seq_signature;
-	u8	afi_rate_ratio;
-	u8	calib_lfifo_offset;
-	u8	calib_vfifo_offset;
-	u8	enable_super_quick_calibration;
-	u8	max_latency_count_width;
-	u8	read_valid_fifo_size;
-	u8	tinit_cntr0_val;
-	u8	tinit_cntr1_val;
-	u8	tinit_cntr2_val;
-	u8	treset_cntr0_val;
-	u8	treset_cntr1_val;
-	u8	treset_cntr2_val;
-};
-
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
-/* Register template: sdr::ctrlgrp::dramtiming1                            */
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming2                            */
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
-/* Register template: sdr::ctrlgrp::dramtiming3                            */
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming4                            */
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::lowpwrtiming                           */
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
-/* Register template: sdr::ctrlgrp::dramaddrw                              */
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
-/* Register template: sdr::ctrlgrp::dramifwidth                            */
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dramdevwidth                           */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramintr                               */
-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
-/* Register template: sdr::ctrlgrp::staticcfg                              */
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::ctrlwidth                              */
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::cportwidth                             */
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::cportwmap                              */
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::cportrmap                              */
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::rfifocmap                              */
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::wfifocmap                              */
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::cportrdwr                              */
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::portcfg                                */
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::fifocfg                                */
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::mppriority                             */
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
-#define  \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
-0x0000ffff
-/* Register template: sdr::ctrlgrp::remappriority                          */
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
- (((x) << 10) & 0x00000c00)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
- (((x) << 6) & 0x000000c0)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
- (((x) << 8) & 0x00000100)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
- (((x) << 9) & 0x00000200)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
- (((x) << 4) & 0x00000030)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
- (((x) << 2) & 0x0000000c)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
- (((x) << 0) & 0x00000003)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::dramodt                                */
-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
-/* Field instance: sdr::ctrlgrp::dramsts                                   */
-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-/* Register template: sdr::ctrlgrp::extratime1                             */
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
-
-/* SDRAM width macro for configuration with ECC */
-#define SDRAM_WIDTH_32BIT_WITH_ECC	40
-#define SDRAM_WIDTH_16BIT_WITH_ECC	24
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/sdram_gen5.h>
+#endif
 
 #endif
 #endif /* _SDRAM_H_ */

similarity index 99%
copy from arch/arm/mach-socfpga/include/mach/sdram.h
copy to arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index b11228f..b16d776 100644
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef	_SDRAM_H_
-#define	_SDRAM_H_
+#ifndef	_SOCFPGA_SDRAM_GEN5_H_
+#define	_SOCFPGA_SDRAM_GEN5_H_
 
 #ifndef __ASSEMBLY__
 

@@ -439,4 +439,4 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
 #define SDRAM_WIDTH_16BIT_WITH_ECC	24
 
 #endif
-#endif /* _SDRAM_H_ */
+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */

similarity index 100%
rename from drivers/ddr/altera/sdram.c
rename to drivers/ddr/altera/sdram_gen5.c

index a41d089..965f9dc 100644
@@ -29,6 +29,13 @@ int board_init(void)
 	return 0;
 }
 
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.usb_gusbcfg	= 0x1417,

index 8a7debb..31b1eda 100644
@@ -43,6 +43,7 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040
 #else

index 137e073..33f830b 100644
@@ -10,6 +10,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include <asm/arch/sdram_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/sdram_arria10.h>
 #endif
 
 #endif

index 1d7b7c1..e7a2503 100644
@@ -8,6 +8,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
 	u32 ip_rev_id;

@@ -204,6 +205,7 @@ struct socfpga_io48_mmr {
 	u32 niosreserve1;
 	u32 niosreserve2;
 };
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000

737 lines not on this page · raw message

index 31b1eda..7dcacbc 100644
@@ -263,17 +263,33 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * SPL
  *
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
  *
  * 0xFFFF_0000 ...... Start of SRAM
  * 0xFFFF_xxxx ...... Top of stack (grows down)
  * 0xFFFF_yyyy ...... Malloc area
  * 0xFFFF_zzzz ...... Global Data
  * 0xFFFF_FF00 ...... End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_0000 ...... Start of SRAM (bottom)
+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc area (grows up to top)
+ * 0xFFE3_FFFF ...... End of SRAM (top)
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE + \
+					 CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT

@@ -303,7 +319,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Stack setup
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK		CONFIG_SYS_SPL_MALLOC_START
+#endif
 
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD

index d6b9435..7e8a2b1 100644
@@ -14,8 +14,8 @@ _start:
 	.balignl 64,0xf33db33f;
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
-	.word	0xc01df00d;	/* Version, flags, length */
-	.word	0xcafec0d3;	/* Checksum, zero-pad */
+	.word	0xc01df00d;	/* Header length(2B),flags(1B),version(1B) */
+	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;
 
 	b reset;		/* SoCFPGA jumps here */

index 7e8a2b1..e6db659 100644
@@ -15,6 +15,13 @@ _start:
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
 	.word	0xc01df00d;	/* Header length(2B),flags(1B),version(1B) */
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+	.word	0xfeedface;	/* Program length(4B) */
+	.word	0xf00dcafe;	/*
+				 * Program entry offset(4B),relative to
+				 * the start of program header
+				 */
+#endif
 	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;
 

index 965f9dc..8d3b515 100644
@@ -8,7 +8,9 @@
 
 #include <common.h>
 #include <errno.h>
+#include <fdtdec.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/clock_manager.h>
 #include <asm/io.h>
 
 #include <usb.h>

@@ -26,6 +28,11 @@ int board_init(void)
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+	/* configuring the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+#endif
+
 	return 0;
 }
 

index 8d3b515..7beb347 100644
@@ -11,6 +11,7 @@
 #include <fdtdec.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
 #include <asm/io.h>
 
 #include <usb.h>

@@ -31,6 +32,9 @@ int board_init(void)
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 	/* configuring the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
 #endif
 
 	return 0;

index 9d751f6..8760ac9 100644
@@ -94,11 +94,6 @@ int arch_early_init_r(void)
 	/* assert reset to all except L4WD0 and L4TIMER0 */
 	socfpga_per_reset_all();
 
-	/* configuring the clock based on handoff */
-	/* TODO: Add call to cm_basic_init() */
-
-	/* Add device descriptor to FPGA device table */
-	socfpga_fpga_add();
 	return 0;
 }
 #else

index 71bae82..aba116d 100644
@@ -15,6 +15,7 @@
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>

@@ -208,6 +209,11 @@ void spl_board_init(void)
 
 	/* enable console uart printing */
 	preloader_console_init();
+
+	WATCHDOG_RESET();
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
 }
 
 void board_init_f(ulong dummy)

index aba116d..60159b2 100644
@@ -15,13 +15,19 @@
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/fpga_manager.h>
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
 #include <asm/sections.h>
+#include <environment.h>
 #include <fdtdec.h>
+#include <fat.h>
+#include <fs.h>
+#include <linux/ctype.h>
+#include <mmc.h>
 #include <watchdog.h>
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/pinmux.h>

@@ -29,6 +35,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BSIZE	4096
+#define PERIPH_RBF	0
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;

@@ -197,6 +206,12 @@ void board_init_f(ulong dummy)
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 void spl_board_init(void)
 {
+	int rval = 0;
+	int len = 0;
+	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
+	struct spl_boot_device bootdev;
+	fpga_fs_info fpga_fsinfo;
+
 	/* configuring the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
 	WATCHDOG_RESET();

@@ -214,6 +229,34 @@ void spl_board_init(void)
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
+
+	set_default_env(NULL);
+
+	bootdev.boot_device = spl_boot_device();
+
+	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
+		fpga_fsinfo.interface = "mmc";
+		fpga_fsinfo.fstype = FS_TYPE_FAT;
+	}
+
+	fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,
+							&len,
+							PERIPH_RBF);
+
+	fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob,
+						       &len);
+
+	if (fpga_fsinfo.dev_part)
+		env_set("FW_DEV_PART", fpga_fsinfo.dev_part);
+
+	/* Program peripheral RBF */
+	rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
+
+	if (!rval) {
+		config_pins(gd->fdt_blob, "shared");
+
+		ddr_calibration_sequence();
+	}
 }
 
 void board_init_f(ulong dummy)