Skip to contentSkip to conversation

arm: npcm: add basic support for Nuvoton BMCs

PATCH Superseded Tomer Maimon 2 participants 5 messages Dec 13, 2017 – Dec 15, 2017

Subsystems (4)

v1 of 12 Superseded Latest is v12 →

lore
Share & tools
lore

Tomer Maimon

author maintainer
#0 lore raw

cover arm: npcm: add basic support for Nuvoton BMCs

This patch set adds support for the Nuvoton NPCM Baseboard Management Controller (BMC) SoC architecture as well as the NPCM750 variant. NPCM is an ARM based SoC with external DDR RAM and supports a large set of peripherals.

The NPCM750 is based on Cortex A9 and comes in single core and dual core flavors.

The device tree added in this patchset has a number of bindings for which the corresponding drivers will be sent out later and thus do not yet have binding documentation. Apologies in advance if you would like the bindings to be added along with the corresponding drivers.

this patch set based on Brendan Higgins patcehs.
https://patchwork.kernel.org/project/linux-arm-kernel/list/?submitter=170155

Thanks!

Tomer Maimon (3):
arm: npcm: add basic support for Nuvoton BMCs
arm: dts: add Nuvoton NPCM750 device tree
MAINTAINERS: Add entry for Nuvoton NPCM architecture

 MAINTAINERS                                 |   13 +
 arch/arm/Kconfig                            |    2 +
 arch/arm/Makefile                           |    1 +
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts   |  468 +++++++++++
 arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi |  877 ++++++++++++++++++++
 arch/arm/boot/dts/nuvoton-npcm750.dtsi      | 1189 +++++++++++++++++++++++++++
 arch/arm/configs/PolegSVB_defconfig         |  428 ++++++++++
 arch/arm/mach-npcm/Kconfig                  |   61 ++
 arch/arm/mach-npcm/Makefile                 |    6 +
 arch/arm/mach-npcm/headsmp.S                |   22 +
 arch/arm/mach-npcm/npcm7xx.c                |   27 +
 arch/arm/mach-npcm/platsmp.c                |   86 ++
 12 files changed, 3180 insertions(+)
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
 create mode 100644 arch/arm/configs/PolegSVB_defconfig
 create mode 100644 arch/arm/mach-npcm/Kconfig
 create mode 100644 arch/arm/mach-npcm/Makefile
 create mode 100644 arch/arm/mach-npcm/headsmp.S
 create mode 100644 arch/arm/mach-npcm/npcm7xx.c
 create mode 100644 arch/arm/mach-npcm/platsmp.c
Signature · 1 line
2.14.1
author maintainer
#1 lore raw

PATCH 1/3 arm: npcm: add basic support for Nuvoton BMCs

Adds basic support for the Nuvoton NPCM750 BMC.

Based on [v8,1/3] arm: npcm: add basic support for Nuvoton BMCs patch:
Brendan Higgins : - https://patchwork.kernel.org/patch/10063409/

---
 arch/arm/Kconfig                    |   2 +
 arch/arm/Makefile                   |   1 +
 arch/arm/configs/PolegSVB_defconfig | 428 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-npcm/Kconfig          |  61 +++++
 arch/arm/mach-npcm/Makefile         |   6 +
 arch/arm/mach-npcm/headsmp.S        |  22 ++
 arch/arm/mach-npcm/npcm7xx.c        |  27 +++
 arch/arm/mach-npcm/platsmp.c        |  86 ++++++++
 8 files changed, 633 insertions(+)
 create mode 100644 arch/arm/configs/PolegSVB_defconfig
 create mode 100644 arch/arm/mach-npcm/Kconfig
 create mode 100644 arch/arm/mach-npcm/Makefile
 create mode 100644 arch/arm/mach-npcm/headsmp.S
 create mode 100644 arch/arm/mach-npcm/npcm7xx.c
 create mode 100644 arch/arm/mach-npcm/platsmp.c
arch/arm/Kconfig +2 -0
index 61a0cb15067e..05543f1cfbde 100644
@@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
 
+source "arch/arm/mach-npcm/Kconfig"
+
 source "arch/arm/mach-nspire/Kconfig"
 
 source "arch/arm/plat-omap/Kconfig"
arch/arm/Makefile +1 -0
index 47d3a1ab08d2..60ca50c7d762 100644
@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK)		+= mediatek
 machine-$(CONFIG_ARCH_MXS)		+= mxs
 machine-$(CONFIG_ARCH_NETX)		+= netx
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_NPCM)		+= npcm
 machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
 machine-$(CONFIG_ARCH_OXNAS)		+= oxnas
 machine-$(CONFIG_ARCH_OMAP1)		+= omap1
arch/arm/configs/PolegSVB_defconfig new file +428 -0

428 lines not on this page · raw message

arch/arm/mach-npcm/Kconfig new file +61 -0

61 lines not on this page · raw message

arch/arm/mach-npcm/Makefile new file +6 -0
new file mode 100644
index 000000000000..37f05e4bd0b3
@@ -0,0 +1,6 @@
+AFLAGS_headsmp.o		+= -march=armv7-a
+
+obj-$(CONFIG_ARCH_NPCM7XX)	+= npcm7xx.o
+obj-$(CONFIG_ARCH_NPCM750)	+= platsmp.o headsmp.o
+
+
arch/arm/mach-npcm/headsmp.S new file +22 -0
new file mode 100644
index 000000000000..5456268453f0
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017 Nuvoton Technology corporation.
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+
+/*
+ * The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
+ * here.
+ */
+ENTRY(npcm7xx_secondary_startup)
+	safe_svcmode_maskall r0
+
+	b	secondary_startup
+ENDPROC(npcm7xx_secondary_startup)
arch/arm/mach-npcm/npcm7xx.c new file +27 -0
new file mode 100644
index 000000000000..fa1759b85300
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 Nuvoton Technology corporation.
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static const char *const npcm7xx_dt_match[] = {
+	"nuvoton,npcm750",
+	NULL
+};
+
+DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
+	.atag_offset	= 0x100,
+	.dt_compat	= npcm7xx_dt_match,
+	.l2c_aux_val	= 0x0,
+	.l2c_aux_mask	= ~0x0,
+MACHINE_END
arch/arm/mach-npcm/platsmp.c new file +86 -0

86 lines not on this page · raw message

Signature · 1 line
2.14.1
#2 lore raw
Quoted 10 lines · Tomer Maimon

Adds basic support for the Nuvoton NPCM750 BMC.

Based on [v8,1/3] arm: npcm: add basic support for Nuvoton BMCs patch:
Brendan Higgins : - https://patchwork.kernel.org/patch/10063409/

---
 arch/arm/Kconfig                    |   2 +
 arch/arm/Makefile                   |   1 +
 arch/arm/configs/PolegSVB_defconfig | 428 ++++++++++++++++++++++++++++++++++++

Convention is to use lowercase for the filename. Please put the defconfig in a separate patch.

arch/arm/configs/PolegSVB_defconfig

Quoted 18 lines
 arch/arm/mach-npcm/Kconfig          |  61 +++++
 arch/arm/mach-npcm/Makefile         |   6 +
 arch/arm/mach-npcm/headsmp.S        |  22 ++
 arch/arm/mach-npcm/npcm7xx.c        |  27 +++
 arch/arm/mach-npcm/platsmp.c        |  86 ++++++++
 8 files changed, 633 insertions(+)
 create mode 100644 arch/arm/configs/PolegSVB_defconfig
 create mode 100644 arch/arm/mach-npcm/Kconfig
 create mode 100644 arch/arm/mach-npcm/Makefile
 create mode 100644 arch/arm/mach-npcm/headsmp.S
 create mode 100644 arch/arm/mach-npcm/npcm7xx.c
 create mode 100644 arch/arm/mach-npcm/platsmp.c
arch/arm/configs/PolegSVB_defconfig new file +0 -0
new file mode 100644
index 000000000000..149e422a24ef

The defconfig should be the result of running "make savedefconfig". This produces a file called "defconfig" that you can copy to arch/arm/configs/poleg_svb_defconfig and commit.

This is the same process you should use when updating the defconfig:

make ARCH=arm poleg_svb_defconfig
// update config options
make ARCH=arm savedefconfig
cp defconfig arch/arm/configs/poleg_svb_defconfig git commit -vsm "ARM: configs: npcmu: update defconfig"

Cheers,

Joel

author maintainer
#3 lore raw

PATCH 2/3 arm: dts: add Nuvoton NPCM750 device tree

In reply to Tomer Maimon

Add full device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board.

Based on [v8,2/3] arm: dts: add Nuvoton NPCM750 device tree patch:
Brendan Higgins : - https://patchwork.kernel.org/patch/10063497/

---
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts   |  468 +++++++++++
 arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi |  877 ++++++++++++++++++++
 arch/arm/boot/dts/nuvoton-npcm750.dtsi      | 1189 +++++++++++++++++++++++++++
 3 files changed, 2534 insertions(+)
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
arch/arm/boot/dts/nuvoton-npcm750-evb.dts new file +468 -0
new file mode 100644
index 000000000000..211909e1075e
@@ -0,0 +1,468 @@
+/*
+ * DTS file for all NPCM750 SoCs
+ *
+ * Copyright (c) 2017 Nuvoton Technology corporation.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "nuvoton-npcm750.dtsi"
+#include "nuvoton-npcm750-gpio.dtsi"
+
+/ {
+	model = "Nuvoton npcm750 Development Board (Device Tree)";
+	compatible = "nuvoton,npcm750";
+
+	aliases {
+		ethernet0 = &emc0;
+		ethernet1 = &emc1;
+		ethernet2 = &gmac0;
+		ethernet3 = &gmac1;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		udc0 = &udc0;
+		udc1 = &udc1;
+		udc2 = &udc2;
+		udc3 = &udc3;
+		udc4 = &udc4;
+		udc5 = &udc5;
+		udc6 = &udc6;
+		udc7 = &udc7;
+		udc8 = &udc8;
+		udc9 = &udc9;
+		emmc0 = &sdhci0;
+		emmc1 = &sdhci1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		i2c9 = &i2c9;
+		i2c10 = &i2c10;
+		i2c11 = &i2c11;
+		i2c12 = &i2c12;
+		i2c13 = &i2c13;
+		i2c14 = &i2c14;
+		i2c15 = &i2c15;
+	};
+
+	chosen {
+		stdout-path = &serial3;
+	};
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+	gmac0: eth@f0802000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&rg1_pins
+						 &rg1mdio_pins>;
+			phy-mode = "rgmii-id";
+			status = "okay";
+		};
+
+		gmac1: eth@f0804000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&rg2_pins
+						 &rg2mdio_pins>;
+			phy-mode = "rgmii-id";
+			status = "okay";
+		};
+
+		emc0: eth@f0825000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&r1_pins
+						 &r1err_pins
+						 &r1md_pins>;
+			phy-mode = "rmii";
+			status = "okay";
+		};
+
+		emc1: eth@f0826000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&r2_pins
+						 &r2err_pins
+						 &r2md_pins>;
+			phy-mode = "rmii";
+			status = "okay";
+		};
+
+		ehci1: ehci@f0806000 {
+			status = "okay";
+		};
+
+		ohci1: ohci@f0807000 {
+			status = "okay";
+		};
+
+		udc0:udc@f0830000 {
+			status = "okay";
+		};
+
+		udc1:udc@f0831000 {
+			status = "okay";
+		};
+
+		udc2:udc@f0832000 {
+			status = "okay";
+		};
+
+		udc3:udc@f0833000 {
+			status = "okay";
+		};
+
+		udc4:udc@f0834000 {
+			status = "okay";
+		};
+
+		udc5:udc@f0835000 {
+			status = "okay";
+		};
+
+		udc6:udc@f0836000 {
+			status = "okay";
+		};
+
+		udc7:udc@f0837000 {
+			status = "okay";
+		};
+
+		udc8:udc@f0838000 {
+			status = "okay";
+		};
+
+		udc9:udc@f0839000 {
+			status = "okay";
+		};
+
+		aes:aes@f0858000 {
+			status = "okay";
+		};
+
+		sha:sha@f085a000 {
+			status = "okay";
+		};
+
+		spi0: spi@fb000000 {
+			spi-nor@0 {
+				partitions@80000000 {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+					bbuboot1@0 {
+						label = "bb-uboot-1";
+						reg = <0x0000000 0x80000>;
+						read-only;
+						};
+					bbuboot2@80000 {
+						label = "bb-uboot-2";
+						reg = <0x0080000 0x80000>;
+						read-only;
+						};
+					envparam@100000 {
+						label = "env-param";
+						reg = <0x0100000 0x40000>;
+						read-only;
+						};
+					spare@140000 {
+						label = "spare";
+						reg = <0x0140000 0xC0000>;
+						};
+					kernel@200000 {
+						label = "kernel";
+						reg = <0x0200000 0x400000>;
+						};
+					rootfs@600000 {
+						label = "rootfs";
+						reg = <0x0600000 0x700000>;
+						};
+					spare1@D00000 {
+						label = "spare1";
+						reg = <0x0D00000 0x200000>;
+						};
+					spare2@0F00000 {
+						label = "spare2";
+						reg = <0x0F00000 0x200000>;
+						};
+					spare3@1100000 {
+						label = "spare3";
+						reg = <0x1100000 0x200000>;
+						};
+					spare4@1300000 {
+						label = "spare4";
+						reg = <0x1300000 0x0>;
+					};
+				};
+			};
+		};
+
+		spi3: spi@c0000000 {
+				spi-nor@0 {
+				partitions@A0000000 {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+					spare@0 {
+						label = "spare-1";
+						reg = <0x0 0x0>;
+					};
+				};
+			};
+		};
+
+		sdhci0: sdhci@f0840000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&sd1_pins>;
+			status = "okay";
+		};
+
+		sdhci1: sdhci@f0842000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc8_pins
+				     &mmc_pins>;
+			status = "okay";
+		};
+
+	};
+	apb {
+
+		watchdog1: watchdog@f0009000 {
+			status = "okay";
+		};
+
+		rng: rng@f000b000 {
+			status = "okay";
+		};
+
+		serial0: serial0@f0001000 {
+			status = "okay";
+		};
+
+		serial1: serial1@f0002000 {
+			status = "okay";
+		};
+
+		serial2: serial2@f0003000 {
+			status = "okay";
+		};
+
+		serial3: serial3@f0004000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_pins>;
+			status = "okay";
+		};
+
+		otp:otp@f0189000 {
+			status = "okay";
+		};
+
+		/* lm75 on SVB */
+		i2c0: i2c-bus@f0080000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			lm75@48 {
+				compatible = "lm75";
+				reg = <0x48>;
+				status = "okay";
+			};
+		};
+
+		/* lm75 on EB */
+		i2c1: i2c-bus@f0081000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			lm75@48 {
+				compatible = "lm75";
+				reg = <0x48>;
+				status = "okay";
+			};
+		};
+
+		/* tmp100 on EB */
+		i2c2: i2c-bus@f0082000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			tmp100@48 {
+				compatible = "tmp100";
+				reg = <0x48>;
+				status = "okay";
+			};
+		};
+
+		/* tmp100 on SVB */
+		i2c6: i2c-bus@f0086000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			tmp100@48 {
+				compatible = "tmp100";
+				reg = <0x48>;
+				status = "okay";
+			};
+		};
+
+		i2c3: i2c-bus@f0083000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c4: i2c-bus@f0084000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c5: i2c-bus@f0085000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c7: i2c-bus@f0087000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c8: i2c-bus@f0088000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c9: i2c-bus@f0089000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c10: i2c-bus@f008a000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c11: i2c-bus@f008b000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c14: i2c-bus@f008e000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c15: i2c-bus@f008f000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		mft: mft@0 {
+			pinctrl-names = "default";
+			pinctrl-0 = <	&fanin0_pins
+					&fanin1_pins
+					&fanin2_pins
+					&fanin3_pins
+					&fanin4_pins
+					&fanin5_pins
+					&fanin6_pins
+					&fanin7_pins
+					&fanin8_pins
+					&fanin9_pins
+					&fanin10_pins
+					&fanin11_pins
+					&fanin12_pins
+					&fanin13_pins
+					&fanin14_pins
+					&fanin15_pins>;
+			status = "okay";
+			};
+		};
+
+		pinctrl: pinctrl@0 {
+			pinctrl-names = "default";
+			pinctrl-0 = <	&gpio0o_pins
+					&gpio1_pins
+					&gpio2o_pins
+					&gpio3_pins
+					&gpio8_pins
+					&gpio9o_pins
+					&gpio10_pins
+					&gpio11o_pins
+					&gpio16_pins
+					&gpio17_pins
+					&gpio24o_pins
+					&gpio25ol_pins
+					&gpio32o_pins
+					&spi0quad_pins
+					&jtag2_pins
+					&gpio61o_pins
+					&gpio62o_pins
+					&gpio63o_pins
+					&gpio80_pins
+					&gpio81_pins
+					&gpio82_pins
+					&gpio83_pins
+					&lpc_pins
+					&gpio132o_pins
+					&gpio133_pins
+					&gpio134_pins
+					&gpio135_pins
+					&gpio144_pins
+					&gpio145_pins
+					&gpio146_pins
+					&gpio147_pins
+					&gpio160_pins
+					&gpio162_pins
+					&gpio168_pins
+					&gpio169_pins
+					&gpio170_pins
+					&gpio175_pins
+					&gpio176_pins
+					&gpio177o_pins
+					&spi3_pins
+					&gpio187o_pins
+					&spi3quad_pins
+					&gpio190_pins
+					&gpio191o_pins
+					&gpio192o_pins
+					&gpio197ol_pins
+					&gpio203o_pins
+					&ddc_pins
+					&gpio218_pins
+					&gpio219ol_pins
+					&gpio220ol_pins
+					&gpio221o_pins
+					&gpio222_pins
+					&gpio223ol_pins
+					&spix_pins
+					&gpio228ol_pins
+					&gpio231o_pins
+					&gpio255_pins>;
+		};
+};
arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi new file +877 -0

877 lines not on this page · raw message

arch/arm/boot/dts/nuvoton-npcm750.dtsi new file +1189 -0

1,189 lines not on this page · raw message

Signature · 1 line
2.14.1
author maintainer
#4 lore raw

PATCH 3/3 MAINTAINERS: Add entry for Nuvoton NPCM architecture

In reply to Tomer Maimon

Add maintainers and reviewers for Nuvoton NPCM architecture

Based on [v8,3/3] MAINTAINERS: Add entry for Nuvoton NPCM architecture patch:
Brendan Higgins : - https://patchwork.kernel.org/patch/10063413/

---
 MAINTAINERS | 13 +++++++++++++
 1 file changed, 13 insertions(+)
MAINTAINERS +13 -0
index 1c3feffb1c1c..9b90748b729d 100644
@@ -1598,6 +1598,19 @@ F:	drivers/pinctrl/nomadik/
 F:	drivers/i2c/busses/i2c-nomadik.c
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
 
+ARM/NUVOTON NPCM ARCHITECTURE
+M:	Avi Fishman <[email protected]>
+M:	Tomer Maimon <[email protected]>
+R:	Brendan Higgins <[email protected]>
+R:	Rick Altherr <[email protected]>
+L:	[email protected] (moderated for non-subscribers)
+S:	Supported
+F:	arch/arm/mach-npcm/
+F:	arch/arm/boot/dts/nuvoton-npcm*
+F:	include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
+F:	drivers/*/*npcm*
+F:	Documentation/*/*npcm*
+
 ARM/NUVOTON W90X900 ARM ARCHITECTURE
 M:	Wan ZongShun <[email protected]>
 L:	[email protected] (moderated for non-subscribers)
Signature · 1 line
2.14.1