eSPI: add Aspeed AST2500 eSPI driver to boot a host with PCH runs on eSPI

The PCH (master) provides the eSPI to support connection of a BMC (slave) to the platform.

The LPC and eSPI interfaces are mutually exclusive. Both use the same pins, but on power-up, a HW strap determines if the eSPI or the LPC bus is operational. Once selected, it’s not possible to change to the other interface.

eSPI Channels and Supported Transactions:

+------+---------------------+----------------------+--------------------+
| CH # | Channel             | Posted Cycles        | Non-Posted Cycles  |
+------+---------------------+----------------------+--------------------+
|  0   | Peripheral          | Memory Write,        | Memory Read,       |
|      |                     | Completions          | I/O Read/Write     |
+------+---------------------+----------------------+--------------------+
|  1   | Virtual Wire        | Virtual Wire GET/PUT | N/A                |
+------+---------------------+----------------------+--------------------+
|  2   | Out-of-Band Message | SMBus Packet GET/PUT | N/A                |
+------+---------------------+----------------------+--------------------+
|  3   | Flash Access        | N/A                  | Flash Read, Write, |
|      |                     |                      | Erase              |
+------+---------------------+----------------------+--------------------+
|  N/A | General             | Register Accesses    | N/A                |
+------+---------------------+----------------------+--------------------+

Virtual Wire Channel (Channel 1) Overview
The Virtual Wire channel uses a standard message format to communicate several types of signals between the components on the platform.
- Sideband and GPIO Pins: System events and other dedicated signals between the PCH and eSPI slave. These signals are tunneled between the two components over eSPI.
- Serial IRQ Interrupts: Interrupts are tunneled from the eSPI slave to the PCH. Both edge and triggered interrupts are supported.

[This patch add the basic function to boot a host whose PCH runs on eSPI]

When PCH runs on eSPI mode, from BMC side, the following VW messages are done in firmware:
1. SLAVE_BOOT_LOAD_DONE / SLAVE_BOOT_LOAD_STATUS
2. SUS_ACK
3. OOB_RESET_ACK
4. HOST_RESET_ACK

+----------------------+---------+---------------------------------------+
|Virtual Wire          |PCH Pin  |Comments                               |
|                      |Direction|                                       |
+----------------------+---------+---------------------------------------+
|SUS_WARN#             |Output   |PCH pin is a GPIO when eSPI is enabled.|
|                      |         |eSPI controller receives as VW message.|
+----------------------+---------+---------------------------------------+
|SUS_ACK#              |Input    |PCH pin is a GPIO when eSPI is enabled.|
|                      |         |eSPI controller receives as VW message.|
+----------------------+---------+---------------------------------------+
|SLAVE_BOOT_LOAD_DONE  |Input    |Sent when the BMC has completed its    |
|                      |         |boot process as an indication to       |
|                      |         |eSPI-MC to continue with the G3 to S0  |
|                      |         |exit.                                  |
|                      |         |The eSPI Master waits for the assertion|
|                      |         |of this virtual wire before proceeding |
|                      |         |with the SLP_S5# deassertion.          |
|                      |         |The intent is that it is never changed |
|                      |         |except on a G3 exit - it is reset on a |
|                      |         |G3 entry.                              |
+----------------------+---------+---------------------------------------+
|SLAVE_BOOT_LOAD_STATUS|Input    |Sent upon completion of the Slave Boot |
|                      |         |Load from the attached flash. A stat of|
|                      |         |1 indicates that the boot code load was|
|                      |         |successful and that the integrity of   |
|                      |         |the image is intact.                   |
+----------------------+---------+---------------------------------------+
|HOST_RESET_WARN       |Output   |Sent from the MC just before the Host  |
|                      |         |is about to enter reset. Upon receiving|
|                      |         |, the BMC must flush and quiesce its   |
|                      |         |upstream Peripheral Channel request    |
|                      |         |queues and assert HOST_RESET_ACK VWire.|
|                      |         |The MC subsequently completes any      |
|                      |         |outstanding posted transactions or     |
|                      |         |completions and then disables the      |
|                      |         |Peripheral Channel via a write to      |
|                      |         |the Slave's Configuration Register.    |
+----------------------+---------+---------------------------------------+
|HOST_RESET_ACK        |Input    |ACK for the HOST_RESET_WARN message    |
+----------------------+---------+---------------------------------------+
|OOB_RESET_WARN        |Output   |Sent from the MC just before the OOB   |
|                      |         |processor is about to enter reset. Upon|
|                      |         |receiving, the BMC must flush and      |
|                      |         |quiesce its OOB Channel upstream       |
|                      |         |request queues and assert OOB_RESET_ACK|
|                      |         |VWire. The-MC subsequently completes   |
|                      |         |any outstanding posted transactions or |
|                      |         |completions and then disables the OOB  |
|                      |         |Channel via a write to the Slave's     |
|                      |         |Configuration Register.                |
+----------------------+---------+---------------------------------------+
|OOB_RESET_ACK         |Input    |ACK for OOB_RESET_WARN message         |
+----------------------+---------+---------------------------------------+

---
 .../devicetree/bindings/misc/aspeed-espi-slave.txt |  32 +++
 drivers/misc/Kconfig                               |  11 +
 drivers/misc/Makefile                              |   1 +
 drivers/misc/aspeed-espi-slave.c                   | 264 +++++++++++++++++++++
 4 files changed, 308 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/aspeed-espi-slave.txt
 create mode 100644 drivers/misc/aspeed-espi-slave.c

new file mode 100644
index 0000000..0db889b
@@ -0,0 +1,32 @@
+Aspeed eSPI Slave Controller
+
+Enhanced Serial Peripheral Interface (eSPI) is an interface using pins of SPI,
+but runs different protocol.
+
+Its interface supports peripheral, virtual wire, out-of-band, and flash sharing
+channels.
+
+ -- https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0.pdf
+    Enhanced Serial Peripheral Interface (eSPI)
+    Interface Base Specification (for Client and Server Platforms)
+    January 2016
+    Revision 1.0
+
+Required properties:
+ - compatible: must be one of:
+	- "aspeed,ast2500-espi-slave"
+
+ - reg: physical base address of the controller and length of memory mapped
+   region
+
+ - interrupts: interrupt generated by the controller
+
+Example:
+
+    espi: espi@1e6ee000 {
+        compatible = "aspeed,ast2500-espi-slave";
+        reg = <0x1e6ee000 0x100>;
+        interrupts = <23>;
+        status = "disabled";
+};
+

index 02ffdd1..8c0d791 100644
@@ -766,6 +766,17 @@ config PANEL_BOOT_MESSAGE
 	  An empty message will only clear the display at driver init time. Any other
 	  printf()-formatted message is valid with newline and escape codes.
 
+config ASPEED_ESPI_SLAVE
+	depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP
+	tristate "Aspeed ast2500 eSPI slave device"
+	---help---
+	  This allows host to access Baseboard Management Controller (BMC) over the
+	  Enhanced Serial Peripheral Interface (eSPI) bus, which replaces the Low Pin
+	  Count (LPC) bus.
+
+	  Its interface supports peripheral, virtual wire, out-of-band, and flash
+	  sharing channels.
+
 config ASPEED_LPC_CTRL
 	depends on (ARCH_ASPEED || COMPILE_TEST) && REGMAP && MFD_SYSCON
 	tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"

index ab8af76..a648599 100644
@@ -53,6 +53,7 @@ obj-$(CONFIG_ECHO)		+= echo/
 obj-$(CONFIG_VEXPRESS_SYSCFG)	+= vexpress-syscfg.o
 obj-$(CONFIG_CXL_BASE)		+= cxl/
 obj-$(CONFIG_PANEL)             += panel.o
+obj-$(CONFIG_ASPEED_ESPI_SLAVE) += aspeed-espi-slave.o
 obj-$(CONFIG_ASPEED_LPC_CTRL)	+= aspeed-lpc-ctrl.o
 obj-$(CONFIG_ASPEED_LPC_SNOOP)	+= aspeed-lpc-snoop.o
 

2.7.4