Patch "x86/mm: Add INVPCID helpers" has been added to the 4.4-stable tree
Subsystems (2)
This is a note to let you know that I've just added the patch titled
x86/mm: Add INVPCID helpers
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
x86-mm-add-invpcid-helpers.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
060a402a1ddb551455ee410de2eadd3349f2801bMon Sep 17 00:00:00 2001
From: Andy Lutomirski <[email protected]>
Date: Fri, 29 Jan 2016 11:42:57 -0800
Subject: x86/mm: Add INVPCID helpers
From: Andy Lutomirski <[email protected]>
commit 060a402a1ddb551455ee410de2eadd3349f2801b upstream.
This adds helpers for each of the four currently-specified INVPCID modes.
--- arch/x86/include/asm/tlbflush.h | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
arch/x86/include/asm/tlbflush.h +48 -0
@@ -7,6 +7,54 @@#include <asm/processor.h> #include <asm/special_insns.h> +static inline void __invpcid (unsigned long pcid,unsigned long addr, +unsigned long type) +{ +u64 desc[2 ] = { pcid, addr }; + +/* +* The memory clobber is because the whole point is to invalidate +* stale TLB entries and, especially if we're flushing global +* mappings, we don't want the compiler to reorder any subsequent +* memory accesses before the TLB flush. +* +* The hex opcode is invpcid (%ecx), %eax in 32-bit mode and +* invpcid (%rcx), %rax in long mode. +*/ + asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" + : :"m" (desc),"a" (type),"c" (desc) :"memory" ); +} + +#define INVPCID_TYPE_INDIV_ADDR 0 +#define INVPCID_TYPE_SINGLE_CTXT 1 +#define INVPCID_TYPE_ALL_INCL_GLOBAL 2 +#define INVPCID_TYPE_ALL_NON_GLOBAL 3 + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invpcid_flush_one (unsigned long pcid, +unsigned long addr) +{ +__invpcid (pcid, addr,INVPCID_TYPE_INDIV_ADDR ); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invpcid_flush_single_context (unsigned long pcid) +{ +__invpcid (pcid,0 ,INVPCID_TYPE_SINGLE_CTXT ); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invpcid_flush_all (void ) +{ +__invpcid (0 ,0 ,INVPCID_TYPE_ALL_INCL_GLOBAL ); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invpcid_flush_all_nonglobals (void ) +{ +__invpcid (0 ,0 ,INVPCID_TYPE_ALL_NON_GLOBAL ); +} +#ifdef CONFIG_PARAVIRT #include <asm/paravirt.h> #else
Patches currently in stable-queue which might be from [email protected] are
queue-4.4/x86-mm-sched-core-uninline-switch_mm.patch queue-4.4/x86-mm-add-a-noinvpcid-boot-option-to-turn-off-invpcid.patch queue-4.4/x86-irq-do-not-substract-irq_tlb_count-from-irq_call_count.patch queue-4.4/x86-mm-if-invpcid-is-available-use-it-to-flush-global-mappings.patch queue-4.4/x86-mm-add-invpcid-helpers.patch queue-4.4/sched-core-add-switch_mm_irqs_off-and-use-it-in-the-scheduler.patch queue-4.4/arm-hide-finish_arch_post_lock_switch-from-modules.patch queue-4.4/x86-mm-sched-core-turn-off-irqs-in-switch_mm.patch queue-4.4/mm-mmu_context-sched-core-fix-mmu_context.h-assumption.patch queue-4.4/x86-mm-build-arch-x86-mm-tlb.c-even-on-smp.patch queue-4.4/sched-core-idle_task_exit-shouldn-t-use-switch_mm_irqs_off.patch