Patch "x86/mm: Enable CR4.PCIDE on supported systems" has been added to the 4.4-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
x86/mm: Enable CR4.PCIDE on supported systems
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
x86-mm-enable-cr4.pcide-on-supported-systems.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
660da7c9228f685b2ebe664f9fd69aaddcc420b5Mon Sep 17 00:00:00 2001
From: Andy Lutomirski <[email protected]>
Date: Thu, 29 Jun 2017 08:53:21 -0700
Subject: x86/mm: Enable CR4.PCIDE on supported systems
From: Andy Lutomirski <[email protected]>
commit 660da7c9228f685b2ebe664f9fd69aaddcc420b5 upstream.
We can use PCID if the CPU has PCID and PGE and we're not on Xen.
By itself, this has no effect. A followup patch will start using PCID.
--- arch/x86/include/asm/tlbflush.h | 8 ++++++++ arch/x86/kernel/cpu/common.c | 22 ++++++++++++++++++++++ arch/x86/xen/enlighten.c | 6 ++++++ 3 files changed, 36 insertions(+)
arch/x86/include/asm/tlbflush.h +8 -0
@@ -190,6 +190,14 @@ static inline void __flush_tlb_all(void)__flush_tlb_global (); else__flush_tlb (); + +/* +* Note: if we somehow had PCID but not PGE, then this wouldn't work -- +* we'd end up flushing kernel translations for the current ASID but +* we might fail to flush kernel translations for other cached ASIDs. +* +* To avoid this issue, we force PCID off if PGE is off. +*/ }static inline void __flush_tlb_one (unsigned long addr)
arch/x86/kernel/cpu/common.c +22 -0
@@ -321,6 +321,25 @@ static __always_inline void setup_smap(s } } +static void setup_pcid (struct cpuinfo_x86 *c) +{ +if (cpu_has (c,X86_FEATURE_PCID )) { +if (cpu_has (c,X86_FEATURE_PGE )) { +cr4_set_bits (X86_CR4_PCIDE ); + }else { +/* +* flush_tlb_all(), as currently implemented, won't +* work if PCID is on but PGE is not. Since that +* combination doesn't exist on real hardware, there's +* no reason to try to fully support it, but it's +* polite to avoid corrupting data if we're on +* an improperly configured VM. +*/ +clear_cpu_cap (c,X86_FEATURE_PCID ); + } + } +} +/* * Some CPU features depend on higher CPUID levels, which may not always * be available due to CPUID level capping or broken virtualization
@@ -952,6 +971,9 @@ static void identify_cpu(struct cpuinfo_setup_smep (c);setup_smap (c); +/* Set up PCID */ +setup_pcid (c); +/* * The vendor-specific functions might have changed features. * Now we do "generic changes."
arch/x86/xen/enlighten.c +6 -0
@@ -433,6 +433,12 @@ static void __init xen_init_cpuid_mask(v ~((1 <<X86_FEATURE_MTRR ) |/* disable MTRR */ (1 <<X86_FEATURE_ACC ));/* thermal monitoring */ +/* +* Xen PV would need some work to support PCID: CR3 handling as well +* as xen_flush_tlb_others() would need updating. +*/ + cpuid_leaf1_ecx_mask &= ~(1 <<X86_FEATURE_PCID );/* disable PCID */ +if (!xen_initial_domain ()) cpuid_leaf1_edx_mask &= ~((1 <<X86_FEATURE_ACPI ));/* disable ACPI */
Patches currently in stable-queue which might be from [email protected] are
queue-4.4/x86-vm86-32-switch-to-flush_tlb_mm_range-in-mark_screen_rdonly.patch queue-4.4/x86-mm-add-the-nopcid-boot-option-to-turn-off-pcid.patch queue-4.4/x86-mm-enable-cr4.pcide-on-supported-systems.patch queue-4.4/x86-mm-remove-the-up-asm-tlbflush.h-code-always-use-the-formerly-smp-code.patch queue-4.4/x86-mm-reimplement-flush_tlb_page-using-flush_tlb_mm_range.patch queue-4.4/x86-mm-make-flush_tlb_mm_range-more-predictable.patch queue-4.4/x86-mm-remove-flush_tlb-and-flush_tlb_current_task.patch queue-4.4/x86-mm-disable-pcid-on-32-bit-kernels.patch queue-4.4/x86-mm-64-fix-reboot-interaction-with-cr4.pcide.patch