Patch "drm/i915: Move init_clock_gating() back to where it was" has been added to the 4.14-stable tree

This is a note to let you know that I've just added the patch titled

drm/i915: Move init_clock_gating() back to where it was

to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-i915-move-init_clock_gating-back-to-where-it-was.patch
and it can be found in the queue-4.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <[email protected]>
Date: Wed, 8 Nov 2017 15:35:55 +0200
Subject: drm/i915: Move init_clock_gating() back to where it was
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From: Ville Syrjälä <[email protected]>

commit 6ac43272768ca901daac4076a66c2c4e3c7b9321 upstream.

Apparently setting up a bunch of GT registers before we've properly initialized the rest of the GT hardware leads to these setting being lost. So looks like I broke HSW with commit b7048ea12fbb ("drm/i915:
Do .init_clock_gating() earlier to avoid it clobbering watermarks") by doing init_clock_gating() too early. This should actually affect other platforms as well, but apparently not to such a great degree.

What I was ultimately after in that commit was to move the ilk_init_lp_watermarks() call earlier. So let's undo the damage and move init_clock_gating() back to where it was, and call ilk_init_lp_watermarks() just before the watermark state readout.

This highlights how fragile and messed up our init order really is. I wonder why we even initialize the display before gem. The opposite order would make much more sense to me...

v2: Keep WaRsPkgCStateDisplayPMReq:hsw early as it really must
be done before all planes might get disabled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103549

References: https://lists.freedesktop.org/archives/intel-gfx/2017-November/145432.html

---
 drivers/gpu/drm/i915/intel_display.c |   14 +++++++++--
 drivers/gpu/drm/i915/intel_pm.c      |   44 ++++++++++++++---------------------
 2 files changed, 30 insertions(+), 28 deletions(-)

@@ -3800,6 +3800,7 @@ void intel_finish_reset(struct drm_i915_
 
 		intel_pps_unlock_regs_wa(dev_priv);
 		intel_modeset_init_hw(dev);
+		intel_init_clock_gating(dev_priv);
 
 		spin_lock_irq(&dev_priv->irq_lock);
 		if (dev_priv->display.hpd_irq_setup)

@@ -14406,8 +14407,6 @@ void intel_modeset_init_hw(struct drm_de
 
 	intel_update_cdclk(dev_priv);
 	dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
-
-	intel_init_clock_gating(dev_priv);
 }
 
 /*

@@ -15124,6 +15123,15 @@ intel_modeset_setup_hw_state(struct drm_
 	struct intel_encoder *encoder;
 	int i;
 
+	if (IS_HASWELL(dev_priv)) {
+		/*
+		 * WaRsPkgCStateDisplayPMReq:hsw
+		 * System hang if this isn't done before disabling all planes!
+		 */
+		I915_WRITE(CHICKEN_PAR1_1,
+			   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+	}
+
 	intel_modeset_readout_hw_state(dev);
 
 	/* HW state is read out, now we need to sanitize this mess. */

@@ -15220,6 +15228,8 @@ void intel_modeset_gem_init(struct drm_d
 
 	intel_init_gt_powersave(dev_priv);
 
+	intel_init_clock_gating(dev_priv);
+
 	intel_setup_overlay(dev_priv);
 }
 

Patches currently in stable-queue which might be from [email protected] are

queue-4.14/drm-i915-move-init_clock_gating-back-to-where-it-was.patch queue-4.14/drm-i915-fix-init_clock_gating-for-resume.patch