imx: mx25: Remove SION bit in all pin-mux that are safe
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdf
The software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIO
SION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
---
Changes V2->V3:
- SION pin -> SION bit
- mulfuction to malfunction
Changes V1->V2:
- some english typo
- avoid changes from 0x00 to 0 or 0x01 to 1 when are not needed
- preserve one SION bit on sdcard for a bug in silicon and add linux comment on it
--- arch/arm/include/asm/arch-mx25/iomux-mx25.h | 571 ++++++++++++++-------------- 1 file changed, 290 insertions(+), 281 deletions(-)
arch/arm/include/asm/arch-mx25/iomux-mx25.h +290 -281
@@ -36,59 +36,59 @@ enum {MX25_PAD_A13__A13 =IOMUX_PAD (0x22C ,0x00c ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_A13__GPIO_4_1 =IOMUX_PAD (0x22C ,0x00c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A14__A14 =IOMUX_PAD (0x230 ,0x010 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A14__GPIO_2_0 =IOMUX_PAD (0x230 ,0x010 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A14__A14 =IOMUX_PAD (0x230 ,0x010 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A14__GPIO_2_0 =IOMUX_PAD (0x230 ,0x010 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A15__A15 =IOMUX_PAD (0x234 ,0x014 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A15__GPIO_2_1 =IOMUX_PAD (0x234 ,0x014 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A15__A15 =IOMUX_PAD (0x234 ,0x014 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A15__GPIO_2_1 =IOMUX_PAD (0x234 ,0x014 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A16__A16 =IOMUX_PAD (0x000 ,0x018 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A16__GPIO_2_2 =IOMUX_PAD (0x000 ,0x018 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A16__A16 =IOMUX_PAD (0x000 ,0x018 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A16__GPIO_2_2 =IOMUX_PAD (0x000 ,0x018 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A17__A17 =IOMUX_PAD (0x238 ,0x01c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A17__GPIO_2_3 =IOMUX_PAD (0x238 ,0x01c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A17__A17 =IOMUX_PAD (0x238 ,0x01c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A17__GPIO_2_3 =IOMUX_PAD (0x238 ,0x01c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A18__A18 =IOMUX_PAD (0x23c ,0x020 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A18__GPIO_2_4 =IOMUX_PAD (0x23c ,0x020 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A18__FEC_COL =IOMUX_PAD (0x23c ,0x020 ,0x17 ,0x504 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A18__A18 =IOMUX_PAD (0x23c ,0x020 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A18__GPIO_2_4 =IOMUX_PAD (0x23c ,0x020 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A18__FEC_COL =IOMUX_PAD (0x23c ,0x020 ,0x07 ,0x504 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A19__A19 =IOMUX_PAD (0x240 ,0x024 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A19__FEC_RX_ER =IOMUX_PAD (0x240 ,0x024 ,0x17 ,0x518 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A19__GPIO_2_5 =IOMUX_PAD (0x240 ,0x024 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A19__A19 =IOMUX_PAD (0x240 ,0x024 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A19__FEC_RX_ER =IOMUX_PAD (0x240 ,0x024 ,0x07 ,0x518 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A19__GPIO_2_5 =IOMUX_PAD (0x240 ,0x024 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A20__A20 =IOMUX_PAD (0x244 ,0x028 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A20__GPIO_2_6 =IOMUX_PAD (0x244 ,0x028 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A20__FEC_RDATA2 =IOMUX_PAD (0x244 ,0x028 ,0x17 ,0x50c ,0 ,NO_PAD_CTRL ), +MX25_PAD_A20__A20 =IOMUX_PAD (0x244 ,0x028 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A20__GPIO_2_6 =IOMUX_PAD (0x244 ,0x028 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A20__FEC_RDATA2 =IOMUX_PAD (0x244 ,0x028 ,0x07 ,0x50c ,0 ,NO_PAD_CTRL ), -MX25_PAD_A21__A21 =IOMUX_PAD (0x248 ,0x02c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A21__GPIO_2_7 =IOMUX_PAD (0x248 ,0x02c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A21__FEC_RDATA3 =IOMUX_PAD (0x248 ,0x02c ,0x17 ,0x510 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A21__A21 =IOMUX_PAD (0x248 ,0x02c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A21__GPIO_2_7 =IOMUX_PAD (0x248 ,0x02c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A21__FEC_RDATA3 =IOMUX_PAD (0x248 ,0x02c ,0x07 ,0x510 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A22__A22 =IOMUX_PAD (0x000 ,0x030 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A22__GPIO_2_8 =IOMUX_PAD (0x000 ,0x030 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A22__A22 =IOMUX_PAD (0x000 ,0x030 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A22__GPIO_2_8 =IOMUX_PAD (0x000 ,0x030 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A23__A23 =IOMUX_PAD (0x24c ,0x034 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A23__GPIO_2_9 =IOMUX_PAD (0x24c ,0x034 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A23__A23 =IOMUX_PAD (0x24c ,0x034 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A23__GPIO_2_9 =IOMUX_PAD (0x24c ,0x034 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A24__A24 =IOMUX_PAD (0x250 ,0x038 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A24__GPIO_2_10 =IOMUX_PAD (0x250 ,0x038 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A24__FEC_RX_CLK =IOMUX_PAD (0x250 ,0x038 ,0x17 ,0x514 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A24__A24 =IOMUX_PAD (0x250 ,0x038 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A24__GPIO_2_10 =IOMUX_PAD (0x250 ,0x038 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A24__FEC_RX_CLK =IOMUX_PAD (0x250 ,0x038 ,0x07 ,0x514 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A25__A25 =IOMUX_PAD (0x254 ,0x03c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A25__GPIO_2_11 =IOMUX_PAD (0x254 ,0x03c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_A25__FEC_CRS =IOMUX_PAD (0x254 ,0x03c ,0x17 ,0x508 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A25__A25 =IOMUX_PAD (0x254 ,0x03c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A25__GPIO_2_11 =IOMUX_PAD (0x254 ,0x03c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_A25__FEC_CRS =IOMUX_PAD (0x254 ,0x03c ,0x07 ,0x508 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EB0__EB0 =IOMUX_PAD (0x258 ,0x040 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EB0__AUD4_TXD =IOMUX_PAD (0x258 ,0x040 ,0x14 ,0x464 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EB0__GPIO_2_12 =IOMUX_PAD (0x258 ,0x040 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EB0__EB0 =IOMUX_PAD (0x258 ,0x040 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EB0__AUD4_TXD =IOMUX_PAD (0x258 ,0x040 ,0x04 ,0x464 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EB0__GPIO_2_12 =IOMUX_PAD (0x258 ,0x040 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EB1__EB1 =IOMUX_PAD (0x25c ,0x044 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EB1__AUD4_RXD =IOMUX_PAD (0x25c ,0x044 ,0x14 ,0x460 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EB1__GPIO_2_13 =IOMUX_PAD (0x25c ,0x044 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EB1__EB1 =IOMUX_PAD (0x25c ,0x044 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EB1__AUD4_RXD =IOMUX_PAD (0x25c ,0x044 ,0x04 ,0x460 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EB1__GPIO_2_13 =IOMUX_PAD (0x25c ,0x044 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_OE__OE =IOMUX_PAD (0x260 ,0x048 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_OE__AUD4_TXC =IOMUX_PAD (0x260 ,0x048 ,0x14 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_OE__GPIO_2_14 =IOMUX_PAD (0x260 ,0x048 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_OE__OE =IOMUX_PAD (0x260 ,0x048 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_OE__AUD4_TXC =IOMUX_PAD (0x260 ,0x048 ,0x04 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_OE__GPIO_2_14 =IOMUX_PAD (0x260 ,0x048 ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CS0__CS0 =IOMUX_PAD (0x000 ,0x04c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
@@ -97,51 +97,51 @@ enum {MX25_PAD_CS1__NF_CE3 =IOMUX_PAD (0x000 ,0x050 ,0x01 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CS1__GPIO_4_3 =IOMUX_PAD (0x000 ,0x050 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CS4__CS4 =IOMUX_PAD (0x264 ,0x054 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CS4__CS4 =IOMUX_PAD (0x264 ,0x054 ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CS4__NF_CE1 =IOMUX_PAD (0x264 ,0x054 ,0x01 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CS4__UART5_CTS =IOMUX_PAD (0x264 ,0x054 ,0x13 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CS4__GPIO_3_20 =IOMUX_PAD (0x264 ,0x054 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CS4__UART5_CTS =IOMUX_PAD (0x264 ,0x054 ,0x03 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CS4__GPIO_3_20 =IOMUX_PAD (0x264 ,0x054 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CS5__CS5 =IOMUX_PAD (0x268 ,0x058 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CS5__CS5 =IOMUX_PAD (0x268 ,0x058 ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CS5__NF_CE2 =IOMUX_PAD (0x268 ,0x058 ,0x01 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CS5__UART5_RTS =IOMUX_PAD (0x268 ,0x058 ,0x13 ,0x574 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CS5__GPIO_3_21 =IOMUX_PAD (0x268 ,0x058 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CS5__UART5_RTS =IOMUX_PAD (0x268 ,0x058 ,0x03 ,0x574 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CS5__GPIO_3_21 =IOMUX_PAD (0x268 ,0x058 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NF_CE0__NF_CE0 =IOMUX_PAD (0x26c ,0x05c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NF_CE0__GPIO_3_22 =IOMUX_PAD (0x26c ,0x05c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NF_CE0__NF_CE0 =IOMUX_PAD (0x26c ,0x05c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NF_CE0__GPIO_3_22 =IOMUX_PAD (0x26c ,0x05c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_ECB__ECB =IOMUX_PAD (0x270 ,0x060 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_ECB__UART5_TXD_MUX =IOMUX_PAD (0x270 ,0x060 ,0x13 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_ECB__GPIO_3_23 =IOMUX_PAD (0x270 ,0x060 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_ECB__ECB =IOMUX_PAD (0x270 ,0x060 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_ECB__UART5_TXD_MUX =IOMUX_PAD (0x270 ,0x060 ,0x03 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_ECB__GPIO_3_23 =IOMUX_PAD (0x270 ,0x060 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LBA__LBA =IOMUX_PAD (0x274 ,0x064 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LBA__UART5_RXD_MUX =IOMUX_PAD (0x274 ,0x064 ,0x13 ,0x578 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LBA__GPIO_3_24 =IOMUX_PAD (0x274 ,0x064 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LBA__LBA =IOMUX_PAD (0x274 ,0x064 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LBA__UART5_RXD_MUX =IOMUX_PAD (0x274 ,0x064 ,0x03 ,0x578 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LBA__GPIO_3_24 =IOMUX_PAD (0x274 ,0x064 ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_BCLK__BCLK =IOMUX_PAD (0x000 ,0x068 ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_BCLK__GPIO_4_4 =IOMUX_PAD (0x000 ,0x068 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_RW__RW =IOMUX_PAD (0x278 ,0x06c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_RW__AUD4_TXFS =IOMUX_PAD (0x278 ,0x06c ,0x14 ,0x474 ,0 ,NO_PAD_CTRL ), -MX25_PAD_RW__GPIO_3_25 =IOMUX_PAD (0x278 ,0x06c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_RW__RW =IOMUX_PAD (0x278 ,0x06c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_RW__AUD4_TXFS =IOMUX_PAD (0x278 ,0x06c ,0x04 ,0x474 ,0 ,NO_PAD_CTRL ), +MX25_PAD_RW__GPIO_3_25 =IOMUX_PAD (0x278 ,0x06c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFWE_B__NFWE_B =IOMUX_PAD (0x000 ,0x070 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFWE_B__GPIO_3_26 =IOMUX_PAD (0x000 ,0x070 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFWE_B__NFWE_B =IOMUX_PAD (0x000 ,0x070 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFWE_B__GPIO_3_26 =IOMUX_PAD (0x000 ,0x070 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFRE_B__NFRE_B =IOMUX_PAD (0x000 ,0x074 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFRE_B__GPIO_3_27 =IOMUX_PAD (0x000 ,0x074 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFRE_B__NFRE_B =IOMUX_PAD (0x000 ,0x074 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFRE_B__GPIO_3_27 =IOMUX_PAD (0x000 ,0x074 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFALE__NFALE =IOMUX_PAD (0x000 ,0x078 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFALE__GPIO_3_28 =IOMUX_PAD (0x000 ,0x078 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFALE__NFALE =IOMUX_PAD (0x000 ,0x078 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFALE__GPIO_3_28 =IOMUX_PAD (0x000 ,0x078 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFCLE__NFCLE =IOMUX_PAD (0x000 ,0x07c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFCLE__GPIO_3_29 =IOMUX_PAD (0x000 ,0x07c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFCLE__NFCLE =IOMUX_PAD (0x000 ,0x07c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFCLE__GPIO_3_29 =IOMUX_PAD (0x000 ,0x07c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFWP_B__NFWP_B =IOMUX_PAD (0x000 ,0x080 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFWP_B__GPIO_3_30 =IOMUX_PAD (0x000 ,0x080 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFWP_B__NFWP_B =IOMUX_PAD (0x000 ,0x080 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFWP_B__GPIO_3_30 =IOMUX_PAD (0x000 ,0x080 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_NFRB__NFRB =IOMUX_PAD (0x27c ,0x084 ,0x10 ,0 ,0 ,PAD_CTL_PKE ), -MX25_PAD_NFRB__GPIO_3_31 =IOMUX_PAD (0x27c ,0x084 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_NFRB__NFRB =IOMUX_PAD (0x27c ,0x084 ,0x00 ,0 ,0 ,PAD_CTL_PKE ), +MX25_PAD_NFRB__GPIO_3_31 =IOMUX_PAD (0x27c ,0x084 ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_D15__D15 =IOMUX_PAD (0x280 ,0x088 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
@@ -197,309 +197,318 @@ enum {MX25_PAD_D0__D0 =IOMUX_PAD (0x2bc ,0x0c4 ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_D0__GPIO_4_20 =IOMUX_PAD (0x2bc ,0x0c4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD0__LD0 =IOMUX_PAD (0x2c0 ,0x0c8 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD0__CSI_D0 =IOMUX_PAD (0x2c0 ,0x0c8 ,0x12 ,0x488 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD0__GPIO_2_15 =IOMUX_PAD (0x2c0 ,0x0c8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD0__LD0 =IOMUX_PAD (0x2c0 ,0x0c8 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD0__CSI_D0 =IOMUX_PAD (0x2c0 ,0x0c8 ,0x02 ,0x488 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD0__GPIO_2_15 =IOMUX_PAD (0x2c0 ,0x0c8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD1__LD1 =IOMUX_PAD (0x2c4 ,0x0cc ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD1__CSI_D1 =IOMUX_PAD (0x2c4 ,0x0cc ,0x12 ,0x48c ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD1__GPIO_2_16 =IOMUX_PAD (0x2c4 ,0x0cc ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD1__LD1 =IOMUX_PAD (0x2c4 ,0x0cc ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD1__CSI_D1 =IOMUX_PAD (0x2c4 ,0x0cc ,0x02 ,0x48c ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD1__GPIO_2_16 =IOMUX_PAD (0x2c4 ,0x0cc ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD2__LD2 =IOMUX_PAD (0x2c8 ,0x0d0 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD2__GPIO_2_17 =IOMUX_PAD (0x2c8 ,0x0d0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD2__LD2 =IOMUX_PAD (0x2c8 ,0x0d0 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD2__GPIO_2_17 =IOMUX_PAD (0x2c8 ,0x0d0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD3__LD3 =IOMUX_PAD (0x2cc ,0x0d4 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD3__GPIO_2_18 =IOMUX_PAD (0x2cc ,0x0d4 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD3__LD3 =IOMUX_PAD (0x2cc ,0x0d4 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD3__GPIO_2_18 =IOMUX_PAD (0x2cc ,0x0d4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD4__LD4 =IOMUX_PAD (0x2d0 ,0x0d8 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD4__GPIO_2_19 =IOMUX_PAD (0x2d0 ,0x0d8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD4__LD4 =IOMUX_PAD (0x2d0 ,0x0d8 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD4__GPIO_2_19 =IOMUX_PAD (0x2d0 ,0x0d8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD5__LD5 =IOMUX_PAD (0x2d4 ,0x0dc ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD5__GPIO_1_19 =IOMUX_PAD (0x2d4 ,0x0dc ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD5__LD5 =IOMUX_PAD (0x2d4 ,0x0dc ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD5__GPIO_1_19 =IOMUX_PAD (0x2d4 ,0x0dc ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD6__LD6 =IOMUX_PAD (0x2d8 ,0x0e0 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD6__GPIO_1_20 =IOMUX_PAD (0x2d8 ,0x0e0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD6__LD6 =IOMUX_PAD (0x2d8 ,0x0e0 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD6__GPIO_1_20 =IOMUX_PAD (0x2d8 ,0x0e0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD7__LD7 =IOMUX_PAD (0x2dc ,0x0e4 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD7__GPIO_1_21 =IOMUX_PAD (0x2dc ,0x0e4 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD7__LD7 =IOMUX_PAD (0x2dc ,0x0e4 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD7__GPIO_1_21 =IOMUX_PAD (0x2dc ,0x0e4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD8__LD8 =IOMUX_PAD (0x2e0 ,0x0e8 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD8__FEC_TX_ERR =IOMUX_PAD (0x2e0 ,0x0e8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD8__LD8 =IOMUX_PAD (0x2e0 ,0x0e8 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD8__FEC_TX_ERR =IOMUX_PAD (0x2e0 ,0x0e8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD9__LD9 =IOMUX_PAD (0x2e4 ,0x0ec ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD9__FEC_COL =IOMUX_PAD (0x2e4 ,0x0ec ,0x15 ,0x504 ,1 ,NO_PAD_CTRL ), +MX25_PAD_LD9__LD9 =IOMUX_PAD (0x2e4 ,0x0ec ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD9__FEC_COL =IOMUX_PAD (0x2e4 ,0x0ec ,0x05 ,0x504 ,1 ,NO_PAD_CTRL ), -MX25_PAD_LD10__LD10 =IOMUX_PAD (0x2e8 ,0x0f0 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD10__FEC_RX_ER =IOMUX_PAD (0x2e8 ,0x0f0 ,0x15 ,0x518 ,1 ,NO_PAD_CTRL ), +MX25_PAD_LD10__LD10 =IOMUX_PAD (0x2e8 ,0x0f0 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD10__FEC_RX_ER =IOMUX_PAD (0x2e8 ,0x0f0 ,0x05 ,0x518 ,1 ,NO_PAD_CTRL ), -MX25_PAD_LD11__LD11 =IOMUX_PAD (0x2ec ,0x0f4 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD11__FEC_RDATA2 =IOMUX_PAD (0x2ec ,0x0f4 ,0x15 ,0x50c ,1 ,NO_PAD_CTRL ), +MX25_PAD_LD11__LD11 =IOMUX_PAD (0x2ec ,0x0f4 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD11__FEC_RDATA2 =IOMUX_PAD (0x2ec ,0x0f4 ,0x05 ,0x50c ,1 ,NO_PAD_CTRL ), -MX25_PAD_LD12__LD12 =IOMUX_PAD (0x2f0 ,0x0f8 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD12__FEC_RDATA3 =IOMUX_PAD (0x2f0 ,0x0f8 ,0x15 ,0x510 ,1 ,NO_PAD_CTRL ), +MX25_PAD_LD12__LD12 =IOMUX_PAD (0x2f0 ,0x0f8 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD12__FEC_RDATA3 =IOMUX_PAD (0x2f0 ,0x0f8 ,0x05 ,0x510 ,1 ,NO_PAD_CTRL ), -MX25_PAD_LD13__LD13 =IOMUX_PAD (0x2f4 ,0x0fc ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD13__FEC_TDATA2 =IOMUX_PAD (0x2f4 ,0x0fc ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD13__LD13 =IOMUX_PAD (0x2f4 ,0x0fc ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD13__FEC_TDATA2 =IOMUX_PAD (0x2f4 ,0x0fc ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD14__LD14 =IOMUX_PAD (0x2f8 ,0x100 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD14__FEC_TDATA3 =IOMUX_PAD (0x2f8 ,0x100 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LD14__LD14 =IOMUX_PAD (0x2f8 ,0x100 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD14__FEC_TDATA3 =IOMUX_PAD (0x2f8 ,0x100 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LD15__LD15 =IOMUX_PAD (0x2fc ,0x104 ,0x10 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_LD15__FEC_RX_CLK =IOMUX_PAD (0x2fc ,0x104 ,0x15 ,0x514 ,1 ,NO_PAD_CTRL ), +MX25_PAD_LD15__LD15 =IOMUX_PAD (0x2fc ,0x104 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), +MX25_PAD_LD15__FEC_RX_CLK =IOMUX_PAD (0x2fc ,0x104 ,0x05 ,0x514 ,1 ,NO_PAD_CTRL ), -MX25_PAD_HSYNC__HSYNC =IOMUX_PAD (0x300 ,0x108 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_HSYNC__GPIO_1_22 =IOMUX_PAD (0x300 ,0x108 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_HSYNC__HSYNC =IOMUX_PAD (0x300 ,0x108 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_HSYNC__GPIO_1_22 =IOMUX_PAD (0x300 ,0x108 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_VSYNC__VSYNC =IOMUX_PAD (0x304 ,0x10c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_VSYNC__GPIO_1_23 =IOMUX_PAD (0x304 ,0x10c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_VSYNC__VSYNC =IOMUX_PAD (0x304 ,0x10c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_VSYNC__GPIO_1_23 =IOMUX_PAD (0x304 ,0x10c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LSCLK__LSCLK =IOMUX_PAD (0x308 ,0x110 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_LSCLK__GPIO_1_24 =IOMUX_PAD (0x308 ,0x110 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LSCLK__LSCLK =IOMUX_PAD (0x308 ,0x110 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_LSCLK__GPIO_1_24 =IOMUX_PAD (0x308 ,0x110 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_OE_ACD__OE_ACD =IOMUX_PAD (0x30c ,0x114 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_OE_ACD__GPIO_1_25 =IOMUX_PAD (0x30c ,0x114 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_OE_ACD__OE_ACD =IOMUX_PAD (0x30c ,0x114 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_OE_ACD__GPIO_1_25 =IOMUX_PAD (0x30c ,0x114 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CONTRAST__CONTRAST =IOMUX_PAD (0x310 ,0x118 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CONTRAST__PWM4_PWMO =IOMUX_PAD (0x310 ,0x118 ,0x14 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CONTRAST__FEC_CRS =IOMUX_PAD (0x310 ,0x118 ,0x15 ,0x508 ,1 ,NO_PAD_CTRL ), +MX25_PAD_CONTRAST__CONTRAST =IOMUX_PAD (0x310 ,0x118 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CONTRAST__PWM4_PWMO =IOMUX_PAD (0x310 ,0x118 ,0x04 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CONTRAST__FEC_CRS =IOMUX_PAD (0x310 ,0x118 ,0x05 ,0x508 ,1 ,NO_PAD_CTRL ), -MX25_PAD_PWM__PWM =IOMUX_PAD (0x314 ,0x11c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_PWM__GPIO_1_26 =IOMUX_PAD (0x314 ,0x11c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_PWM__USBH2_OC =IOMUX_PAD (0x314 ,0x11c ,0x16 ,0x580 ,1 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_PWM__PWM =IOMUX_PAD (0x314 ,0x11c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_PWM__GPIO_1_26 =IOMUX_PAD (0x314 ,0x11c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_PWM__USBH2_OC =IOMUX_PAD (0x314 ,0x11c ,0x06 ,0x580 ,1 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_CSI_D2__CSI_D2 =IOMUX_PAD (0x318 ,0x120 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D2__UART5_RXD_MUX =IOMUX_PAD (0x318 ,0x120 ,0x11 ,0x578 ,1 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D2__GPIO_1_27 =IOMUX_PAD (0x318 ,0x120 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D2__CSPI3_MOSI =IOMUX_PAD (0x318 ,0x120 ,0x17 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D2__CSI_D2 =IOMUX_PAD (0x318 ,0x120 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D2__UART5_RXD_MUX =IOMUX_PAD (0x318 ,0x120 ,0x01 ,0x578 ,1 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D2__GPIO_1_27 =IOMUX_PAD (0x318 ,0x120 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D2__CSPI3_MOSI =IOMUX_PAD (0x318 ,0x120 ,0x07 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D3__CSI_D3 =IOMUX_PAD (0x31c ,0x124 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D3__GPIO_1_28 =IOMUX_PAD (0x31c ,0x124 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D3__CSPI3_MISO =IOMUX_PAD (0x31c ,0x124 ,0x17 ,0x4b4 ,1 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D3__CSI_D3 =IOMUX_PAD (0x31c ,0x124 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D3__GPIO_1_28 =IOMUX_PAD (0x31c ,0x124 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D3__CSPI3_MISO =IOMUX_PAD (0x31c ,0x124 ,0x07 ,0x4b4 ,1 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D4__CSI_D4 =IOMUX_PAD (0x320 ,0x128 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D4__UART5_RTS =IOMUX_PAD (0x320 ,0x128 ,0x11 ,0x574 ,1 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D4__GPIO_1_29 =IOMUX_PAD (0x320 ,0x128 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D4__CSPI3_SCLK =IOMUX_PAD (0x320 ,0x128 ,0x17 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D4__CSI_D4 =IOMUX_PAD (0x320 ,0x128 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D4__UART5_RTS =IOMUX_PAD (0x320 ,0x128 ,0x01 ,0x574 ,1 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D4__GPIO_1_29 =IOMUX_PAD (0x320 ,0x128 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D4__CSPI3_SCLK =IOMUX_PAD (0x320 ,0x128 ,0x07 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D5__CSI_D5 =IOMUX_PAD (0x324 ,0x12c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D5__GPIO_1_30 =IOMUX_PAD (0x324 ,0x12c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D5__CSPI3_RDY =IOMUX_PAD (0x324 ,0x12c ,0x17 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D5__CSI_D5 =IOMUX_PAD (0x324 ,0x12c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D5__GPIO_1_30 =IOMUX_PAD (0x324 ,0x12c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D5__CSPI3_RDY =IOMUX_PAD (0x324 ,0x12c ,0x07 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D6__CSI_D6 =IOMUX_PAD (0x328 ,0x130 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D6__GPIO_1_31 =IOMUX_PAD (0x328 ,0x130 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D6__CSI_D6 =IOMUX_PAD (0x328 ,0x130 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D6__GPIO_1_31 =IOMUX_PAD (0x328 ,0x130 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D7__CSI_D7 =IOMUX_PAD (0x32c ,0x134 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D7__GPIO_1_6 =IOMUX_PAD (0x32c ,0x134 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D7__CSI_D7 =IOMUX_PAD (0x32c ,0x134 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D7__GPIO_1_6 =IOMUX_PAD (0x32c ,0x134 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D8__CSI_D8 =IOMUX_PAD (0x330 ,0x138 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D8__GPIO_1_7 =IOMUX_PAD (0x330 ,0x138 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D8__CSI_D8 =IOMUX_PAD (0x330 ,0x138 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D8__GPIO_1_7 =IOMUX_PAD (0x330 ,0x138 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D9__CSI_D9 =IOMUX_PAD (0x334 ,0x13c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_D9__GPIO_4_21 =IOMUX_PAD (0x334 ,0x13c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D9__CSI_D9 =IOMUX_PAD (0x334 ,0x13c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D9__GPIO_4_21 =IOMUX_PAD (0x334 ,0x13c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_MCLK__CSI_MCLK =IOMUX_PAD (0x338 ,0x140 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_MCLK__GPIO_1_8 =IOMUX_PAD (0x338 ,0x140 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_MCLK__CSI_MCLK =IOMUX_PAD (0x338 ,0x140 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_MCLK__GPIO_1_8 =IOMUX_PAD (0x338 ,0x140 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_VSYNC__CSI_VSYNC =IOMUX_PAD (0x33c ,0x144 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_VSYNC__GPIO_1_9 =IOMUX_PAD (0x33c ,0x144 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_VSYNC__CSI_VSYNC =IOMUX_PAD (0x33c ,0x144 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_VSYNC__GPIO_1_9 =IOMUX_PAD (0x33c ,0x144 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_HSYNC__CSI_HSYNC =IOMUX_PAD (0x340 ,0x148 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_HSYNC__GPIO_1_10 =IOMUX_PAD (0x340 ,0x148 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_HSYNC__CSI_HSYNC =IOMUX_PAD (0x340 ,0x148 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_HSYNC__GPIO_1_10 =IOMUX_PAD (0x340 ,0x148 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_PIXCLK__CSI_PIXCLK =IOMUX_PAD (0x344 ,0x14c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSI_PIXCLK__GPIO_1_11 =IOMUX_PAD (0x344 ,0x14c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_PIXCLK__CSI_PIXCLK =IOMUX_PAD (0x344 ,0x14c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_PIXCLK__GPIO_1_11 =IOMUX_PAD (0x344 ,0x14c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_I2C1_CLK__I2C1_CLK =IOMUX_PAD (0x348 ,0x150 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_I2C1_CLK__GPIO_1_12 =IOMUX_PAD (0x348 ,0x150 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_I2C1_CLK__I2C1_CLK =IOMUX_PAD (0x348 ,0x150 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_I2C1_CLK__GPIO_1_12 =IOMUX_PAD (0x348 ,0x150 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_I2C1_DAT__I2C1_DAT =IOMUX_PAD (0x34c ,0x154 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_I2C1_DAT__GPIO_1_13 =IOMUX_PAD (0x34c ,0x154 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_I2C1_DAT__I2C1_DAT =IOMUX_PAD (0x34c ,0x154 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_I2C1_DAT__GPIO_1_13 =IOMUX_PAD (0x34c ,0x154 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_MOSI__CSPI1_MOSI =IOMUX_PAD (0x350 ,0x158 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_MOSI__GPIO_1_14 =IOMUX_PAD (0x350 ,0x158 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_MOSI__CSPI1_MOSI =IOMUX_PAD (0x350 ,0x158 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_MOSI__GPIO_1_14 =IOMUX_PAD (0x350 ,0x158 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_MISO__CSPI1_MISO =IOMUX_PAD (0x354 ,0x15c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_MISO__GPIO_1_15 =IOMUX_PAD (0x354 ,0x15c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_MISO__CSPI1_MISO =IOMUX_PAD (0x354 ,0x15c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_MISO__GPIO_1_15 =IOMUX_PAD (0x354 ,0x15c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_SS0__CSPI1_SS0 =IOMUX_PAD (0x358 ,0x160 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_SS0__GPIO_1_16 =IOMUX_PAD (0x358 ,0x160 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_SS0__CSPI1_SS0 =IOMUX_PAD (0x358 ,0x160 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_SS0__GPIO_1_16 =IOMUX_PAD (0x358 ,0x160 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_SS1__CSPI1_SS1 =IOMUX_PAD (0x35c ,0x164 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_SS1__I2C3_DAT =IOMUX_PAD (0x35c ,0x164 ,0x11 ,0x528 ,1 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_SS1__GPIO_1_17 =IOMUX_PAD (0x35c ,0x164 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_SS1__CSPI1_SS1 =IOMUX_PAD (0x35c ,0x164 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_SS1__I2C3_DAT =IOMUX_PAD (0x35c ,0x164 ,0x01 ,0x528 ,1 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_SS1__GPIO_1_17 =IOMUX_PAD (0x35c ,0x164 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_SCLK__CSPI1_SCLK =IOMUX_PAD (0x360 ,0x168 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_SCLK__GPIO_1_18 =IOMUX_PAD (0x360 ,0x168 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_SCLK__CSPI1_SCLK =IOMUX_PAD (0x360 ,0x168 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_SCLK__GPIO_1_18 =IOMUX_PAD (0x360 ,0x168 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CSPI1_RDY__CSPI1_RDY =IOMUX_PAD (0x364 ,0x16c ,0x10 ,0 ,0 ,PAD_CTL_PKE ), -MX25_PAD_CSPI1_RDY__GPIO_2_22 =IOMUX_PAD (0x364 ,0x16c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSPI1_RDY__CSPI1_RDY =IOMUX_PAD (0x364 ,0x16c ,0x00 ,0 ,0 ,PAD_CTL_PKE ), +MX25_PAD_CSPI1_RDY__GPIO_2_22 =IOMUX_PAD (0x364 ,0x16c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART1_RXD__UART1_RXD =IOMUX_PAD (0x368 ,0x170 ,0x10 ,0 ,0 ,PAD_CTL_PUS_100K_DOWN ), -MX25_PAD_UART1_RXD__GPIO_4_22 =IOMUX_PAD (0x368 ,0x170 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART1_RXD__UART1_RXD =IOMUX_PAD (0x368 ,0x170 ,0x00 ,0 ,0 ,PAD_CTL_PUS_100K_DOWN ), +MX25_PAD_UART1_RXD__GPIO_4_22 =IOMUX_PAD (0x368 ,0x170 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART1_TXD__UART1_TXD =IOMUX_PAD (0x36c ,0x174 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART1_TXD__GPIO_4_23 =IOMUX_PAD (0x36c ,0x174 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART1_TXD__UART1_TXD =IOMUX_PAD (0x36c ,0x174 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART1_TXD__GPIO_4_23 =IOMUX_PAD (0x36c ,0x174 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART1_RTS__UART1_RTS =IOMUX_PAD (0x370 ,0x178 ,0x10 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_UART1_RTS__CSI_D0 =IOMUX_PAD (0x370 ,0x178 ,0x11 ,0x488 ,1 ,NO_PAD_CTRL ), -MX25_PAD_UART1_RTS__GPIO_4_24 =IOMUX_PAD (0x370 ,0x178 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART1_RTS__UART1_RTS =IOMUX_PAD (0x370 ,0x178 ,0x00 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_UART1_RTS__CSI_D0 =IOMUX_PAD (0x370 ,0x178 ,0x01 ,0x488 ,1 ,NO_PAD_CTRL ), +MX25_PAD_UART1_RTS__GPIO_4_24 =IOMUX_PAD (0x370 ,0x178 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART1_CTS__UART1_CTS =IOMUX_PAD (0x374 ,0x17c ,0x10 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_UART1_CTS__CSI_D1 =IOMUX_PAD (0x374 ,0x17c ,0x11 ,0x48c ,1 ,NO_PAD_CTRL ), -MX25_PAD_UART1_CTS__GPIO_4_25 =IOMUX_PAD (0x374 ,0x17c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART1_CTS__UART1_CTS =IOMUX_PAD (0x374 ,0x17c ,0x00 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_UART1_CTS__CSI_D1 =IOMUX_PAD (0x374 ,0x17c ,0x01 ,0x48c ,1 ,NO_PAD_CTRL ), +MX25_PAD_UART1_CTS__GPIO_4_25 =IOMUX_PAD (0x374 ,0x17c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_RXD__UART2_RXD =IOMUX_PAD (0x378 ,0x180 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_RXD__GPIO_4_26 =IOMUX_PAD (0x378 ,0x180 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_RXD__UART2_RXD =IOMUX_PAD (0x378 ,0x180 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_RXD__GPIO_4_26 =IOMUX_PAD (0x378 ,0x180 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_TXD__UART2_TXD =IOMUX_PAD (0x37c ,0x184 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_TXD__GPIO_4_27 =IOMUX_PAD (0x37c ,0x184 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_TXD__UART2_TXD =IOMUX_PAD (0x37c ,0x184 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_TXD__GPIO_4_27 =IOMUX_PAD (0x37c ,0x184 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_RTS__UART2_RTS =IOMUX_PAD (0x380 ,0x188 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_RTS__FEC_COL =IOMUX_PAD (0x380 ,0x188 ,0x12 ,0x504 ,2 ,NO_PAD_CTRL ), -MX25_PAD_UART2_RTS__GPIO_4_28 =IOMUX_PAD (0x380 ,0x188 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_RTS__UART2_RTS =IOMUX_PAD (0x380 ,0x188 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_RTS__FEC_COL =IOMUX_PAD (0x380 ,0x188 ,0x02 ,0x504 ,2 ,NO_PAD_CTRL ), +MX25_PAD_UART2_RTS__GPIO_4_28 =IOMUX_PAD (0x380 ,0x188 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_CTS__FEC_RX_ER =IOMUX_PAD (0x384 ,0x18c ,0x12 ,0x518 ,2 ,NO_PAD_CTRL ), -MX25_PAD_UART2_CTS__UART2_CTS =IOMUX_PAD (0x384 ,0x18c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UART2_CTS__GPIO_4_29 =IOMUX_PAD (0x384 ,0x18c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_CTS__FEC_RX_ER =IOMUX_PAD (0x384 ,0x18c ,0x02 ,0x518 ,2 ,NO_PAD_CTRL ), +MX25_PAD_UART2_CTS__UART2_CTS =IOMUX_PAD (0x384 ,0x18c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UART2_CTS__GPIO_4_29 =IOMUX_PAD (0x384 ,0x18c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +/* +* Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD +* card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM +* Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon +* bug that configuring the SD1_CMD function doesn't enable the input path for +* this pin. +* This might have side effects for other hardware units that are connected to +* that pin and use the respective function as input. +*/ MX25_PAD_SD1_CMD__SD1_CMD =IOMUX_PAD (0x388 ,0x190 ,0x10 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), -MX25_PAD_SD1_CMD__FEC_RDATA2 =IOMUX_PAD (0x388 ,0x190 ,0x12 ,0x50c ,2 ,NO_PAD_CTRL ), -MX25_PAD_SD1_CMD__GPIO_2_23 =IOMUX_PAD (0x388 ,0x190 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_SD1_CMD__FEC_RDATA2 =IOMUX_PAD (0x388 ,0x190 ,0x02 ,0x50c ,2 ,NO_PAD_CTRL ), +MX25_PAD_SD1_CMD__GPIO_2_23 =IOMUX_PAD (0x388 ,0x190 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_SD1_CLK__SD1_CLK =IOMUX_PAD (0x38c ,0x194 ,0x10 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), -MX25_PAD_SD1_CLK__FEC_RDATA3 =IOMUX_PAD (0x38c ,0x194 ,0x12 ,0x510 ,2 ,NO_PAD_CTRL ), -MX25_PAD_SD1_CLK__GPIO_2_24 =IOMUX_PAD (0x38c ,0x194 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_SD1_CLK__SD1_CLK =IOMUX_PAD (0x38c ,0x194 ,0x00 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), +MX25_PAD_SD1_CLK__FEC_RDATA3 =IOMUX_PAD (0x38c ,0x194 ,0x02 ,0x510 ,2 ,NO_PAD_CTRL ), +MX25_PAD_SD1_CLK__GPIO_2_24 =IOMUX_PAD (0x38c ,0x194 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_SD1_DATA0__SD1_DATA0 =IOMUX_PAD (0x390 ,0x198 ,0x10 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), -MX25_PAD_SD1_DATA0__GPIO_2_25 =IOMUX_PAD (0x390 ,0x198 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_SD1_DATA0__SD1_DATA0 =IOMUX_PAD (0x390 ,0x198 ,0x00 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), +MX25_PAD_SD1_DATA0__GPIO_2_25 =IOMUX_PAD (0x390 ,0x198 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_SD1_DATA1__SD1_DATA1 =IOMUX_PAD (0x394 ,0x19c ,0x10 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), -MX25_PAD_SD1_DATA1__AUD7_RXD =IOMUX_PAD (0x394 ,0x19c ,0x13 ,0x478 ,0 ,NO_PAD_CTRL ), -MX25_PAD_SD1_DATA1__GPIO_2_26 =IOMUX_PAD (0x394 ,0x19c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_SD1_DATA1__SD1_DATA1 =IOMUX_PAD (0x394 ,0x19c ,0x00 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), +MX25_PAD_SD1_DATA1__AUD7_RXD =IOMUX_PAD (0x394 ,0x19c ,0x03 ,0x478 ,0 ,NO_PAD_CTRL ), +MX25_PAD_SD1_DATA1__GPIO_2_26 =IOMUX_PAD (0x394 ,0x19c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_SD1_DATA2__SD1_DATA2 =IOMUX_PAD (0x398 ,0x1a0 ,0x10 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), -MX25_PAD_SD1_DATA2__FEC_RX_CLK =IOMUX_PAD (0x398 ,0x1a0 ,0x15 ,0x514 ,2 ,NO_PAD_CTRL ), -MX25_PAD_SD1_DATA2__GPIO_2_27 =IOMUX_PAD (0x398 ,0x1a0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_SD1_DATA2__SD1_DATA2 =IOMUX_PAD (0x398 ,0x1a0 ,0x00 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), +MX25_PAD_SD1_DATA2__FEC_RX_CLK =IOMUX_PAD (0x398 ,0x1a0 ,0x05 ,0x514 ,2 ,NO_PAD_CTRL ), +MX25_PAD_SD1_DATA2__GPIO_2_27 =IOMUX_PAD (0x398 ,0x1a0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_SD1_DATA3__SD1_DATA3 =IOMUX_PAD (0x39c ,0x1a4 ,0x10 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), -MX25_PAD_SD1_DATA3__FEC_CRS =IOMUX_PAD (0x39c ,0x1a4 ,0x10 ,0x508 ,2 ,NO_PAD_CTRL ), -MX25_PAD_SD1_DATA3__GPIO_2_28 =IOMUX_PAD (0x39c ,0x1a4 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_SD1_DATA3__SD1_DATA3 =IOMUX_PAD (0x39c ,0x1a4 ,0x00 ,0 ,0 ,PAD_CTL_PUS_47K_UP ), +MX25_PAD_SD1_DATA3__FEC_CRS =IOMUX_PAD (0x39c ,0x1a4 ,0x00 ,0x508 ,2 ,NO_PAD_CTRL ), +MX25_PAD_SD1_DATA3__GPIO_2_28 =IOMUX_PAD (0x39c ,0x1a4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_ROW0__KPP_ROW0 =IOMUX_PAD (0x3a0 ,0x1a8 ,0x10 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), -MX25_PAD_KPP_ROW0__GPIO_2_29 =IOMUX_PAD (0x3a0 ,0x1a8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_ROW0__KPP_ROW0 =IOMUX_PAD (0x3a0 ,0x1a8 ,0x00 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), +MX25_PAD_KPP_ROW0__GPIO_2_29 =IOMUX_PAD (0x3a0 ,0x1a8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_ROW1__KPP_ROW1 =IOMUX_PAD (0x3a4 ,0x1ac ,0x10 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), -MX25_PAD_KPP_ROW1__GPIO_2_30 =IOMUX_PAD (0x3a4 ,0x1ac ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_ROW1__KPP_ROW1 =IOMUX_PAD (0x3a4 ,0x1ac ,0x00 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), +MX25_PAD_KPP_ROW1__GPIO_2_30 =IOMUX_PAD (0x3a4 ,0x1ac ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_ROW2__KPP_ROW2 =IOMUX_PAD (0x3a8 ,0x1b0 ,0x10 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), -MX25_PAD_KPP_ROW2__CSI_D0 =IOMUX_PAD (0x3a8 ,0x1b0 ,0x13 ,0x488 ,2 ,NO_PAD_CTRL ), -MX25_PAD_KPP_ROW2__GPIO_2_31 =IOMUX_PAD (0x3a8 ,0x1b0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_ROW2__KPP_ROW2 =IOMUX_PAD (0x3a8 ,0x1b0 ,0x00 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), +MX25_PAD_KPP_ROW2__CSI_D0 =IOMUX_PAD (0x3a8 ,0x1b0 ,0x03 ,0x488 ,2 ,NO_PAD_CTRL ), +MX25_PAD_KPP_ROW2__GPIO_2_31 =IOMUX_PAD (0x3a8 ,0x1b0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_ROW3__KPP_ROW3 =IOMUX_PAD (0x3ac ,0x1b4 ,0x10 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), -MX25_PAD_KPP_ROW3__CSI_LD1 =IOMUX_PAD (0x3ac ,0x1b4 ,0x13 ,0x48c ,2 ,NO_PAD_CTRL ), -MX25_PAD_KPP_ROW3__GPIO_3_0 =IOMUX_PAD (0x3ac ,0x1b4 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_ROW3__KPP_ROW3 =IOMUX_PAD (0x3ac ,0x1b4 ,0x00 ,0 ,0 ,MX25_KPP_ROW_PAD_CTRL ), +MX25_PAD_KPP_ROW3__CSI_LD1 =IOMUX_PAD (0x3ac ,0x1b4 ,0x03 ,0x48c ,2 ,NO_PAD_CTRL ), +MX25_PAD_KPP_ROW3__GPIO_3_0 =IOMUX_PAD (0x3ac ,0x1b4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL0__KPP_COL0 =IOMUX_PAD (0x3b0 ,0x1b8 ,0x10 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), -MX25_PAD_KPP_COL0__UART4_RXD_MUX =IOMUX_PAD (0x3b0 ,0x1b8 ,0x11 ,0x570 ,1 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL0__AUD5_TXD =IOMUX_PAD (0x3b0 ,0x1b8 ,0x12 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_KPP_COL0__GPIO_3_1 =IOMUX_PAD (0x3b0 ,0x1b8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL0__KPP_COL0 =IOMUX_PAD (0x3b0 ,0x1b8 ,0x00 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), +MX25_PAD_KPP_COL0__UART4_RXD_MUX =IOMUX_PAD (0x3b0 ,0x1b8 ,0x01 ,0x570 ,1 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL0__AUD5_TXD =IOMUX_PAD (0x3b0 ,0x1b8 ,0x02 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_KPP_COL0__GPIO_3_1 =IOMUX_PAD (0x3b0 ,0x1b8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL1__KPP_COL1 =IOMUX_PAD (0x3b4 ,0x1bc ,0x10 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), -MX25_PAD_KPP_COL1__UART4_TXD_MUX =IOMUX_PAD (0x3b4 ,0x1bc ,0x11 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL1__AUD5_RXD =IOMUX_PAD (0x3b4 ,0x1bc ,0x12 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_KPP_COL1__GPIO_3_2 =IOMUX_PAD (0x3b4 ,0x1bc ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL1__KPP_COL1 =IOMUX_PAD (0x3b4 ,0x1bc ,0x00 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), +MX25_PAD_KPP_COL1__UART4_TXD_MUX =IOMUX_PAD (0x3b4 ,0x1bc ,0x01 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL1__AUD5_RXD =IOMUX_PAD (0x3b4 ,0x1bc ,0x02 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_KPP_COL1__GPIO_3_2 =IOMUX_PAD (0x3b4 ,0x1bc ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL2__KPP_COL2 =IOMUX_PAD (0x3b8 ,0x1c0 ,0x10 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), -MX25_PAD_KPP_COL2__UART4_RTS =IOMUX_PAD (0x3b8 ,0x1c0 ,0x11 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL2__AUD5_TXC =IOMUX_PAD (0x3b8 ,0x1c0 ,0x12 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_KPP_COL2__GPIO_3_3 =IOMUX_PAD (0x3b8 ,0x1c0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL2__KPP_COL2 =IOMUX_PAD (0x3b8 ,0x1c0 ,0x00 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), +MX25_PAD_KPP_COL2__UART4_RTS =IOMUX_PAD (0x3b8 ,0x1c0 ,0x01 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL2__AUD5_TXC =IOMUX_PAD (0x3b8 ,0x1c0 ,0x02 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_KPP_COL2__GPIO_3_3 =IOMUX_PAD (0x3b8 ,0x1c0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL3__KPP_COL3 =IOMUX_PAD (0x3bc ,0x1c4 ,0x10 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), -MX25_PAD_KPP_COL3__UART4_CTS =IOMUX_PAD (0x3bc ,0x1c4 ,0x11 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_KPP_COL3__AUD5_TXFS =IOMUX_PAD (0x3bc ,0x1c4 ,0x12 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_KPP_COL3__GPIO_3_4 =IOMUX_PAD (0x3bc ,0x1c4 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL3__KPP_COL3 =IOMUX_PAD (0x3bc ,0x1c4 ,0x00 ,0 ,0 ,MX25_KPP_COL_PAD_CTRL ), +MX25_PAD_KPP_COL3__UART4_CTS =IOMUX_PAD (0x3bc ,0x1c4 ,0x01 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_KPP_COL3__AUD5_TXFS =IOMUX_PAD (0x3bc ,0x1c4 ,0x02 ,0 ,0 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_KPP_COL3__GPIO_3_4 =IOMUX_PAD (0x3bc ,0x1c4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_MDC__FEC_MDC =IOMUX_PAD (0x3c0 ,0x1c8 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_MDC__AUD4_TXD =IOMUX_PAD (0x3c0 ,0x1c8 ,0x12 ,0x464 ,1 ,NO_PAD_CTRL ), -MX25_PAD_FEC_MDC__GPIO_3_5 =IOMUX_PAD (0x3c0 ,0x1c8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_MDC__FEC_MDC =IOMUX_PAD (0x3c0 ,0x1c8 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_MDC__AUD4_TXD =IOMUX_PAD (0x3c0 ,0x1c8 ,0x02 ,0x464 ,1 ,NO_PAD_CTRL ), +MX25_PAD_FEC_MDC__GPIO_3_5 =IOMUX_PAD (0x3c0 ,0x1c8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_MDIO__FEC_MDIO =IOMUX_PAD (0x3c4 ,0x1cc ,0x10 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_22K_UP ), -MX25_PAD_FEC_MDIO__AUD4_RXD =IOMUX_PAD (0x3c4 ,0x1cc ,0x12 ,0x460 ,1 ,NO_PAD_CTRL ), -MX25_PAD_FEC_MDIO__GPIO_3_6 =IOMUX_PAD (0x3c4 ,0x1cc ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_MDIO__FEC_MDIO =IOMUX_PAD (0x3c4 ,0x1cc ,0x00 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_22K_UP ), +MX25_PAD_FEC_MDIO__AUD4_RXD =IOMUX_PAD (0x3c4 ,0x1cc ,0x02 ,0x460 ,1 ,NO_PAD_CTRL ), +MX25_PAD_FEC_MDIO__GPIO_3_6 =IOMUX_PAD (0x3c4 ,0x1cc ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TDATA0__FEC_TDATA0 =IOMUX_PAD (0x3c8 ,0x1d0 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TDATA0__GPIO_3_7 =IOMUX_PAD (0x3c8 ,0x1d0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TDATA0__FEC_TDATA0 =IOMUX_PAD (0x3c8 ,0x1d0 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TDATA0__GPIO_3_7 =IOMUX_PAD (0x3c8 ,0x1d0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TDATA1__FEC_TDATA1 =IOMUX_PAD (0x3cc ,0x1d4 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TDATA1__AUD4_TXFS =IOMUX_PAD (0x3cc ,0x1d4 ,0x12 ,0x474 ,1 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TDATA1__GPIO_3_8 =IOMUX_PAD (0x3cc ,0x1d4 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TDATA1__FEC_TDATA1 =IOMUX_PAD (0x3cc ,0x1d4 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TDATA1__AUD4_TXFS =IOMUX_PAD (0x3cc ,0x1d4 ,0x02 ,0x474 ,1 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TDATA1__GPIO_3_8 =IOMUX_PAD (0x3cc ,0x1d4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TX_EN__FEC_TX_EN =IOMUX_PAD (0x3d0 ,0x1d8 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TX_EN__GPIO_3_9 =IOMUX_PAD (0x3d0 ,0x1d8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TX_EN__FEC_TX_EN =IOMUX_PAD (0x3d0 ,0x1d8 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TX_EN__GPIO_3_9 =IOMUX_PAD (0x3d0 ,0x1d8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_RDATA0__FEC_RDATA0 =IOMUX_PAD (0x3d4 ,0x1dc ,0x10 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), -MX25_PAD_FEC_RDATA0__GPIO_3_10 =IOMUX_PAD (0x3d4 ,0x1dc ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_RDATA0__FEC_RDATA0 =IOMUX_PAD (0x3d4 ,0x1dc ,0x00 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), +MX25_PAD_FEC_RDATA0__GPIO_3_10 =IOMUX_PAD (0x3d4 ,0x1dc ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_RDATA1__FEC_RDATA1 =IOMUX_PAD (0x3d8 ,0x1e0 ,0x10 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), -MX25_PAD_FEC_RDATA1__GPIO_3_11 =IOMUX_PAD (0x3d8 ,0x1e0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_RDATA1__FEC_RDATA1 =IOMUX_PAD (0x3d8 ,0x1e0 ,0x00 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), +MX25_PAD_FEC_RDATA1__GPIO_3_11 =IOMUX_PAD (0x3d8 ,0x1e0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_RX_DV__FEC_RX_DV =IOMUX_PAD (0x3dc ,0x1e4 ,0x10 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), -MX25_PAD_FEC_RX_DV__CAN2_RX =IOMUX_PAD (0x3dc ,0x1e4 ,0x14 ,0x484 ,0 ,PAD_CTL_PUS_22K_UP ), -MX25_PAD_FEC_RX_DV__GPIO_3_12 =IOMUX_PAD (0x3dc ,0x1e4 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_RX_DV__FEC_RX_DV =IOMUX_PAD (0x3dc ,0x1e4 ,0x00 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), +MX25_PAD_FEC_RX_DV__CAN2_RX =IOMUX_PAD (0x3dc ,0x1e4 ,0x04 ,0x484 ,0 ,PAD_CTL_PUS_22K_UP ), +MX25_PAD_FEC_RX_DV__GPIO_3_12 =IOMUX_PAD (0x3dc ,0x1e4 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_FEC_TX_CLK__FEC_TX_CLK =IOMUX_PAD (0x3e0 ,0x1e8 ,0x10 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), -MX25_PAD_FEC_TX_CLK__GPIO_3_13 =IOMUX_PAD (0x3e0 ,0x1e8 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_FEC_TX_CLK__FEC_TX_CLK =IOMUX_PAD (0x3e0 ,0x1e8 ,0x00 ,0 ,0 ,PAD_CTL_HYS |PAD_CTL_PUS_100K_DOWN ), +MX25_PAD_FEC_TX_CLK__GPIO_3_13 =IOMUX_PAD (0x3e0 ,0x1e8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_RTCK__RTCK =IOMUX_PAD (0x3e4 ,0x1ec ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_RTCK__OWIRE =IOMUX_PAD (0x3e4 ,0x1ec ,0x11 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_RTCK__GPIO_3_14 =IOMUX_PAD (0x3e4 ,0x1ec ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_RTCK__RTCK =IOMUX_PAD (0x3e4 ,0x1ec ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_RTCK__OWIRE =IOMUX_PAD (0x3e4 ,0x1ec ,0x01 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_RTCK__GPIO_3_14 =IOMUX_PAD (0x3e4 ,0x1ec ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_DE_B__DE_B =IOMUX_PAD (0x3ec ,0x1f0 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_DE_B__GPIO_2_20 =IOMUX_PAD (0x3ec ,0x1f0 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_DE_B__DE_B =IOMUX_PAD (0x3ec ,0x1f0 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_DE_B__GPIO_2_20 =IOMUX_PAD (0x3ec ,0x1f0 ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_TDO__TDO =IOMUX_PAD (0x3e8 ,0x000 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_GPIO_A__GPIO_A =IOMUX_PAD (0x3f0 ,0x1f4 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_GPIO_A__CAN1_TX =IOMUX_PAD (0x3f0 ,0x1f4 ,0x16 ,0 ,0 ,PAD_CTL_PUS_22K_UP ), -MX25_PAD_GPIO_A__USBOTG_PWR =IOMUX_PAD (0x3f0 ,0x1f4 ,0x12 ,0 ,0 ,PAD_CTL_PKE ), +MX25_PAD_GPIO_A__GPIO_A =IOMUX_PAD (0x3f0 ,0x1f4 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_A__CAN1_TX =IOMUX_PAD (0x3f0 ,0x1f4 ,0x06 ,0 ,0 ,PAD_CTL_PUS_22K_UP ), +MX25_PAD_GPIO_A__USBOTG_PWR =IOMUX_PAD (0x3f0 ,0x1f4 ,0x02 ,0 ,0 ,PAD_CTL_PKE ), -MX25_PAD_GPIO_B__GPIO_B =IOMUX_PAD (0x3f4 ,0x1f8 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_GPIO_B__CAN1_RX =IOMUX_PAD (0x3f4 ,0x1f8 ,0x16 ,0x480 ,1 ,PAD_CTL_PUS_22K_UP ), -MX25_PAD_GPIO_B__USBOTG_OC =IOMUX_PAD (0x3f4 ,0x1f8 ,0x12 ,0x57c ,1 ,PAD_CTL_PUS_100K_UP ), +MX25_PAD_GPIO_B__GPIO_B =IOMUX_PAD (0x3f4 ,0x1f8 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_B__CAN1_RX =IOMUX_PAD (0x3f4 ,0x1f8 ,0x06 ,0x480 ,1 ,PAD_CTL_PUS_22K_UP ), +MX25_PAD_GPIO_B__USBOTG_OC =IOMUX_PAD (0x3f4 ,0x1f8 ,0x02 ,0x57c ,1 ,PAD_CTL_PUS_100K_UP ), -MX25_PAD_GPIO_C__GPIO_C =IOMUX_PAD (0x3f8 ,0x1fc ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_GPIO_C__CAN2_TX =IOMUX_PAD (0x3f8 ,0x1fc ,0x16 ,0 ,0 ,PAD_CTL_PUS_22K_UP ), +MX25_PAD_GPIO_C__GPIO_C =IOMUX_PAD (0x3f8 ,0x1fc ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_C__CAN2_TX =IOMUX_PAD (0x3f8 ,0x1fc ,0x06 ,0 ,0 ,PAD_CTL_PUS_22K_UP ), -MX25_PAD_GPIO_D__GPIO_D =IOMUX_PAD (0x3fc ,0x200 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_D__GPIO_D =IOMUX_PAD (0x3fc ,0x200 ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_GPIO_E__LD16 =IOMUX_PAD (0x400 ,0x204 ,0x02 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_GPIO_D__CAN2_RX =IOMUX_PAD (0x3fc ,0x200 ,0x16 ,0x484 ,1 ,PAD_CTL_PUS_22K_UP ), +MX25_PAD_GPIO_D__CAN2_RX =IOMUX_PAD (0x3fc ,0x200 ,0x06 ,0x484 ,1 ,PAD_CTL_PUS_22K_UP ), -MX25_PAD_GPIO_E__GPIO_E =IOMUX_PAD (0x400 ,0x204 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_E__GPIO_E =IOMUX_PAD (0x400 ,0x204 ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_GPIO_F__LD17 =IOMUX_PAD (0x404 ,0x208 ,0x02 ,0 ,0 ,PAD_CTL_SRE_FAST ), -MX25_PAD_GPIO_E__I2C3_CLK =IOMUX_PAD (0x400 ,0x204 ,0x11 ,0x524 ,2 ,NO_PAD_CTRL ), -MX25_PAD_GPIO_E__AUD7_TXD =IOMUX_PAD (0x400 ,0x204 ,0x14 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_E__I2C3_CLK =IOMUX_PAD (0x400 ,0x204 ,0x01 ,0x524 ,2 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_E__AUD7_TXD =IOMUX_PAD (0x400 ,0x204 ,0x04 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_GPIO_F__GPIO_F =IOMUX_PAD (0x404 ,0x208 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_GPIO_F__AUD7_TXC =IOMUX_PAD (0x404 ,0x208 ,0x14 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_F__GPIO_F =IOMUX_PAD (0x404 ,0x208 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_GPIO_F__AUD7_TXC =IOMUX_PAD (0x404 ,0x208 ,0x04 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EXT_ARMCLK__EXT_ARMCLK =IOMUX_PAD (0x000 ,0x20c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_EXT_ARMCLK__GPIO_3_15 =IOMUX_PAD (0x000 ,0x20c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EXT_ARMCLK__EXT_ARMCLK =IOMUX_PAD (0x000 ,0x20c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_EXT_ARMCLK__GPIO_3_15 =IOMUX_PAD (0x000 ,0x20c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK =IOMUX_PAD (0x000 ,0x210 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_UPLL_BYPCLK__GPIO_3_16 =IOMUX_PAD (0x000 ,0x210 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK =IOMUX_PAD (0x000 ,0x210 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_UPLL_BYPCLK__GPIO_3_16 =IOMUX_PAD (0x000 ,0x210 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_VSTBY_REQ__VSTBY_REQ =IOMUX_PAD (0x408 ,0x214 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_VSTBY_REQ__AUD7_TXFS =IOMUX_PAD (0x408 ,0x214 ,0x14 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_VSTBY_REQ__GPIO_3_17 =IOMUX_PAD (0x408 ,0x214 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_VSTBY_ACK__VSTBY_ACK =IOMUX_PAD (0x40c ,0x218 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_VSTBY_ACK__GPIO_3_18 =IOMUX_PAD (0x40c ,0x218 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_VSTBY_REQ__VSTBY_REQ =IOMUX_PAD (0x408 ,0x214 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_VSTBY_REQ__AUD7_TXFS =IOMUX_PAD (0x408 ,0x214 ,0x04 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_VSTBY_REQ__GPIO_3_17 =IOMUX_PAD (0x408 ,0x214 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_VSTBY_ACK__VSTBY_ACK =IOMUX_PAD (0x40c ,0x218 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_VSTBY_ACK__GPIO_3_18 =IOMUX_PAD (0x40c ,0x218 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_POWER_FAIL__POWER_FAIL =IOMUX_PAD (0x410 ,0x21c ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_POWER_FAIL__AUD7_RXD =IOMUX_PAD (0x410 ,0x21c ,0x14 ,0x478 ,1 ,NO_PAD_CTRL ), -MX25_PAD_POWER_FAIL__GPIO_3_19 =IOMUX_PAD (0x410 ,0x21c ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_POWER_FAIL__POWER_FAIL =IOMUX_PAD (0x410 ,0x21c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_POWER_FAIL__AUD7_RXD =IOMUX_PAD (0x410 ,0x21c ,0x04 ,0x478 ,1 ,NO_PAD_CTRL ), +MX25_PAD_POWER_FAIL__GPIO_3_19 =IOMUX_PAD (0x410 ,0x21c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CLKO__CLKO =IOMUX_PAD (0x414 ,0x220 ,0x10 ,0 ,0 ,NO_PAD_CTRL ), -MX25_PAD_CLKO__GPIO_2_21 =IOMUX_PAD (0x414 ,0x220 ,0x15 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CLKO__CLKO =IOMUX_PAD (0x414 ,0x220 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CLKO__GPIO_2_21 =IOMUX_PAD (0x414 ,0x220 ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_BOOT_MODE0__BOOT_MODE0 =IOMUX_PAD (0x000 ,0x224 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
Signature · 1 line
2.7.4
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
Hi Michael,
Quoted 23 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIO
Quoted 5 lines
SION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>
[...]
I have now tested the following peripherals on i.MX25 without any SION bit set: AUDMUX/SSI, eSDHC, FEC (except PHY access for which MDIO might have an issue without SION; Ethernet works but I have not checked whether this is possible at least partially without access to the PHY registers), GPIO, I2C, SLCDC, UART, and USB. Everything worked fine except the lack of SION for eSDHC CMD, which is true for all eSDHC instances (and not only for eSDHC1, so Linux's arch/arm/boot/dts/imx25-pinfunc.h should be fixed). Therefore, SION is mandatory for all the eSDHC CMD functions in arch/arm/include/asm/arch-mx25/iomux-mx25.h, but it can be removed for everything else (I still have to carry out one more test to confirm this for FEC MDIO), and moved to the board files if necessary (but I don't think that any mainline board code is doing something fancy enough to need it).
If the bus-status detection example in the documentation of SION in the reference manual is useful, it means that SION is probably required for all the signals requiring simultaneous output and input (such as I²C for device clock stretching or multi-master bus arbitration, except if the IP toggles between input and output low at each clock edge rather than between open-drain output high and output low), because there are no automatic SION signals between the peripherals and the pads but only direction signals that can request a single direction at a time. For bidirectional signals that do not require simultaneous output and input because they work in turns (such as FEC MDIO), SION can be required or not depending on whether the IP toggles the direction signal for each turn or always expects an input feedback while driving an open-drain output high. Even if SION is required for the I²C example mentioned above (which is unlikely as basic I²C transfers work fine and clock stretching detection is automatic and would always need the input state), the need for these advanced I²C features can be considered board-specific, so SION would still not be required in iomux-mx25.h.
In the end, for this patch, apart from the pending test for FEC MDIO:
Best regards,
Benoît
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
Hi
Quoted 35 lines · Benoît Thébaudeau
Hi Michael,
Quoted 28 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIOSION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>[...]
Quoted 10 lines
I have now tested the following peripherals on i.MX25 without any SION bit set: AUDMUX/SSI, eSDHC, FEC (except PHY access for which MDIO might have an issue without SION; Ethernet works but I have not checked whether this is possible at least partially without access to the PHY registers), GPIO, I2C, SLCDC, UART, and USB. Everything worked fine except the lack of SION for eSDHC CMD, which is true for all eSDHC instances (and not only for eSDHC1, so Linux's
arch/arm/boot/dts/imx25-pinfunc.hshould be fixed). Therefore, SION is mandatory for all the eSDHC CMD functions inarch/arm/include/asm/arch-mx25/iomux-mx25.h, but it can be removed for
I will repost. On my side I have tested already some of the peripherals you mention
but I was not having the second slod for eSDHC.
We already run preliminary testing on the hardware and usb problem is right now fixed.
Thank you for testing
Michael
Quoted 29 lines
everything else (I still have to carry out one more test to confirm this for FEC MDIO), and moved to the board files if necessary (but I don't think that any mainline board code is doing something fancy enough to need it).
If the bus-status detection example in the documentation of SION in the reference manual is useful, it means that SION is probably required for all the signals requiring simultaneous output and input (such as I²C for device clock stretching or multi-master bus arbitration, except if the IP toggles between input and output low at each clock edge rather than between open-drain output high and output low), because there are no automatic SION signals between the peripherals and the pads but only direction signals that can request a single direction at a time. For bidirectional signals that do not require simultaneous output and input because they work in turns (such as FEC MDIO), SION can be required or not depending on whether the IP toggles the direction signal for each turn or always expects an input feedback while driving an open-drain output high. Even if SION is required for the I²C example mentioned above (which is unlikely as basic I²C transfers work fine and clock stretching detection is automatic and would always need the input state), the need for these advanced I²C features can be considered board-specific, so SION would still not be required in
iomux-mx25.h.In the end, for this patch, apart from the pending test for FEC MDIO:
Reviewed-by Benoît Thébaudeau <[email protected]>Best regards,
Benoît
Signature · 4 lines
| Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com |
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
In reply to Benoît ThébaudeauHi Benoit
Quoted 35 lines · Benoît Thébaudeau
Hi Michael,
Quoted 28 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIOSION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>[...]
Quoted 9 lines
I have now tested the following peripherals on i.MX25 without any SION bit set: AUDMUX/SSI, eSDHC, FEC (except PHY access for which MDIO might have an issue without SION; Ethernet works but I have not checked whether this is possible at least partially without access to the PHY registers), GPIO, I2C, SLCDC, UART, and USB. Everything worked fine except the lack of SION for eSDHC CMD, which is true for all eSDHC instances (and not only for eSDHC1, so Linux's
arch/arm/boot/dts/imx25-pinfunc.hshould be fixed). Therefore, SION is mandatory for all the eSDHC CMD functions in
I have checked and u-boot does not have this pin-muxing. I think that this patch should go as it is and a separate patch like this one following should be applied after that. What do you think?
Quoted 30 lines
arch/arm/include/asm/arch-mx25/iomux-mx25.h, but it can be removed for everything else (I still have to carry out one more test to confirm this for FEC MDIO), and moved to the board files if necessary (but I don't think that any mainline board code is doing something fancy enough to need it).If the bus-status detection example in the documentation of SION in the reference manual is useful, it means that SION is probably required for all the signals requiring simultaneous output and input (such as I²C for device clock stretching or multi-master bus arbitration, except if the IP toggles between input and output low at each clock edge rather than between open-drain output high and output low), because there are no automatic SION signals between the peripherals and the pads but only direction signals that can request a single direction at a time. For bidirectional signals that do not require simultaneous output and input because they work in turns (such as FEC MDIO), SION can be required or not depending on whether the IP toggles the direction signal for each turn or always expects an input feedback while driving an open-drain output high. Even if SION is required for the I²C example mentioned above (which is unlikely as basic I²C transfers work fine and clock stretching detection is automatic and would always need the input state), the need for these advanced I²C features can be considered board-specific, so SION would still not be required in
iomux-mx25.h.In the end, for this patch, apart from the pending test for FEC MDIO:
Reviewed-by Benoît Thébaudeau <[email protected]>Best regards,
Benoît
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
Hi Michael,
Quoted 44 lines · Michael Trimarchi
Quoted 33 lines · Benoît Thébaudeau
Quoted 28 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIOSION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>[...]
Quoted 9 lines
I have now tested the following peripherals on i.MX25 without any SION bit set: AUDMUX/SSI, eSDHC, FEC (except PHY access for which MDIO might have an issue without SION; Ethernet works but I have not checked whether this is possible at least partially without access to the PHY registers), GPIO, I2C, SLCDC, UART, and USB. Everything worked fine except the lack of SION for eSDHC CMD, which is true for all eSDHC instances (and not only for eSDHC1, so Linux's
arch/arm/boot/dts/imx25-pinfunc.hshould be fixed). Therefore, SION is mandatory for all the eSDHC CMD functions in
Quoted 3 lines
I have checked and u-boot does not have this pin-muxing. I think that this patch should go as it is and a separate patch like this one following should be applied after that. What do you think?
Your patch is just fine as is. We do not need to add support for eSDHC2 in U-Boot unless some mainline board needs it. But eSDHC2 CMD should have SION set by default in Linux.
Quoted 49 lines
Quoted 25 lines
arch/arm/include/asm/arch-mx25/iomux-mx25.h, but it can be removed for everything else (I still have to carry out one more test to confirm this for FEC MDIO), and moved to the board files if necessary (but I don't think that any mainline board code is doing something fancy enough to need it).If the bus-status detection example in the documentation of SION in the reference manual is useful, it means that SION is probably required for all the signals requiring simultaneous output and input (such as I²C for device clock stretching or multi-master bus arbitration, except if the IP toggles between input and output low at each clock edge rather than between open-drain output high and output low), because there are no automatic SION signals between the peripherals and the pads but only direction signals that can request a single direction at a time. For bidirectional signals that do not require simultaneous output and input because they work in turns (such as FEC MDIO), SION can be required or not depending on whether the IP toggles the direction signal for each turn or always expects an input feedback while driving an open-drain output high. Even if SION is required for the I²C example mentioned above (which is unlikely as basic I²C transfers work fine and clock stretching detection is automatic and would always need the input state), the need for these advanced I²C features can be considered board-specific, so SION would still not be required in
iomux-mx25.h.Quoted 7 lines
In the end, for this patch, apart from the pending test for FEC MDIO:
Reviewed-by Benoît Thébaudeau <[email protected]>Best regards,
BenoîtFrom
d6b5bf4f1b6a0bcbcfd6ff2597fd2a7b3884cb3bMon Sep 17 00:00:00 2001From: Michael Trimarchi <[email protected]>
Date: Fri, 26 Jan 2018 08:42:54 +0100
Subject: [PATCH] imx: mx25: Add pinmux definition for ESDHC2Add pin mux of second esdhc interface. Set SION bin on the CMD muxing in order to avoid sdcard fail detection
Signed-off-by Michael Trimarchi <[email protected]>--- arch/arm/include/asm/arch-mx25/iomux-mx25.h | 8 ++++++++ 1 file changed, 8 insertions(+)arch/arm/include/asm/arch-mx25/iomux-mx25.h +0
-0
arch/arm/include/asm/arch-mx25/iomux-mx25.h enum { · line 228
Quoted 4 lines
arch/arm/include/asm/arch-mx25/iomux-mx25.h +1
-0@@ -225,15 +225,18 @@ enum {MX25_PAD_LD8__LD8 =IOMUX_PAD (0x2e0 ,0x0e8 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ),MX25_PAD_LD8__FEC_TX_ERR =IOMUX_PAD (0x2e0 ,0x0e8 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), + MX25_PAD_LD8__SDHC2_CMD = IOMUX_PAD(0x2e0, 0x0e8, 0x06, 0x4e0, 0, NO_PAD_CTRL),
SD CMD, so SION is required here.
Quoted 35 lines
arch/arm/include/asm/arch-mx25/iomux-mx25.h +5
-0MX25_PAD_LD9__LD9 =IOMUX_PAD (0x2e4 ,0x0ec ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ),MX25_PAD_LD9__FEC_COL =IOMUX_PAD (0x2e4 ,0x0ec ,0x05 ,0x504 ,1 ,NO_PAD_CTRL ), +MX25_PAD_LD9__SDHC2_CLK =IOMUX_PAD (0x2e4 ,0x0ec ,0x06 ,0x4dc ,0 ,NO_PAD_CTRL ),MX25_PAD_LD10__LD10 =IOMUX_PAD (0x2e8 ,0x0f0 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ),MX25_PAD_LD10__FEC_RX_ER =IOMUX_PAD (0x2e8 ,0x0f0 ,0x05 ,0x518 ,1 ,NO_PAD_CTRL ),MX25_PAD_LD11__LD11 =IOMUX_PAD (0x2ec ,0x0f4 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ),MX25_PAD_LD11__FEC_RDATA2 =IOMUX_PAD (0x2ec ,0x0f4 ,0x05 ,0x50c ,1 ,NO_PAD_CTRL ), +MX25_PAD_LD11__SDHC2_DAT1 =IOMUX_PAD (0x2ec ,0x0f4 ,0x06 ,0x4e8 ,0 ,NO_PAD_CTRL ),MX25_PAD_LD12__LD12 =IOMUX_PAD (0x2f0 ,0x0f8 ,0x00 ,0 ,0 ,PAD_CTL_SRE_FAST ), MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),@@ -287,8 +290,10 @@ enum {MX25_PAD_CSI_D6__CSI_D6 =IOMUX_PAD (0x328 ,0x130 ,0x00 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CSI_D6__GPIO_1_31 =IOMUX_PAD (0x328 ,0x130 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D6__SDHC2_CMD =IOMUX_PAD (0x328 ,0x130 ,0x12 ,0x4e0 ,1 ,NO_PAD_CTRL ),MX25_PAD_CSI_D7__CSI_D7 =IOMUX_PAD (0x32c ,0x134 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_D7__SDHC2_DAT_CLK =IOMUX_PAD (0x32C ,0x134 ,0x02 ,0x4dc ,1 ,NO_PAD_CTRL ),MX25_PAD_CSI_D7__GPIO_1_6 =IOMUX_PAD (0x32c ,0x134 ,0x05 ,0 ,0 ,NO_PAD_CTRL ), MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),@@ -298,15 +303,18 @@ enum {MX25_PAD_CSI_D9__GPIO_4_21 =IOMUX_PAD (0x334 ,0x13c ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CSI_MCLK__CSI_MCLK =IOMUX_PAD (0x338 ,0x140 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_MCLK__SDHC2_DAT0 =IOMUX_PAD (0x338 ,0x140 ,0x02 ,0x4e4 ,1 ,NO_PAD_CTRL ),MX25_PAD_CSI_MCLK__GPIO_1_8 =IOMUX_PAD (0x338 ,0x140 ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CSI_VSYNC__CSI_VSYNC =IOMUX_PAD (0x33c ,0x144 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
arch/arm/include/asm/arch-mx25/iomux-mx25.h enum { · line 320
Quoted 10 lines
arch/arm/include/asm/arch-mx25/iomux-mx25.h +2
-0MX25_PAD_CSI_HSYNC__CSI_HSYNC =IOMUX_PAD (0x340 ,0x148 ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_HSYNC__SDHC2_DAT2 =IOMUX_PAD (0x340 ,0x148 ,0x02 ,0x4ec ,1 ,NO_PAD_CTRL ),MX25_PAD_CSI_HSYNC__GPIO_1_10 =IOMUX_PAD (0x340 ,0x148 ,0x05 ,0 ,0 ,NO_PAD_CTRL ),MX25_PAD_CSI_PIXCLK__CSI_PIXCLK =IOMUX_PAD (0x344 ,0x14c ,0x00 ,0 ,0 ,NO_PAD_CTRL ), +MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 =IOMUX_PAD (0x344 ,0x14c ,0x02 ,0x4f0 ,1 ,NO_PAD_CTRL ),MX25_PAD_CSI_PIXCLK__GPIO_1_11 =IOMUX_PAD (0x344 ,0x14c ,0x05 ,0 ,0 ,NO_PAD_CTRL ), MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
Best regards,
Benoît
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
In reply to Benoît ThébaudeauQuoted 33 lines · Benoît Thébaudeau
Quoted 28 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIOSION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>[...]
Quoted 14 lines
I have now tested the following peripherals on i.MX25 without any SION bit set: AUDMUX/SSI, eSDHC, FEC (except PHY access for which MDIO might have an issue without SION; Ethernet works but I have not checked whether this is possible at least partially without access to the PHY registers), GPIO, I2C, SLCDC, UART, and USB. Everything worked fine except the lack of SION for eSDHC CMD, which is true for all eSDHC instances (and not only for eSDHC1, so Linux's
arch/arm/boot/dts/imx25-pinfunc.hshould be fixed). Therefore, SION is mandatory for all the eSDHC CMD functions inarch/arm/include/asm/arch-mx25/iomux-mx25.h, but it can be removed for everything else (I still have to carry out one more test to confirm this for FEC MDIO), and moved to the board files if necessary (but I don't think that any mainline board code is doing something fancy enough to need it).
I confirm that FEC RMII register access works fine without setting SION for MDIO.
Benoît
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
Hi Stefano
Do I need to resend with you in CC?
For some reason I forget to include you
Michael
Quoted 53 lines · Benoît Thébaudeau
Quoted 33 lines · Benoît Thébaudeau
Quoted 28 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIOSION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>[...]
Quoted 14 lines
I have now tested the following peripherals on i.MX25 without any SION bit set: AUDMUX/SSI, eSDHC, FEC (except PHY access for which MDIO might have an issue without SION; Ethernet works but I have not checked whether this is possible at least partially without access to the PHY registers), GPIO, I2C, SLCDC, UART, and USB. Everything worked fine except the lack of SION for eSDHC CMD, which is true for all eSDHC instances (and not only for eSDHC1, so Linux's
arch/arm/boot/dts/imx25-pinfunc.hshould be fixed). Therefore, SION is mandatory for all the eSDHC CMD functions inarch/arm/include/asm/arch-mx25/iomux-mx25.h, but it can be removed for everything else (I still have to carry out one more test to confirm this for FEC MDIO), and moved to the board files if necessary (but I don't think that any mainline board code is doing something fancy enough to need it).I confirm that FEC RMII register access works fine without setting SION for MDIO.
Benoît
Signature · 4 lines
| Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com |
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
Hi Michael,
Quoted 6 lines · Michael Nazzareno Trimarchi
Hi Stefano
Do I need to resend with you in CC?
For some reason I forget to include you
No, don't worry, I have already got it :-)
Regards,
Stefano
Quoted 59 lines
Michael
Quoted 53 lines · Benoît Thébaudeau
Quoted 33 lines · Benoît Thébaudeau
Quoted 28 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIOSION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>[...]
Quoted 14 lines
I have now tested the following peripherals on i.MX25 without any SION bit set: AUDMUX/SSI, eSDHC, FEC (except PHY access for which MDIO might have an issue without SION; Ethernet works but I have not checked whether this is possible at least partially without access to the PHY registers), GPIO, I2C, SLCDC, UART, and USB. Everything worked fine except the lack of SION for eSDHC CMD, which is true for all eSDHC instances (and not only for eSDHC1, so Linux's
arch/arm/boot/dts/imx25-pinfunc.hshould be fixed). Therefore, SION is mandatory for all the eSDHC CMD functions inarch/arm/include/asm/arch-mx25/iomux-mx25.h, but it can be removed for everything else (I still have to carry out one more test to confirm this for FEC MDIO), and moved to the board files if necessary (but I don't think that any mainline board code is doing something fancy enough to need it).I confirm that FEC RMII register access works fine without setting SION for MDIO.
Benoît
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
In reply to Michael TrimarchiHi Michael,
Quoted 23 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIO
Quoted 5 lines
SION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>
Please keep my previous Reviewed-by tag.
Here it goes again:
Thanks
PATCH v3 1/1 imx: mx25: Remove SION bit in all pin-mux that are safe
In reply to Michael TrimarchiQuoted 23 lines · Michael Trimarchi
SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro.
We get some malfunction as raised by following thread
https://www.spinics.net/lists/linux-usb/msg162574.html
As reported by this application note:
https://www.nxp.com/docs/en/application-note/AN5078.pdfThe software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin.
The SION bit can be used in:
• Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input
• GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIO
Quoted 5 lines
SION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file
Signed-off-by Michael Trimarchi <[email protected]>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================