aspeed: watchdog and devicetree updates

This series provides a number of fixes for the AST2500 watchdog driver and devicetree. It also adds some features such as allowing configuration of whether or not the watchdog should boot from the alternate flash after a watchdog timeout.

Milton Miller (5):
ARM: dts: aspeed-g5: fix watchdog 3 definition
watchdog: aspeed: update ASPEED reference dev tree properties for
config
watchdog: aspeed: Fix translation of reset mode to ctrl register
arm: dts: aspeed: witherspoon: configure watchdogs
watchdog: aspeed: Allow configuring for alternate boot

 .../devicetree/bindings/watchdog/aspeed-wdt.txt          |  3 +++
 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts         |  8 ++++++++
 arch/arm/boot/dts/aspeed-g5.dtsi                         |  4 ++--
 drivers/watchdog/aspeed_wdt.c                            | 16 ++++++++++++----
 4 files changed, 25 insertions(+), 6 deletions(-)

1.8.3.1

From: Milton Miller <[email protected]>

Fix wdt3 reg and compatible properties.

The ast2500 generation SOC has added a third watchdog. The address specified is incorrect, and the compatible was not updated when upstream requested the SOC name in the compatible property.

---
 arch/arm/boot/dts/aspeed-g5.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index ba3607c..a8a237d 100644
@@ -317,8 +317,8 @@
 			};
 
 			wdt3: wdt@1e785040 {
-				compatible = "aspeed,wdt";
-				reg = <0x1e785074 0x1c>;
+				compatible = "aspeed,ast2500-wdt";
+				reg = <0x1e785040 0x1c>;
 				status = "disabled";
 			};
 

1.8.3.1

From: Milton Miller <[email protected]>

Update the dev-4.10 branch from the v4 upstream propsal to the v5 version before proposing further changes.

v4: http://patchwork.ozlabs.org/patch/785315/
v5: http://patchwork.ozlabs.org/patch/789692/

---
 drivers/watchdog/aspeed_wdt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

index ba9b938..9d40802 100644
@@ -194,7 +194,7 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
 	np = pdev->dev.of_node;
 	ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
 	if (ret) {
-		wdt->ctrl |= WDT_CTRL_RESET_SYSTEM;
+		wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
 	} else {
 		if (!strcmp(reset_type, "cpu"))
 			wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU;

@@ -202,6 +202,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
 			wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC;
 		else if (!strcmp(reset_type, "system"))
 			wdt->ctrl |= WDT_CTRL_RESET_SYSTEM;
+		else if (strcmp(reset_type, "none"))
+			return -EINVAL;
 	}
 	if (of_property_read_bool(np, "aspeed,external-signal"))
 		wdt->ctrl |= WDT_CTRL_WDT_EXT;

1.8.3.1

From: Milton Miller <[email protected]>

Assert RESET_SYSTEM bit for any reset and set MODE field from reset type.

The watchdog control register has a RESET_SYSTEM bit that is really closer to activate a reset, and RESET_SYSTEM_MODE field that chooses how much to reset.

Before this patch, a node without these optional property would do a SOC reset, but a node with properties requesting a cpu or SOC reset would do nothing and a node requesting a system reset would do a SOC reset.

---
 drivers/watchdog/aspeed_wdt.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

index 9d40802..7eef0dd 100644
@@ -197,11 +197,14 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
 		wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
 	} else {
 		if (!strcmp(reset_type, "cpu"))
-			wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU;
+			wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
+				     WDT_CTRL_RESET_SYSTEM;
 		else if (!strcmp(reset_type, "soc"))
-			wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC;
+			wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
+				     WDT_CTRL_RESET_SYSTEM;
 		else if (!strcmp(reset_type, "system"))
-			wdt->ctrl |= WDT_CTRL_RESET_SYSTEM;
+			wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
+				     WDT_CTRL_RESET_SYSTEM;
 		else if (strcmp(reset_type, "none"))
 			return -EINVAL;
 	}

1.8.3.1

From: Milton Miller <[email protected]>

Add additional device tree configuration of the watchdogs to prove the config works or does not work.

---
 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

index 68058ec..bb94321 100644
@@ -654,8 +654,16 @@
 
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_wdtrst1_default>;
+
+	status = "okay";
 };
 
 &wdt2 {
 	status = "okay";
+	aspeed,reset-type = "soc";
+};
+
+&wdt3 {
+	status = "okay";
+	aspeed,reset-type = "system";
 };

1.8.3.1

From: Milton Miller <[email protected]>

Allow the device tree to specify a watchdog to fallover to the alternate boot source.

The aspeeed watchdog can set a latch directing flash chip select 0 to chip select 1, allowing boot from an alternate media if the watchdog is not reset in time. On the ast2400 bank 1 also goes to flash bank 1, while on the ast2500 the chip selects are swapped.

---
 Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 3 +++
 drivers/watchdog/aspeed_wdt.c                             | 3 +++
 2 files changed, 6 insertions(+)

index 7aa885f..82dedaa 100644
@@ -33,6 +33,9 @@ Optional properties:
         - none: No reset is performed on timeout. Assumes another watchdog
                 engine is responsible for this.
 
+ - aspeed,secondary-boot: If property is present and watchdog activates,
+			  swtich to alternate boot source
+
  - aspeed,interrupt:	If property is present then interrupt CPU.
 			If not specified then don't interrupt CPU.
 

index 7eef0dd..1dd687b 100644
@@ -34,6 +34,7 @@ struct aspeed_wdt {
 #define WDT_RELOAD_VALUE	0x04
 #define WDT_RESTART		0x08
 #define WDT_CTRL		0x0C
+#define   WDT_CTRL_BOOT_SECONDARY	BIT(7)
 #define   WDT_CTRL_RESET_MODE_SOC	(0x00 << 5)
 #define   WDT_CTRL_RESET_MODE_FULL_CHIP	(0x01 << 5)
 #define   WDT_CTRL_RESET_MODE_ARM_CPU	(0x10 << 5)

@@ -210,6 +211,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
 	}
 	if (of_property_read_bool(np, "aspeed,external-signal"))
 		wdt->ctrl |= WDT_CTRL_WDT_EXT;
+	if (of_property_read_bool(np, "aspeed,secondary-boot"))
+		wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
 
 	if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
 		/*

1.8.3.1