Patch "drm/amdgpu: Fix SDMA load/unload sequence on HWS disabled mode" has been added to the 4.9-stable tree
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This is a note to let you know that I've just added the patch titled
drm/amdgpu: Fix SDMA load/unload sequence on HWS disabled mode
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amdgpu-fix-sdma-load-unload-sequence-on-hws-disabled-mode.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From foo@baz Thu Feb 1 14:00:34 CET 2018
From: Felix Kuehling <[email protected]>
Date: Wed, 1 Nov 2017 19:21:55 -0400
Subject: drm/amdgpu: Fix SDMA load/unload sequence on HWS disabled mode
From: Felix Kuehling <[email protected]>
[ Upstream commit cf21654b40968609779751b34e7923180968fe5b ]
Fix the SDMA load and unload sequence as suggested by HW document.
--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 47 +++++++++++++++------- 1 file changed, 34 insertions(+), 13 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +34 -13
@@ -367,29 +367,50 @@ static int kgd_hqd_sdma_load(struct kgd_ {struct amdgpu_device *adev =get_amdgpu_device (kgd);struct cik_sdma_rlc_registers *m; +unsigned long end_jiffies;uint32_t sdma_base_addr; +uint32_t data; m =get_sdma_mqd (mqd); sdma_base_addr =get_sdma_base_addr (m); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, - m->sdma_rlc_virtual_addr); +WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, + m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK )); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_BASE, - m->sdma_rlc_rb_base); + end_jiffies =msecs_to_jiffies (2000 ) + jiffies; +while (true) { + data =RREG32 (sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); +if (data &SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK ) +break ; +if (time_after (jiffies, end_jiffies)) +return -ETIME ; +usleep_range (500 ,1000 ); + } +if (m->sdma_engine_id) { + data =RREG32 (mmSDMA1_GFX_CONTEXT_CNTL); + data =REG_SET_FIELD (data,SDMA1_GFX_CONTEXT_CNTL , +RESUME_CTX ,0 ); +WREG32 (mmSDMA1_GFX_CONTEXT_CNTL, data); + }else { + data =RREG32 (mmSDMA0_GFX_CONTEXT_CNTL); + data =REG_SET_FIELD (data,SDMA0_GFX_CONTEXT_CNTL , +RESUME_CTX ,0 ); +WREG32 (mmSDMA0_GFX_CONTEXT_CNTL, data); + } +WREG32 (sdma_base_addr + mmSDMA0_RLC0_DOORBELL, + m->sdma_rlc_doorbell); +WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_RPTR,0 ); +WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,0 ); +WREG32 (sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, + m->sdma_rlc_virtual_addr); +WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, m->sdma_rlc_rb_base_hi); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, m->sdma_rlc_rb_rptr_addr_lo); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, m->sdma_rlc_rb_rptr_addr_hi); - -WREG32 (sdma_base_addr + mmSDMA0_RLC0_DOORBELL, - m->sdma_rlc_doorbell); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, m->sdma_rlc_rb_cntl);
@@ -493,9 +514,9 @@ static int kgd_hqd_sdma_destroy(struct k }WREG32 (sdma_base_addr + mmSDMA0_RLC0_DOORBELL,0 ); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_RPTR,0 ); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,0 ); -WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_BASE,0 ); +WREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, +RREG32 (sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | +SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK );return 0 ; }
Patches currently in stable-queue which might be from [email protected] are
queue-4.9/drm-amdkfd-fix-sdma-oversubsription-handling.patch queue-4.9/drm-amdkfd-fix-sdma-ring-buffer-size-calculation.patch queue-4.9/drm-amdgpu-fix-sdma-load-unload-sequence-on-hws-disabled-mode.patch