Add support for remoteproc modem-pil on SDM845 SoCs
Subsystems (5)
cover Add support for remoteproc modem-pil on SDM845 SoCs
This patch series add support for remoteproc Q6v5 modem-pil on Qualcomm SDM845 SoC. The first patch adds AOSS (Always on subsystem) reset driver to provide for mss reset line. The third patch adds the APCS offset for SDM845. The last couple of patches add the resets sequence for Q6 on SDM845 and adds helper functions for arbitrary reset assert/deassert sequences.
sibis (6):
reset: qcom: AOSS (Always on subsystem) reset controller
dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
mailbox: Add support for Qualcomm SDM845 SoCs
dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
remoteproc: qcom: Add support for mss remoteproc on SDM845
remoteproc: qcom: Reorder active clks enable and reset
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 3 +- .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +- .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++ drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + drivers/remoteproc/qcom_q6v5_pil.c | 149 +++++++++++++++++-- drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++ include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ 9 files changed, 386 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt create mode 100644 drivers/reset/reset-qcom-aoss.c create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 1/6 reset: qcom: AOSS (Always on subsystem) reset controller
Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by sibis <[email protected]>
--- .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++ drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++ include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ 5 files changed, 243 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt create mode 100644 drivers/reset/reset-qcom-aoss.c create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt new file +54 -0
@@ -0,0 +1,54 @@ +Qualcomm AOSS Reset Controller +====================================== + +This binding describes a reset-controller found on AOSS (Always on SubSysem) +for Qualcomm SDM845 SoCs. + +Required properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be: + "qcom,aoss-reset-sdm845", "syscon" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: must specify the base address and size of the + syscon device. + + +- #reset-cells: + Usage: required + Value type: <uint> + Definition: must be 1; cell entry represents the reset index. + +example: + +aoss_reset: qcom,reset-controller@b2e0100 { + compatible = "qcom,aoss-reset-sdm845", "syscon"; + reg = <0xc2b0000 0x20004>; + #reset-cells = <1>; +}; + + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +Example: + + modem-pil@4080000 { + ... + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; + reset-names = "mss_restart"; + + ... + }; + +For list of all valid reset indicies see +<dt-bindings/reset/qcom,aoss-sdm845.h>
drivers/reset/Kconfig +10 -0
@@ -81,6 +81,16 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_QCOM_AOSS + bool "Qcom AOSS Reset Driver" + depends on ARCH_QCOM || COMPILE_TEST + select MFD_SYSCON + help + This enables the AOSS (Always On SubSystem) reset driver + for Qcom SoCs. Say Y if you want to control reset signals + provided by AOSS for Modem, Venus, ADSP, GPU, Camera, + Wireless, Display subsystem. Otherwise, say N. + config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
drivers/reset/Makefile +1 -0
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
drivers/reset/reset-qcom-aoss.c new file +161 -0
161 lines not on this page · raw message
include/dt-bindings/reset/qcom,aoss-sdm845.h new file +17 -0
@@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (C) 2018 The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Philipp Zabel
maintainerRe: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
Hi sibis,
thank you for the patch. I have a few questions and comments below.
Quoted 81 lines · sibis
Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by sibis <[email protected]>--- .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++ drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++ include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ 5 files changed, 243 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt create mode 100644 drivers/reset/reset-qcom-aoss.c create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.hDocumentation/devicetree/bindings/reset/qcom,aoss-reset.txt new file +54
-0@@ -0,0 +1,54 @@ +Qualcomm AOSS Reset Controller +====================================== + +This binding describes a reset-controller found on AOSS (Always on SubSysem) +for Qualcomm SDM845 SoCs. + +Required properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be: + "qcom,aoss-reset-sdm845", "syscon" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: must specify the base address and size of the + syscon device. + + +- #reset-cells: + Usage: required + Value type: <uint> + Definition: must be 1; cell entry represents the reset index. + +example: + +aoss_reset: qcom,reset-controller@b2e0100 { + compatible = "qcom,aoss-reset-sdm845", "syscon"; + reg = <0xc2b0000 0x20004>; + #reset-cells = <1>; +}; + + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +Example: + + modem-pil@4080000 { + ... + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; + reset-names = "mss_restart"; + + ... + }; + +For list of all valid reset indicies see +<dt-bindings/reset/qcom,aoss-sdm845.h>drivers/reset/Kconfig +0
-0
drivers/reset/Kconfig config RESET_PISTACHIO · line 86
Quoted 6 lines
drivers/reset/Kconfig +3
-0@@ -81,6 +81,16 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_QCOM_AOSS + bool "Qcom AOSS Reset Driver" + depends on ARCH_QCOM || COMPILE_TEST
Do all ARCH_QCOM have AOSS? If so, should this be enabled by default?
drivers/reset/Kconfig config RESET_PISTACHIO · line 90
Quoted 4 lines
drivers/reset/Kconfig +4
-0+ select MFD_SYSCON + help + This enables the AOSS (Always On SubSystem) reset driver + for Qcom SoCs. Say Y if you want to control reset signals
Is Qcom and Qualcomm interchangeable?
Quoted 86 lines
drivers/reset/Kconfig +3
-0+ provided by AOSS for Modem, Venus, ADSP, GPU, Camera, + Wireless, Display subsystem. Otherwise, say N. + config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZXdrivers/reset/Makefile +1
-0@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.odrivers/reset/reset-qcom-aoss.c new file +62
-0@@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (C) 2018 The Linux Foundation. All rights reserved. +*/ + +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/regmap.h> +#include <linux/of_device.h> +#include <dt-bindings/reset/qcom,aoss-sdm845.h> + +struct qcom_aoss_reset_map { +unsigned int reg; +u8 bit; +}; + +struct qcom_aoss_desc { +const struct regmap_config *config; +const struct qcom_aoss_reset_map *resets; +int delay; +size_t num_resets; +}; + +struct qcom_aoss_reset_data { +struct reset_controller_dev rcdev; +struct regmap *regmap; +const struct qcom_aoss_desc *desc; +}; + +static const struct regmap_config aoss_sdm845_regmap_config = { + .name ="aoss-reset" , + .reg_bits =32 , + .reg_stride =4 , + .val_bits =32 , + .max_register =0x20000 , + .fast_io = true, +}; + +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = { + [AOSS_CC_MSS_RESTART ] = {0x0 ,0 }, + [AOSS_CC_CAMSS_RESTART ] = {0x1000 ,0 }, + [AOSS_CC_VENUS_RESTART ] = {0x2000 ,0 }, + [AOSS_CC_GPU_RESTART ] = {0x3000 ,0 }, + [AOSS_CC_DISPSS_RESTART ] = {0x4000 ,0 }, + [AOSS_CC_WCSS_RESTART ] = {0x10000 ,0 }, + [AOSS_CC_LPASS_RESTART ] = {0x20000 ,0 }, +}; + +static const struct qcom_aoss_desc aoss_sdm845_desc = { + .config = &aoss_sdm845_regmap_config, + .resets = aoss_sdm845_resets, +/* Wait 6 32kHz sleep cycles for reset */ + .delay =200 , + .num_resets =ARRAY_SIZE (aoss_sdm845_resets), +}; + +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data ( +struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
drivers/reset/reset-qcom-aoss.c line 72
Quoted 10 lines
drivers/reset/reset-qcom-aoss.c new file +10
-0+} + +static int qcom_aoss_control_assert (struct reset_controller_dev *rcdev, +unsigned long idx) +{ +struct qcom_aoss_reset_data *data =to_qcom_aoss_reset_data (rcdev); +const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + +if (idx >= rcdev->nr_resets) +return -EINVAL ;
This check is not necessary. For all drivers that don't set of_xlate, the default of_reset_simple_xlate already makes sure no reset_control is ever returned with rstc->id >= rcdev->nr_resets.
drivers/reset/reset-qcom-aoss.c line 85
Quoted 12 lines
drivers/reset/reset-qcom-aoss.c new file +12
-0+return regmap_update_bits (data->regmap, map->reg, +BIT (map->bit),BIT (map->bit)); +} + +static int qcom_aoss_control_deassert (struct reset_controller_dev *rcdev, +unsigned long idx) +{ +struct qcom_aoss_reset_data *data =to_qcom_aoss_reset_data (rcdev); +const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + +if (idx >= rcdev->nr_resets) +return -EINVAL ;
Same here.
drivers/reset/reset-qcom-aoss.c line 96
Quoted 10 lines
drivers/reset/reset-qcom-aoss.c new file +10
-0+return regmap_update_bits (data->regmap, map->reg,BIT (map->bit),0 ); +} + +static int qcom_aoss_control_reset (struct reset_controller_dev *rcdev, +unsigned long idx) +{ +struct qcom_aoss_reset_data *data =to_qcom_aoss_reset_data (rcdev); +int ret; + + ret = rcdev->ops->assert (rcdev, idx);
Don't use the ops function pointers here, just call qcom_aoss_control_assert directly.
drivers/reset/reset-qcom-aoss.c line 106
Quoted 10 lines
drivers/reset/reset-qcom-aoss.c new file +10
-0+if (ret) +return ret; + +udelay (data->desc->delay); + + ret = rcdev->ops->deassert (rcdev, idx); +if (ret) +return ret; + +return 0 ;
This can be simplified to just
return qcom_aoss_control_deassert(rcdev, idx);
Quoted 5 lines
drivers/reset/reset-qcom-aoss.c new file +5
-0+} + +static const struct reset_control_ops qcom_aoss_reset_ops = { + .reset = qcom_aoss_control_reset, + .assert = qcom_aoss_control_assert,
drivers/reset/reset-qcom-aoss.c line 121
Quoted 10 lines
drivers/reset/reset-qcom-aoss.c new file +10
-0+ .deassert = qcom_aoss_control_deassert, +}; + +static int qcom_aoss_reset_probe (struct platform_device *pdev) +{ +struct qcom_aoss_reset_data *data; +struct device *dev = &pdev->dev; +const struct qcom_aoss_desc *desc; + + desc =of_device_get_match_data (&pdev->dev);
You could use dev here instead of pdev->dev.
Quoted 9 lines
drivers/reset/reset-qcom-aoss.c new file +9
-0+if (!desc) +return -EINVAL ; + + data =devm_kzalloc (dev,sizeof (*data),GFP_KERNEL ); +if (!data) +return -ENOMEM ; + + data->desc = desc; + data->regmap =syscon_node_to_regmap (dev->of_node);
drivers/reset/reset-qcom-aoss.c line 140
Quoted 10 lines
drivers/reset/reset-qcom-aoss.c new file +10
-0+if (IS_ERR (data->regmap)) { +dev_err (dev,"Unable to get aoss-reset regmap" ); +return PTR_ERR (data->regmap); + } +regmap_attach_dev (dev, data->regmap, desc->config); + + data->rcdev.owner =THIS_MODULE ; + data->rcdev.ops = &qcom_aoss_reset_ops; + data->rcdev.nr_resets = desc->num_resets; + data->rcdev.of_node = pdev->dev.of_node;
And here.
drivers/reset/reset-qcom-aoss.c line 142
Quoted 1 line
drivers/reset/reset-qcom-aoss.c new file +1
-0+return devm_reset_controller_register (&pdev->dev, &data->rcdev);
And here.
drivers/reset/reset-qcom-aoss.c line 146
Quoted 4 lines
drivers/reset/reset-qcom-aoss.c new file +4
-0+} + +static const struct of_device_id qcom_aoss_reset_of_match[] = { + { .compatible ="qcom,aoss-reset-sdm845" , .data = &aoss_sdm845_desc},
Consider adding a space between &aoss_sdm845_desc and } ...
drivers/reset/reset-qcom-aoss.c line 153
Quoted 7 lines
drivers/reset/reset-qcom-aoss.c new file +7
-0+ {} +}; + +static struct platform_driver qcom_aoss_reset_driver = { + .probe = qcom_aoss_reset_probe, + .driver = { + .name ="qcom_aoss_reset" ,
... and removing the superfluous space here.
Quoted 21 lines
drivers/reset/reset-qcom-aoss.c new file +8
-0+ .of_match_table = qcom_aoss_reset_of_match, + }, +}; + +builtin_platform_driver (qcom_aoss_reset_driver); + +MODULE_DESCRIPTION ("Qualcomm AOSS Reset Driver" ); +MODULE_LICENSE ("GPL v2" );include/dt-bindings/reset/qcom,aoss-sdm845.h new file +7
-0@@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (C) 2018 The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H
include/dt-bindings/reset/qcom,aoss-sdm845.h line 17
Quoted 10 lines
include/dt-bindings/reset/qcom,aoss-sdm845.h new file +10
-0+ +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif
regards
Philipp
Re: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller
Hi Philipp,
Thanks for the review. I will post out the v2 of the patch series.
Quoted 89 lines · Philipp Zabel
Hi sibis,
thank you for the patch. I have a few questions and comments below.
Quoted 84 lines · sibis
Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem
Signed-off-by sibis <[email protected]>--- .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++ drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++ include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ 5 files changed, 243 insertions(+)create mode 100644
Documentation/devicetree/bindings/reset/qcom,aoss-reset.txtcreate mode 100644drivers/reset/reset-qcom-aoss.c
create mode 100644include/dt-bindings/reset/qcom,aoss-sdm845.hDocumentation/devicetree/bindings/reset/qcom,aoss-reset.txt new file +54
-0@@ -0,0 +1,54 @@ +Qualcomm AOSS Reset Controller +====================================== + +This binding describes a reset-controller found on AOSS (Always on SubSysem) +for Qualcomm SDM845 SoCs. + +Required properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be: + "qcom,aoss-reset-sdm845", "syscon" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: must specify the base address and size of the + syscon device. + + +- #reset-cells: + Usage: required + Value type: <uint> + Definition: must be 1; cell entry represents the reset index. + +example: + +aoss_reset: qcom,reset-controller@b2e0100 { + compatible = "qcom,aoss-reset-sdm845", "syscon"; + reg = <0xc2b0000 0x20004>; + #reset-cells = <1>; +}; + + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +Example: + + modem-pil@4080000 { + ... + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; + reset-names = "mss_restart"; + + ... + }; + +For list of all valid reset indicies see +<dt-bindings/reset/qcom,aoss-sdm845.h>drivers/reset/Kconfig +0
-0@@ -81,6 +81,16 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs.
Quoted 6 lines
drivers/reset/Kconfig config RESET_PISTACHIO · line 86
Quoted 3 lines
drivers/reset/Kconfig +3
-0+config RESET_QCOM_AOSS + bool "Qcom AOSS Reset Driver" + depends on ARCH_QCOM || COMPILE_TESTDo all
ARCH_QCOMhave AOSS? If so, should this be enabled by default?
AOSS reset is currently supported on SDM845 SoCs and not on any of other the previously upstreamed Qualcomm SoCs. I will change description to convey the same. I needs to explicitly enabled for SDM845 SoCs.
Quoted 7 lines
drivers/reset/Kconfig config RESET_PISTACHIO · line 90
Quoted 4 lines
drivers/reset/Kconfig +4
-0+ select MFD_SYSCON + help + This enables the AOSS (Always On SubSystem) reset driver + for Qcom SoCs. Say Y if you want to control reset signalsIs Qcom and Qualcomm interchangeable?
Though it is used interchangeably, it will make more sense if I change it to Qualcomm here.
Quoted 92 lines
Quoted 92 lines
drivers/reset/Kconfig +3
-0+ provided by AOSS for Modem, Venus, ADSP, GPU, Camera, + Wireless, Display subsystem. Otherwise, say N. + config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZXdrivers/reset/Makefile +1
-0@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.odrivers/reset/reset-qcom-aoss.c new file +68
-0@@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (C) 2018 The Linux Foundation. All rights reserved. +*/ + +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/regmap.h> +#include <linux/of_device.h> +#include <dt-bindings/reset/qcom,aoss-sdm845.h> + +struct qcom_aoss_reset_map { +unsigned int reg; +u8 bit; +}; + +struct qcom_aoss_desc { +const struct regmap_config *config; +const struct qcom_aoss_reset_map *resets; +int delay; +size_t num_resets; +}; + +struct qcom_aoss_reset_data { +struct reset_controller_dev rcdev; +struct regmap *regmap; +const struct qcom_aoss_desc *desc; +}; + +static const struct regmap_config aoss_sdm845_regmap_config = { + .name ="aoss-reset" , + .reg_bits =32 , + .reg_stride =4 , + .val_bits =32 , + .max_register =0x20000 , + .fast_io = true, +}; + +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = { + [AOSS_CC_MSS_RESTART ] = {0x0 ,0 }, + [AOSS_CC_CAMSS_RESTART ] = {0x1000 ,0 }, + [AOSS_CC_VENUS_RESTART ] = {0x2000 ,0 }, + [AOSS_CC_GPU_RESTART ] = {0x3000 ,0 }, + [AOSS_CC_DISPSS_RESTART ] = {0x4000 ,0 }, + [AOSS_CC_WCSS_RESTART ] = {0x10000 ,0 }, + [AOSS_CC_LPASS_RESTART ] = {0x20000 ,0 }, +}; + +static const struct qcom_aoss_desc aoss_sdm845_desc = { + .config = &aoss_sdm845_regmap_config, + .resets = aoss_sdm845_resets, +/* Wait 6 32kHz sleep cycles for reset */ + .delay =200 , + .num_resets =ARRAY_SIZE (aoss_sdm845_resets), +}; + +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data ( +struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev); +} + +static int qcom_aoss_control_assert (struct reset_controller_dev *rcdev, +unsigned long idx) +{ +struct qcom_aoss_reset_data *data =to_qcom_aoss_reset_data (rcdev);
Quoted 9 lines
drivers/reset/reset-qcom-aoss.c line 72
Quoted 4 lines
drivers/reset/reset-qcom-aoss.c new file +4
-0+const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + +if (idx >= rcdev->nr_resets) +return -EINVAL ;This check is not necessary. For all drivers that don't set
of_xlate, the defaultof_reset_simple_xlatealready makes sure noreset_controlis ever returned withrstc->id>=rcdev->nr_resets.
Will remove it
Quoted 6 lines
Quoted 6 lines
drivers/reset/reset-qcom-aoss.c new file +6
-0+return regmap_update_bits (data->regmap, map->reg, +BIT (map->bit),BIT (map->bit)); +} + +static int qcom_aoss_control_deassert (struct reset_controller_dev *rcdev, +unsigned long idx)
Quoted 9 lines
drivers/reset/reset-qcom-aoss.c line 72
Quoted 6 lines
drivers/reset/reset-qcom-aoss.c new file +6
-0+{ +struct qcom_aoss_reset_data *data =to_qcom_aoss_reset_data (rcdev); +const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + +if (idx >= rcdev->nr_resets) +return -EINVAL ;Same here.
ditto
Quoted 5 lines
Quoted 5 lines
drivers/reset/reset-qcom-aoss.c new file +5
-0+return regmap_update_bits (data->regmap, map->reg,BIT (map->bit),0 ); +} + +static int qcom_aoss_control_reset (struct reset_controller_dev *rcdev, +unsigned long idx)
Quoted 8 lines
drivers/reset/reset-qcom-aoss.c line 96
Quoted 5 lines
drivers/reset/reset-qcom-aoss.c new file +5
-0+{ +struct qcom_aoss_reset_data *data =to_qcom_aoss_reset_data (rcdev); +int ret; + + ret = rcdev->ops->assert (rcdev, idx);Don't use the ops function pointers here, just call
qcom_aoss_control_assertdirectly.
sure will repace it.
Quoted 14 lines
drivers/reset/reset-qcom-aoss.c line 106
Quoted 11 lines
drivers/reset/reset-qcom-aoss.c new file +10
-0+if (ret) +return ret; + +udelay (data->desc->delay); + + ret = rcdev->ops->deassert (rcdev, idx); +if (ret) +return ret; + +return 0 ;This can be simplified to just
Quoted 2 lines
return qcom_aoss_control_deassert(rcdev, idx);
ditto
Quoted 9 lines
Quoted 9 lines
drivers/reset/reset-qcom-aoss.c new file +9
-0+} + +static const struct reset_control_ops qcom_aoss_reset_ops = { + .reset = qcom_aoss_control_reset, + .assert = qcom_aoss_control_assert, + .deassert = qcom_aoss_control_deassert, +}; + +static int qcom_aoss_reset_probe (struct platform_device *pdev)
Quoted 9 lines
drivers/reset/reset-qcom-aoss.c line 121
Quoted 6 lines
drivers/reset/reset-qcom-aoss.c new file +6
-0+{ +struct qcom_aoss_reset_data *data; +struct device *dev = &pdev->dev; +const struct qcom_aoss_desc *desc; + + desc =of_device_get_match_data (&pdev->dev);You could use dev here instead of
pdev->dev.
Yeah I will replace all instances of pdev->dev with dev
Quoted 26 lines
Quoted 9 lines
drivers/reset/reset-qcom-aoss.c new file +9
-0+if (!desc) +return -EINVAL ; + + data =devm_kzalloc (dev,sizeof (*data),GFP_KERNEL ); +if (!data) +return -ENOMEM ; + + data->desc = desc; + data->regmap =syscon_node_to_regmap (dev->of_node);drivers/reset/reset-qcom-aoss.c line 140
Quoted 10 lines
drivers/reset/reset-qcom-aoss.c new file +10
-0+if (IS_ERR (data->regmap)) { +dev_err (dev,"Unable to get aoss-reset regmap" ); +return PTR_ERR (data->regmap); + } +regmap_attach_dev (dev, data->regmap, desc->config); + + data->rcdev.owner =THIS_MODULE ; + data->rcdev.ops = &qcom_aoss_reset_ops; + data->rcdev.nr_resets = desc->num_resets; + data->rcdev.of_node = pdev->dev.of_node;And here.
drivers/reset/reset-qcom-aoss.c line 142
Quoted 1 line
drivers/reset/reset-qcom-aoss.c new file +1
-0+return devm_reset_controller_register (&pdev->dev, &data->rcdev);And here.
Quoted 7 lines
drivers/reset/reset-qcom-aoss.c line 146
Quoted 4 lines
drivers/reset/reset-qcom-aoss.c new file +4
-0+} + +static const struct of_device_id qcom_aoss_reset_of_match[] = { + { .compatible ="qcom,aoss-reset-sdm845" , .data = &aoss_sdm845_desc},Consider adding a space between
&aoss_sdm845_descand } ...
sure will do
Quoted 9 lines
drivers/reset/reset-qcom-aoss.c line 153
Quoted 7 lines
drivers/reset/reset-qcom-aoss.c new file +7
-0+ {} +}; + +static struct platform_driver qcom_aoss_reset_driver = { + .probe = qcom_aoss_reset_probe, + .driver = { + .name ="qcom_aoss_reset" ,... and removing the superfluous space here.
Will remove the superfluous spacing
Quoted 36 lines
Quoted 22 lines
drivers/reset/reset-qcom-aoss.c new file +8
-0+ .of_match_table = qcom_aoss_reset_of_match, + }, +}; + +builtin_platform_driver (qcom_aoss_reset_driver); + +MODULE_DESCRIPTION ("Qualcomm AOSS Reset Driver" ); +MODULE_LICENSE ("GPL v2" );include/dt-bindings/reset/qcom,aoss-sdm845.h new file +7
-0@@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (C) 2018 The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_Hinclude/dt-bindings/reset/qcom,aoss-sdm845.h line 17
Quoted 10 lines
include/dt-bindings/reset/qcom,aoss-sdm845.h new file +10
-0+ +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif regards
Philipp
Signature · 3 lines
Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc, is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 2/6 dt-bindings: mailbox: Add APCS global binding for SDM845 SoCs
In reply to sibisInclude SDM845 APCS binding to the list of possible bindings
Signed-off-by sibis <[email protected]>
--- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +2 -1
@@ -9,7 +9,8 @@ platforms. Value type: <string> Definition: must be one of: "qcom,msm8916-apcs-kpss-global", - "qcom,msm8996-apcs-hmss-global" + "qcom,msm8996-apcs-hmss-global", + "qcom,sdm845-apcs-hmss-global" - reg: Usage: required
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 3/6 mailbox: Add support for Qualcomm SDM845 SoCs
In reply to sibisAdd the corresponding APCS offset for SDM845 SoC
Signed-off-by sibis <[email protected]>
--- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 1 file changed, 1 insertion(+)
drivers/mailbox/qcom-apcs-ipc-mailbox.c +1 -0
@@ -125,6 +125,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible ="qcom,msm8916-apcs-kpss-global" , .data = (void *)8 }, { .compatible ="qcom,msm8996-apcs-hmss-global" , .data = (void *)16 }, + { .compatible ="qcom,sdm845-apcs-hmss-global" , .data = (void *)12 }, {} };MODULE_DEVICE_TABLE (of, qcom_apcs_ipc_of_match);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 4/6 dt-bindings: remoteproc: Add Q6v5 Modem PIL binding for SDM845
In reply to sibisAdd new compatible string for Qualcomm SDM845 SoCs
Signed-off-by sibis <[email protected]>
--- Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +3 -2
@@ -9,8 +9,9 @@ on the Qualcomm Hexagon core. Definition: must be one of: "qcom,q6v5-pil", "qcom,msm8916-mss-pil", - "qcom,msm8974-mss-pil" - "qcom,msm8996-mss-pil" + "qcom,msm8974-mss-pil", + "qcom,msm8996-mss-pil", + "qcom,sdm845-mss-pil" - reg: Usage: required
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 5/6 remoteproc: qcom: Add support for mss remoteproc on SDM845
In reply to sibisQuoted 1 line
From SDM845, the Q6SS reset sequence on software side has been
simplified with the introduction of boot FSM which assists in bringing the Q6 out of reset
Add GLINK subdevice to allow definition of GLINK edge as a child of modem-pil
Reset assert/deassert sequence vary across SoCs adding reset start/stop helper functions to handle SoC specific reset sequences
Signed-off-by sibis <[email protected]>
--- drivers/remoteproc/qcom_q6v5_pil.c | 134 +++++++++++++++++++++++++++++++++++-- 1 file changed, 129 insertions(+), 5 deletions(-)
drivers/remoteproc/qcom_q6v5_pil.c +129 -5
@@ -57,6 +57,8 @@#define RMB_PMI_META_DATA_REG 0x10#define RMB_PMI_CODE_START_REG 0x14#define RMB_PMI_CODE_LENGTH_REG 0x18 +#define RMB_MBA_MSS_STATUS 0x40 +#define RMB_MBA_ALT_RESET 0x44#define RMB_CMD_META_DATA_READY 0x1#define RMB_CMD_LOAD_READY 0x2
@@ -104,6 +106,13 @@#define QDSP6SS_XO_CBCR 0x0038#define QDSP6SS_ACC_OVERRIDE_VAL 0x20 +/* QDSP6v65 parameters */ +#define QDSP6SS_SLEEP 0x3C +#define QDSP6SS_BOOT_CORE_START 0x400 +#define QDSP6SS_BOOT_CMD 0x404 +#define SLEEP_CHECK_MAX_LOOPS 200 +#define BOOT_FSM_TIMEOUT 10000 +struct reg_info {struct regulator *reg;int uV;
@@ -126,6 +135,8 @@ struct rproc_hexagon_res {bool need_mem_protection; }; +struct q6v5_reset_ops ; +struct q6v5 {struct device *dev;struct rproc *rproc;
@@ -166,6 +177,8 @@ struct q6v5 {void *mpss_region;size_t mpss_size; +const struct q6v5_reset_ops *ops; +struct qcom_rproc_glink glink_subdev;struct qcom_rproc_subdev smd_subdev;struct qcom_rproc_ssr ssr_subdev;bool need_mem_protection;
@@ -174,10 +187,16 @@ struct q6v5 {int version; }; +struct q6v5_reset_ops { +int (*reset_start)(struct q6v5 *qproc); +int (*reset_stop)(struct q6v5 *qproc); +}; +enum {MSS_MSM8916 ,MSS_MSM8974 ,MSS_MSM8996 , +MSS_SDM845 , }; static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -332,6 +351,52 @@ static int q6v5_load(struct rproc *rproc, const struct firmware *fw)return 0 ; } +static void alt_reset_restart (struct q6v5 *qproc,u32 restart) +{ +writel (restart, qproc->rmb_base +RMB_MBA_ALT_RESET ); +} + +static int q6v5_msm_reset_stop (struct q6v5 *qproc) +{ +return reset_control_assert (qproc->mss_restart); +} + +static int q6v5_msm_reset_start (struct q6v5 *qproc) +{ +return reset_control_deassert (qproc->mss_restart); +} + +static int q6v5_sdm_reset_stop (struct q6v5 *qproc) +{ +return reset_control_reset (qproc->mss_restart); +} + +static int q6v5_sdm_reset_start (struct q6v5 *qproc) +{ +int ret; + +alt_reset_restart (qproc,1 ); +/* Ensure alt reset is written before restart reg */ +udelay (100 ); + + ret =reset_control_reset (qproc->mss_restart); + +udelay (100 ); +alt_reset_restart (qproc,0 ); + +return ret; +} + +static const struct q6v5_reset_ops q6v5_msm_ops = { + .reset_stop = q6v5_msm_reset_stop, + .reset_start = q6v5_msm_reset_start, +}; + +static const struct q6v5_reset_ops q6v5_sdm_ops = { + .reset_stop = q6v5_sdm_reset_stop, + .reset_start = q6v5_sdm_reset_start, +}; +static int q6v5_rmb_pbl_wait (struct q6v5 *qproc,int ms) {unsigned long timeout;
@@ -384,8 +449,37 @@ static int q6v5proc_reset(struct q6v5 *qproc)int ret;int i; +if (qproc->version ==MSS_SDM845 ) { -if (qproc->version ==MSS_MSM8996 ) { + val =readl (qproc->reg_base +QDSP6SS_SLEEP ); + val |=0x1 ; +writel (val, qproc->reg_base +QDSP6SS_SLEEP ); + + ret =readl_poll_timeout (qproc->reg_base +QDSP6SS_SLEEP , + val, !(val &BIT (31 )),1 , +SLEEP_CHECK_MAX_LOOPS ); +if (ret) { +dev_err (qproc->dev,"QDSP6SS Sleep clock timed out\n" ); +return -ETIMEDOUT ; + } + +/* De-assert QDSP6 stop core */ +writel (1 , qproc->reg_base +QDSP6SS_BOOT_CORE_START ); +/* Trigger boot FSM */ +writel (1 , qproc->reg_base +QDSP6SS_BOOT_CMD ); + + ret =readl_poll_timeout (qproc->rmb_base +RMB_MBA_MSS_STATUS , + val, (val &BIT (0 )) !=0 ,10 ,BOOT_FSM_TIMEOUT ); +if (ret) { +dev_err (qproc->dev,"Boot FSM failed to complete.\n" ); +/* Reset the modem so that boot FSM is in reset state */ + qproc->ops->reset_start (qproc); +return ret; + } + + goto pbl_wait; + + }else if (qproc->version ==MSS_MSM8996 ) {/* Override the ACC value if required */ writel (QDSP6SS_ACC_OVERRIDE_VAL , qproc->reg_base +QDSP6SS_STRAP_ACC );
@@ -493,6 +587,7 @@ static int q6v5proc_reset(struct q6v5 *qproc) val &= ~Q6SS_STOP_CORE ;writel (val, qproc->reg_base +QDSP6SS_RESET_REG ); +pbl_wait:/* Wait for PBL status */ ret =q6v5_rmb_pbl_wait (qproc,1000 );if (ret == -ETIMEDOUT ) {
@@ -746,7 +841,7 @@ static int q6v5_start(struct rproc *rproc)dev_err (qproc->dev,"failed to enable supplies\n" ); goto disable_proxy_clk; } - ret =reset_control_deassert (qproc->mss_restart); + ret = qproc->ops->reset_start (qproc);if (ret) {dev_err (qproc->dev,"failed to deassert mss restart\n" ); goto disable_vdd;
@@ -841,7 +936,7 @@ static int q6v5_start(struct rproc *rproc) qproc->active_clk_count); assert_reset: -reset_control_assert (qproc->mss_restart); + qproc->ops->reset_stop (qproc); disable_vdd:q6v5_regulator_disable (qproc, qproc->active_regs, qproc->active_reg_count);
@@ -891,7 +986,7 @@ static int q6v5_stop(struct rproc *rproc) qproc->mpss_phys, qproc->mpss_size);WARN_ON (ret); -reset_control_assert (qproc->mss_restart); + qproc->ops->reset_stop (qproc);q6v5_clk_disable (qproc->dev, qproc->active_clks, qproc->active_clk_count); q6v5_regulator_disable(qproc, qproc->active_regs,
@@ -1140,6 +1235,12 @@ static int q6v5_probe(struct platform_device *pdev) qproc->dev = &pdev->dev; qproc->rproc = rproc;platform_set_drvdata (pdev, qproc); + qproc->version = desc->version; + +if (qproc->version ==MSS_SDM845 ) + qproc->ops = &q6v5_sdm_ops; +else + qproc->ops = &q6v5_msm_ops;init_completion (&qproc->start_done);init_completion (&qproc->stop_done);
@@ -1188,7 +1289,6 @@ static int q6v5_probe(struct platform_device *pdev)if (ret) goto free_rproc; - qproc->version = desc->version; qproc->need_mem_protection = desc->need_mem_protection; ret =q6v5_request_irq (qproc, pdev,"wdog" , q6v5_wdog_interrupt);if (ret <0 )
@@ -1213,6 +1313,7 @@ static int q6v5_probe(struct platform_device *pdev) } qproc->mpss_perm =BIT (QCOM_SCM_VMID_HLOS ); qproc->mba_perm =BIT (QCOM_SCM_VMID_HLOS ); +qcom_add_glink_subdev (rproc, &qproc->glink_subdev);qcom_add_smd_subdev (rproc, &qproc->smd_subdev);qcom_add_ssr_subdev (rproc, &qproc->ssr_subdev,"mpss" );
@@ -1234,6 +1335,7 @@ static int q6v5_remove(struct platform_device *pdev)rproc_del (qproc->rproc); +qcom_remove_glink_subdev (qproc->rproc, &qproc->glink_subdev);qcom_remove_smd_subdev (qproc->rproc, &qproc->smd_subdev);qcom_remove_ssr_subdev (qproc->rproc, &qproc->ssr_subdev);rproc_free (qproc->rproc);
@@ -1241,6 +1343,27 @@ static int q6v5_remove(struct platform_device *pdev)return 0 ; } +static const struct rproc_hexagon_res sdm845_mss = { + .hexagon_mba_image ="mba.mbn" , + .proxy_clk_names = (char *[]){ +"xo" , +"axis2" , +"prng" , +NULL + }, + .active_clk_names = (char *[]){ +"iface" , +"bus" , +"mem" , +"gpll0_mss" , +"snoc_axi" , +"mnoc_axi" , +NULL + }, + .need_mem_protection = true, + .version =MSS_SDM845 , +}; +static const struct rproc_hexagon_res msm8996_mss = { .hexagon_mba_image ="mba.mbn" , .proxy_clk_names = (char *[]){
@@ -1334,6 +1457,7 @@ static int q6v5_remove(struct platform_device *pdev) { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, + { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss}, { }, };MODULE_DEVICE_TABLE (of, q6v5_of_match);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH 6/6 remoteproc: qcom: Reorder active clks enable and reset
In reply to sibisActive clks need to be enabled before Asserting/Deasserting the reset lines in SDM845
Signed-off-by sibis <[email protected]>
--- drivers/remoteproc/qcom_q6v5_pil.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
drivers/remoteproc/qcom_q6v5_pil.c +10 -9
@@ -841,17 +841,18 @@ static int q6v5_start(struct rproc *rproc)dev_err (qproc->dev,"failed to enable supplies\n" ); goto disable_proxy_clk; } - ret = qproc->ops->reset_start (qproc); -if (ret) { -dev_err (qproc->dev,"failed to deassert mss restart\n" ); - goto disable_vdd; - } ret =q6v5_clk_enable (qproc->dev, qproc->active_clks, qproc->active_clk_count);if (ret) {dev_err (qproc->dev,"failed to enable clocks\n" ); - goto assert_reset; + goto disable_vdd; + } + + ret = qproc->ops->reset_start (qproc); +if (ret) { +dev_err (qproc->dev,"failed to deassert mss restart\n" ); + goto disable_active_clks; }/* Assign MBA image access in DDR to q6 */
@@ -862,7 +863,7 @@ static int q6v5_start(struct rproc *rproc)dev_err (qproc->dev,"assigning Q6 access to mba memory failed: %d\n" , xfermemop_ret); - goto disable_active_clks; + goto assert_reset; }writel (qproc->mba_phys, qproc->rmb_base +RMB_MBA_IMAGE_REG );
@@ -931,12 +932,12 @@ static int q6v5_start(struct rproc *rproc) "Failed to reclaim mba buffer, system may become unstable\n"); } +assert_reset: + qproc->ops->reset_stop (qproc); disable_active_clks:q6v5_clk_disable (qproc->dev, qproc->active_clks, qproc->active_clk_count); -assert_reset: - qproc->ops->reset_stop (qproc); disable_vdd:q6v5_regulator_disable (qproc, qproc->active_regs, qproc->active_reg_count);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project