arm64: kaslr: Set TCR_EL1.NFD1 when CONFIG_RANDOMIZE_BASE=y
RFC PATCH 1/1 arm64: kaslr: Set TCR_EL1.NFD1 when CONFIG_RANDOMIZE_BASE=y
TCR_EL1.NFD1 was allocated by SVE and ensures that fault-surpressing SVE memory accesses (e.g. speculative accesses from a first-fault gather load) which translate via TTBR1_EL1 result in a translation fault if they miss in the TLB when executed from EL0. This mitigates some timing attacks against KASLR, where the kernel address space could otherwise be probed efficiently using the FFR in conjunction with suppressed faults on SVE loads.
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Sending as RFC because this doesn't make any difference if kpti is enabled, which is the default with KASLR. It helps if kpti=off is being passed and shouldn't have an impact on performance.
arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/mm/proc.S | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)
arch/arm64/include/asm/pgtable-hwdef.h +1 -0
@@ -291,6 +291,7 @@#define TCR_TBI0 (UL(1) << 37)#define TCR_HA (UL(1) << 39)#define TCR_HD (UL(1) << 40) +#define TCR_NFD1 (UL(1) << 54)/* * TTBR.
arch/arm64/mm/proc.S +8 -1
@@ -36,6 +36,12 @@ #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K #endif +#ifdef CONFIG_RANDOMIZE_BASE +#define TCR_KASLR_FLAGS TCR_NFD1 +#else +#define TCR_KASLR_FLAGS 0 +#endif + #define TCR_SMP_FLAGS TCR_SHARED /* PTWs cacheable, inner/outer WBWA */
@@ -432,7 +438,8 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 + TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ + TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /*
Signature · 1 line
2.1.4
RFC PATCH 1/1 arm64: kaslr: Set TCR_EL1.NFD1 when CONFIG_RANDOMIZE_BASE=y
Quoted 8 lines · Will Deacon
TCR_EL1.NFD1 was allocated by SVE and ensures that fault-surpressing SVE memory accesses (e.g. speculative accesses from a first-fault gather load) which translate via
TTBR1_EL1result in a translation fault if they miss in the TLB when executed from EL0. This mitigates some timing attacks against KASLR, where the kernel address space could otherwise be probed efficiently using the FFR in conjunction with suppressed faults on SVE loads.
Quoted 9 lines
Cc Ard Biesheuvel <[email protected]>Cc Dave Martin <[email protected]>Signed-off-by Will Deacon <[email protected]>---
Sending as RFC because this doesn't make any difference if kpti is enabled, which is the default with KASLR. It helps if kpti=off is being passed and shouldn't have an impact on performance.
This just makes it harder/slower to probe the kernel address space using SVE instructions, right?
Quoted 46 lines
arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/mm/proc.S | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)arch/arm64/include/asm/pgtable-hwdef.h +1
-0@@ -291,6 +291,7 @@#define TCR_TBI0 (UL(1) << 37)#define TCR_HA (UL(1) << 39)#define TCR_HD (UL(1) << 40) +#define TCR_NFD1 (UL(1) << 54)/* * TTBR. arch/arm64/mm/proc.S +8
-2@@ -36,6 +36,12 @@ #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K #endif +#ifdef CONFIG_RANDOMIZE_BASE +#define TCR_KASLR_FLAGS TCR_NFD1 +#else +#define TCR_KASLR_FLAGS 0 +#endif + #define TCR_SMP_FLAGS TCR_SHARED /* PTWs cacheable, inner/outer WBWA */@@ -432,7 +438,8 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 + TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ + TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /* --2.1.4
RFC PATCH 1/1 arm64: kaslr: Set TCR_EL1.NFD1 when CONFIG_RANDOMIZE_BASE=y
Quoted 14 lines · Ard Biesheuvel
Quoted 13 lines · Will Deacon
TCR_EL1.NFD1 was allocated by SVE and ensures that fault-surpressing SVE memory accesses (e.g. speculative accesses from a first-fault gather load) which translate via
TTBR1_EL1result in a translation fault if they miss in the TLB when executed from EL0. This mitigates some timing attacks against KASLR, where the kernel address space could otherwise be probed efficiently using the FFR in conjunction with suppressed faults on SVE loads.Cc Ard Biesheuvel <[email protected]>Cc Dave Martin <[email protected]>Signed-off-by Will Deacon <[email protected]>---
Quoted 7 lines
Quoted 4 lines
Sending as RFC because this doesn't make any difference if kpti is enabled, which is the default with KASLR. It helps if kpti=off is being passed and shouldn't have an impact on performance.
This just makes it harder/slower to probe the kernel address space using SVE instructions, right?
Yeah, basically, but given that kpti should make any walks via ttbr1 from EL0 timing invariant, it doesn't make a whole lot of difference in conjunction with that.
Will
RFC PATCH 1/1 arm64: kaslr: Set TCR_EL1.NFD1 when CONFIG_RANDOMIZE_BASE=y
Quoted 20 lines · Will Deacon
Quoted 19 lines · Ard Biesheuvel
Quoted 17 lines · Will Deacon
TCR_EL1.NFD1 was allocated by SVE and ensures that fault-surpressing SVE memory accesses (e.g. speculative accesses from a first-fault gather load) which translate via
TTBR1_EL1result in a translation fault if they miss in the TLB when executed from EL0. This mitigates some timing attacks against KASLR, where the kernel address space could otherwise be probed efficiently using the FFR in conjunction with suppressed faults on SVE loads.Cc Ard Biesheuvel <[email protected]>Cc Dave Martin <[email protected]>Signed-off-by Will Deacon <[email protected]>---
Sending as RFC because this doesn't make any difference if kpti is enabled, which is the default with KASLR. It helps if kpti=off is being passed and shouldn't have an impact on performance.
Quoted 7 lines
Quoted 2 lines
This just makes it harder/slower to probe the kernel address space using SVE instructions, right?
Yeah, basically, but given that kpti should make any walks via ttbr1 from EL0 timing invariant, it doesn't make a whole lot of difference in conjunction with that.
Seems sane in any case
RFC PATCH 1/1 arm64: kaslr: Set TCR_EL1.NFD1 when CONFIG_RANDOMIZE_BASE=y
In reply to Will DeaconQuoted 1 line · Will Deacon
TCR_EL1.NFD1 was allocated by SVE and ensures that fault-surpressing SVE
suppressing
Quoted 6 lines
memory accesses (e.g. speculative accesses from a first-fault gather load) which translate via
TTBR1_EL1result in a translation fault if they miss in the TLB when executed from EL0. This mitigates some timing attacks against KASLR, where the kernel address space could otherwise be probed efficiently using the FFR in conjunction with suppressed faults on SVE loads.
To be clear, I might say
result in a (suppressed) translation fault
(there is no new exception taken here; the effect is only to suppress the table walk on TLB miss in these cases).
Cheers
---Dave
Quoted 61 lines
Cc Ard Biesheuvel <[email protected]>Cc Dave Martin <[email protected]>Signed-off-by Will Deacon <[email protected]>---
Sending as RFC because this doesn't make any difference if kpti is enabled, which is the default with KASLR. It helps if kpti=off is being passed and shouldn't have an impact on performance.
arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/mm/proc.S | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)arch/arm64/include/asm/pgtable-hwdef.h +1
-0@@ -291,6 +291,7 @@#define TCR_TBI0 (UL(1) << 37)#define TCR_HA (UL(1) << 39)#define TCR_HD (UL(1) << 40) +#define TCR_NFD1 (UL(1) << 54)/* * TTBR. arch/arm64/mm/proc.S +8
-1@@ -36,6 +36,12 @@ #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K #endif +#ifdef CONFIG_RANDOMIZE_BASE +#define TCR_KASLR_FLAGS TCR_NFD1 +#else +#define TCR_KASLR_FLAGS 0 +#endif + #define TCR_SMP_FLAGS TCR_SHARED /* PTWs cacheable, inner/outer WBWA */@@ -432,7 +438,8 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 + TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ + TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /*Signature · 7 lines
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