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ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

PATCH In review Daniel Schultz 2 participants 7 messages Mar 5, 2018 – Mar 6, 2018

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Device tree bindings Arm Rockchip
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Daniel Schultz

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#0 lore raw

PATCH 1/1 ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by Daniel Schultz <[email protected]>

---

The binding will be added with the next merge of net-next:
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570

 arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)
arch/arm/boot/dts/rk3288-phycore-som.dtsi +1 -0
index bdd80aa..e60535d 100644
@@ -141,6 +141,7 @@
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			enet-phy-lane-no-swap;
+			ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
 		};
 	};
 };
Signature · 1 line
2.7.4
maintainer
#1 lore raw

Hi Daniel,

Am Montag, 5. M?rz 2018, 13:45:11 CET schrieb Daniel Schultz:

Quoted 8 lines

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by Daniel Schultz <[email protected]>

---

The binding will be added with the next merge of net-next:
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570

I did find the commit, but no related change of the dp83867 dt binding document [0], including a review by dt-maintainers.

While your property does not look overly complicated, the binding should be updated nontheless.

Heiko

[0] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570

Quoted 16 lines
 arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)
arch/arm/boot/dts/rk3288-phycore-som.dtsi +1 -0
index bdd80aa..e60535d 100644
@@ -141,6 +141,7 @@
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			enet-phy-lane-no-swap;
+			ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
 		};
 	};
 };
author
#2 lore raw

Hi,

Quoted 11 lines · Heiko Stuebner

Hi Daniel,

Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:

Quoted 8 lines

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by Daniel Schultz <[email protected]>

---

The binding will be added with the next merge of net-next:
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570

https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt

If I search in the master branch, I get the patch. Did I searched wrong?

Daniel

Quoted 28 lines

I did find the commit, but no related change of the dp83867 dt binding document [0], including a review by dt-maintainers.

While your property does not look overly complicated, the binding should be updated nontheless.

Heiko

[0] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Documentation/devicetree/bindings/net/ti,dp83867.txt?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570

Quoted 16 lines
  arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 +
  1 file changed, 1 insertion(+)
arch/arm/boot/dts/rk3288-phycore-som.dtsi +1 -0
index bdd80aa..e60535d 100644
@@ -141,6 +141,7 @@
  			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  			enet-phy-lane-no-swap;
+			ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
  		};
  	};
  };
Signature · 20 lines
Mit freundlichen Grüßen,
With best regards,
  Daniel Schultz

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maintainer
#3 lore raw

Hi Daniel,

Am Montag, 5. M?rz 2018, 16:57:13 CET schrieb Daniel Schultz:

Quoted 8 lines · Heiko Stuebner
Quoted 7 lines

Am Montag, 5. M?rz 2018, 13:45:11 CET schrieb Daniel Schultz:

Quoted 6 lines

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by Daniel Schultz <[email protected]>

---

Quoted 7 lines
Quoted 3 lines
Quoted 3 lines

The binding will be added with the next merge of net-next:
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit
/?id=9708fb630d19ee51ae3aeb3a533e3010da0e8570

https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Docum
entation/devicetree/bindings/net/ti,dp83867.txt

If I search in the master branch, I get the patch. Did I searched wrong?

no ... seems I was just blind :-)

Heiko

Quoted 34 lines
Quoted 34 lines

I did find the commit, but no related change of the dp83867 dt binding document [0], including a review by dt-maintainers.

While your property does not look overly complicated, the binding should be updated nontheless.

Heiko

[0]
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/log/Do
cumentation/devicetree/bindings/net/ti,dp83867.txt?id=9708fb630d19ee51ae3a eb3a533e3010da0e8570>

Quoted 21 lines
  arch/arm/boot/dts/rk3288-phycore-som.dtsi | 1 +
  1 file changed, 1 insertion(+)
(quoted diff) +0 -0

b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index bdd80aa..e60535d 100644

arch/arm/boot/dts/rk3288-phycore-som.dtsi +1 -0
@@ -141,6 +141,7 @@
 
  			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  			enet-phy-lane-no-swap;
 
+			ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
 

  		};
  	
  	};
  
  };
maintainer
#5 lore raw

Am Montag, 5. M?rz 2018, 21:25:30 CET schrieb Heiko St?bner:

Quoted 7 lines

Am Montag, 5. M?rz 2018, 13:45:11 CET schrieb Daniel Schultz:

Quoted 4 lines

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by Daniel Schultz <[email protected]>

applied for 4.17

had to move it to 4.18 though.

The change to the dt-binding header goes through the networking tree and will only get merged for 4.17-rc1 .

So devicetree changes in a different branch aren't available at this point.

One commonly practiced alternative is that you provide a v2 with the actual hex values instead of the constants for 4.17 and a follow-up patch replacing them with the constants that I can apply for 4.18.

Heiko

author
#6 lore raw

Hi,

Quoted 12 lines · Heiko Stübner

Am Montag, 5. März 2018, 21:25:30 CET schrieb Heiko Stübner:

Quoted 6 lines

Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:

Quoted 4 lines

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by Daniel Schultz <[email protected]>

applied for 4.17

had to move it to 4.18 though.

The change to the dt-binding header goes through the networking tree and will only get merged for 4.17-rc1 .

Quoted 7 lines

So devicetree changes in a different branch aren't available at this point.

One commonly practiced alternative is that you provide a v2 with the actual hex values instead of the constants for 4.17 and a follow-up patch replacing them with the constants that I can apply for 4.18.

It's not so urgent because the RK818 PMIC currently does not boot and the patch for this problem is also pending.

Signature · 3 lines
Mit freundlichen Grüßen,
With best regards,
  Daniel Schultz