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arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

PATCH New chin.liang.see at intel.com 4 participants 4 messages Feb 28, 2018 – Mar 8, 2018

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Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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chin.liang.see at intel.com

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#0 lore raw

PATCH 1/1 arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

From: Chin Liang See <[email protected]>

Enabling cache and TLB maintenance broadcast through ACTLR as required by Linux.

Signed-off-by Chin Liang See <[email protected]>
---
 arch/arm/mach-socfpga/misc_gen5.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/misc_gen5.c +10 -1
index a7dcacc..7c7a708 100644
@@ -239,7 +239,7 @@ static u32 iswgrp_handoff[8];
 
 int arch_early_init_r(void)
 {
-	int i;
+	int i, val;
 
 	/*
 	 * Write magic value into magic register to unlock support for

@@ -285,6 +285,15 @@ int arch_early_init_r(void)
 	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 #endif
 
+	/* Enable cache and TLB maintainance broadcast as required by Linux */
+	/* Read auxiliary control register */
+	asm volatile ("mrc     p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+	val |= (1 << 0);
+	/* Write auxiliary control register */
+	asm volatile ("mcr     p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+	CP15DSB;
+	CP15ISB;
+
 	return 0;
 }
Signature · 1 line
2.2.2
#1 lore raw

PATCH 1/1 arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

Quoted 4 lines · chin.liang.see at intel.com

From: Chin Liang See <[email protected]>

Enabling cache and TLB maintenance broadcast through ACTLR as required by Linux.

This needs far more clarification. What is the problem you're fixing here ? How does it fix the problem ?

Quoted 35 lines
Signed-off-by Chin Liang See <[email protected]>
---
 arch/arm/mach-socfpga/misc_gen5.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/misc_gen5.c +10 -1
index a7dcacc..7c7a708 100644
@@ -239,7 +239,7 @@ static u32 iswgrp_handoff[8];
 
 int arch_early_init_r(void)
 {
-	int i;
+	int i, val;
 
 	/*
 	 * Write magic value into magic register to unlock support for

@@ -285,6 +285,15 @@ int arch_early_init_r(void)
 	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 #endif
 
+	/* Enable cache and TLB maintainance broadcast as required by Linux */
+	/* Read auxiliary control register */
+	asm volatile ("mrc     p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+	val |= (1 << 0);
+	/* Write auxiliary control register */
+	asm volatile ("mcr     p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+	CP15DSB;
+	CP15ISB;
+
 	return 0;
 }
Signature · 2 lines
Best regards,
Marek Vasut
#2 lore raw

PATCH 1/1 arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

Quoted 9 lines · Marek Vasut
Quoted 6 lines · chin.liang.see at intel.com

From: Chin Liang See <[email protected]>

Enabling cache and TLB maintenance broadcast through ACTLR as required
by Linux.

This needs far more clarification. What is the problem you're fixing here ? How does it fix the problem ?

Sure. When the 2 processors is enabled with SMP, popen operation would fail as content are different after the copy. This issue goes away when we force Linux to run with 1 core only. Checked with ARM, this bit is required by Linux when running SMP.

Chin Liang

Quoted 43 lines
Quoted 42 lines
Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/misc_gen5.c | 11 ++++++++++-

 1 file changed, 10 insertions(+), 1 deletion(-)
arch/arm/mach- renamed from arch/arm/mach-socfpga/misc_gen5.c +0 -0

socfpga/misc_gen5.c
index a7dcacc..7c7a708 100644

arch/arm/mach-socfpga/misc_gen5.c +0 -0
@@ -239,7 +239,7 @@ static u32 iswgrp_handoff[8];


 int arch_early_init_r(void)
 {

arch/arm/mach-socfpga/misc_gen5.c +1 -1
-	int i;
+	int i, val;


  /*
   * Write magic value into magic register to unlock support for

arch/arm/mach-socfpga/misc_gen5.c +0 -0
@@ -285,6 +285,15 @@ int arch_early_init_r(void)
  	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  #endif

arch/arm/mach-socfpga/misc_gen5.c +1 -0
+	/* Enable cache and TLB maintainance broadcast as required

by Linux */

arch/arm/mach-socfpga/misc_gen5.c +2 -0
+	/* Read auxiliary control register */
+	asm volatile ("mrc     p15, 0, %0, c1, c0, 1\n\t" :

"=r"(val));

arch/arm/mach-socfpga/misc_gen5.c +3 -0
+	val |= (1 << 0);
+	/* Write auxiliary control register */
+	asm volatile ("mcr     p15, 0, %0, c1, c0, 1\n\t" : :

"r"(val));

arch/arm/mach-socfpga/misc_gen5.c +3 -0
+	CP15DSB;
+	CP15ISB;
+

  return 0;
 }

maintainer
#3 lore raw

PATCH 1/1 arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast

Quoted 8 lines · Chin Liang
Quoted 7 lines · Marek Vasut
Quoted 6 lines · chin.liang.see at intel.com

From: Chin Liang See <[email protected]>

Enabling cache and TLB maintenance broadcast through ACTLR as required
by Linux.

Quoted 8 lines
Quoted 2 lines

This needs far more clarification. What is the problem you're fixing here ? How does it fix the problem ?

Sure. When the 2 processors is enabled with SMP, popen operation would fail as content are different after the copy. This issue goes away when we force Linux to run with 1 core only. Checked with ARM, this bit is required by Linux when running SMP.

What's a "popen" operation? Shouldn't you also set the SMP along with the FW bit?

Dinh