Skip to contentSkip to conversation

Add Ingenic X1000 SoC Support

RFC In review PrasannaKumar Muralidharan 5 participants 19 messages Sep 27, 2017 – Mar 10, 2018

Subsystems (4)
Device tree bindings MIPS Common clk Ingenic JZ47xx SoCs
lore
Share & tools
lore

PrasannaKumar Muralidharan

author
#0 lore raw

cover Add Ingenic X1000 SoC Support

Add support for Ingenic X1000 SoC. This patch set provides enough bits to boot a kernel to an initramfs user space.

I implemented this code during 2016. Boot stuck at "calibrating delay loop ...". Now I have fixed the issue by setting the correct irq. I do not have access to this device anymore so could not test the fix. Marking this patch series as RFC as this needs to be tested.

Test and feedback appreciated.

This series enables uart, timer and interrupt controller. As this is very minimal a static elf binary should be used as init and should be available in initramfs.

PrasannaKumar Muralidharan (4):
dt-bindings: Add Ingenic X1000 SoC clock define
clk: Add Ingenic X1000 CGU driver
MIPS: Ingenic: Initial X1000 SoC support
MIPS: Ingenic: Add Halley2 development board support

 arch/mips/boot/dts/ingenic/Makefile    |   1 +
 arch/mips/boot/dts/ingenic/halley2.dts |  46 ++++++++
 arch/mips/boot/dts/ingenic/x1000.dtsi  |  93 +++++++++++++++
 arch/mips/configs/halley2_defconfig    |  61 ++++++++++
 arch/mips/jz4740/Kconfig               |  10 ++
 arch/mips/jz4740/time.c                |   2 +-
 drivers/clk/ingenic/Makefile           |   1 +
 drivers/clk/ingenic/x1000-cgu.c        | 203 +++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/x1000-cgu.h  |  46 ++++++++
 9 files changed, 462 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/dts/ingenic/halley2.dts
 create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
 create mode 100644 arch/mips/configs/halley2_defconfig
 create mode 100644 drivers/clk/ingenic/x1000-cgu.c
 create mode 100644 include/dt-bindings/clock/x1000-cgu.h
Signature · 1 line
2.10.0
author
#1 lore raw

RFC 1/4 dt-bindings: Add Ingenic X1000 SoC clock define

Ingenic X1000 SoC has different set of peripherals than JZ4780 and JZ4740. Add a new device tree binding for the clock.

Signed-off-by PrasannaKumar Muralidharan <[email protected]>
---
 include/dt-bindings/clock/x1000-cgu.h | 46 +++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/x1000-cgu.h
include/dt-bindings/clock/x1000-cgu.h new file +46 -0
new file mode 100644
index 0000000..17f05bc
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
+
+/* Add details for other peripherals when their support is added */
+#define X1000_CLK_EXCLK		0
+#define X1000_CLK_RTCLK		(X1000_CLK_EXCLK + 1)
+#define X1000_CLK_APLL		(X1000_CLK_RTCLK + 1)
+#define X1000_CLK_MPLL		(X1000_CLK_APLL + 1)
+
+#define X1000_CLK_SCLKA		(X1000_CLK_MPLL + 1)
+#define X1000_CLK_CPUMUX	(X1000_CLK_SCLKA + 1)
+#define X1000_CLK_CPU		(X1000_CLK_CPUMUX + 1)
+#define X1000_CLK_L2CACHE	(X1000_CLK_CPU + 1)
+#define X1000_CLK_AHB0		(X1000_CLK_L2CACHE + 1)
+#define X1000_CLK_AHB2PMUX	(X1000_CLK_AHB0 + 1)
+#define X1000_CLK_AHB2		(X1000_CLK_AHB2PMUX + 1)
+#define X1000_CLK_PCLK		(X1000_CLK_AHB2 + 1)
+#define X1000_CLK_DDR		(X1000_CLK_PCLK + 1)
+#define X1000_CLK_MSCMUX	(X1000_CLK_DDR + 1)
+#define X1000_CLK_MSC0		(X1000_CLK_MSCMUX + 1)
+#define X1000_CLK_MSC1		(X1000_CLK_MSC0 + 1)
+#define X1000_CLK_CIMMCLK	(X1000_CLK_MSC1 + 1)
+#define X1000_CLK_PCMPLL	(X1000_CLK_CIMMCLK + 1)
+#define X1000_CLK_PCM		(X1000_CLK_PCMPLL + 1)
+#define X1000_CLK_NEMC		(X1000_CLK_PCM + 1)
+#define X1000_CLK_UART0		(X1000_CLK_NEMC + 1)
+#define X1000_CLK_UART1		(X1000_CLK_UART0 + 1)
+#define X1000_CLK_UART2		(X1000_CLK_UART1 + 1)
+#define X1000_CLK_PDMA		(X1000_CLK_UART2 + 1)
+#define X1000_CLK_CIM		(X1000_CLK_PDMA + 1)
+#define X1000_CLK_DDR0		(X1000_CLK_CIM + 1)
+#define X1000_CLK_DDR1		(X1000_CLK_DDR0 + 1)
+#define X1000_CLK_CORE1		(X1000_CLK_DDR1	+ 1)
+
+#define X1000_CLK_I2SPLL	(X1000_CLK_CORE1 + 1)
+#define X1000_CLK_I2S		(X1000_CLK_I2SPLL + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
Signature · 1 line
2.10.0
author
#2 lore raw

RFC 2/4 clk: Add Ingenic X1000 CGU driver

In reply to PrasannaKumar Muralidharan

Add support for the clocks provided by CGU in Ingenic X1000 SoC.

Signed-off-by PrasannaKumar Muralidharan <[email protected]>
---
 drivers/clk/ingenic/Makefile    |   1 +
 drivers/clk/ingenic/x1000-cgu.c | 203 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 204 insertions(+)
 create mode 100644 drivers/clk/ingenic/x1000-cgu.c
drivers/clk/ingenic/Makefile +1 -0
index cd47b06..89c665b 100644
@@ -1,3 +1,4 @@
 obj-y				+= cgu.o
 obj-$(CONFIG_MACH_JZ4740)	+= jz4740-cgu.o
 obj-$(CONFIG_MACH_JZ4780)	+= jz4780-cgu.o
+obj-$(CONFIG_MACH_X1000)	+= x1000-cgu.o
drivers/clk/ingenic/x1000-cgu.c new file +203 -0

203 lines not on this page · raw message

Signature · 1 line
2.10.0
author
#4 lore raw

RFC 3/4 MIPS: Ingenic: Initial X1000 SoC support

In reply to PrasannaKumar Muralidharan

Add initial Ingenic X1000 SoC support. Provide minimum necessary information to boot kernel to an initramfs userspace.

Signed-off-by PrasannaKumar Muralidharan <[email protected]>
---
 arch/mips/boot/dts/ingenic/x1000.dtsi | 93 +++++++++++++++++++++++++++++++++++
 arch/mips/jz4740/Kconfig              |  6 +++
 arch/mips/jz4740/time.c               |  2 +-
 3 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
arch/mips/boot/dts/ingenic/x1000.dtsi new file +93 -0
new file mode 100644
index 0000000..abbb9ec
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/x1000-cgu.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "ingenic,x1000";
+
+	cpuintc: interrupt-controller {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
+	intc: interrupt-controller@10001000 {
+		compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
+		reg = <0x10001000 0x50>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+	};
+
+	ext: ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	rtc: rtc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	cgu: jz4780-cgu@10000000 {
+		compatible = "ingenic,x1000-cgu";
+		reg = <0x10000000 0x100>;
+
+		clocks = <&ext>, <&rtc>;
+		clock-names = "ext", "rtc";
+
+		#clock-cells = <1>;
+	};
+
+	uart0: serial@10030000 {
+		compatible = "ingenic,x1000-uart", "ingenic,jz4780-uart";
+		reg = <0x10030000 0x100>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <51>;
+
+		clocks = <&ext>, <&cgu X1000_CLK_UART0>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart1: serial@10031000 {
+		compatible = "ingenic,x1000-uart", "ingenic,jz4780-uart";
+		reg = <0x10031000 0x100>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <50>;
+
+		clocks = <&ext>, <&cgu X1000_CLK_UART1>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart2: serial@10032000 {
+		compatible = "ingenic,x1000-uart", "ingenic,jz4780-uart";
+		reg = <0x10032000 0x100>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <49>;
+
+		clocks = <&ext>, <&cgu X1000_CLK_UART2>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+};
arch/mips/jz4740/Kconfig +6 -0
index 36f8201..338bc3f 100644
@@ -22,3 +22,9 @@ config MACH_JZ4780
 	select MIPS_CPU_SCACHE
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_HIGHMEM
+
+config MACH_X1000
+	bool
+	select MIPS_CPU_SCACHE
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_HAS_EARLY_PRINTK
arch/mips/jz4740/time.c +1 -1
index bb1ad51..e28c734 100644
@@ -113,7 +113,7 @@ static struct clock_event_device jz4740_clockevent = {
 #ifdef CONFIG_MACH_JZ4740
 	.irq = JZ4740_IRQ_TCU0,
 #endif
-#ifdef CONFIG_MACH_JZ4780
+#if defined CONFIG_MACH_JZ4780 || defined CONFIG_MACH_X1000
 	.irq = JZ4780_IRQ_TCU2,
 #endif
 };
Signature · 1 line
2.10.0
#5 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 10 lines · PrasannaKumar Muralidharan

Add initial Ingenic X1000 SoC support. Provide minimum necessary information to boot kernel to an initramfs userspace.

Signed-off-by PrasannaKumar Muralidharan <[email protected]>
---
 arch/mips/boot/dts/ingenic/x1000.dtsi | 93 +++++++++++++++++++++++++++++++++++
 arch/mips/jz4740/Kconfig              |  6 +++
 arch/mips/jz4740/time.c               |  2 +-
 3 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi

arch/mips/jz4780/setup.c, specifically get_board_mach_type() and get_system_type() will need updating too.

Does X1000 use a different PRID, or is it basically just a JZ4780 core with different SoC peripherals?

arch/mips/boot/dts/ingenic/x1000.dtsi line 6

Quoted 12 lines
arch/mips/boot/dts/ingenic/x1000.dtsi new file +6 -0
new file mode 100644
index 0000000..abbb9ec
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.

(these will need updating to use SPDX identifiers if you respin)

arch/mips/boot/dts/ingenic/x1000.dtsi line 45

Quoted 1 line
arch/mips/boot/dts/ingenic/x1000.dtsi new file +1 -0
+	cgu: jz4780-cgu@10000000 {

not sure jz4780 is appropriate here.

arch/mips/boot/dts/ingenic/x1000.dtsi line 53

Quoted 8 lines
arch/mips/boot/dts/ingenic/x1000.dtsi new file +8 -0
+		compatible = "ingenic,x1000-cgu";
+		reg = <0x10000000 0x100>;
+
+		clocks = <&ext>, <&rtc>;
+		clock-names = "ext", "rtc";
+
+		#clock-cells = <1>;
+	};

Cheers
James

author
#6 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Hi James,

Thanks for reviewing this.

Quoted 12 lines · James Hogan
Quoted 10 lines · PrasannaKumar Muralidharan

Add initial Ingenic X1000 SoC support. Provide minimum necessary information to boot kernel to an initramfs userspace.

Signed-off-by PrasannaKumar Muralidharan <[email protected]>
---
 arch/mips/boot/dts/ingenic/x1000.dtsi | 93 +++++++++++++++++++++++++++++++++++
 arch/mips/jz4740/Kconfig              |  6 +++
 arch/mips/jz4740/time.c               |  2 +-
 3 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
Quoted 2 lines

arch/mips/jz4780/setup.c, specifically get_board_mach_type() and get_system_type() will need updating too.

Missed it. Will make necessary changes.

Quoted 2 lines

Does X1000 use a different PRID, or is it basically just a JZ4780 core with different SoC peripherals?

Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has single CPU core so it is definitely not JZ4780.

Quoted 6 lines
Quoted 6 lines
arch/mips/boot/dts/ingenic/x1000.dtsi new file +0 -0
new file mode 100644
index 0000000..abbb9ec
@@ -0,0 +1,93 @@
Quoted 8 lines

arch/mips/boot/dts/ingenic/x1000.dtsi line 6

Quoted 6 lines
arch/mips/boot/dts/ingenic/x1000.dtsi new file +6 -0
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.

(these will need updating to use SPDX identifiers if you respin)

Sure. Will take care while submitting next version.

Quoted 3 lines

arch/mips/boot/dts/ingenic/x1000.dtsi line 45

Quoted 1 line
arch/mips/boot/dts/ingenic/x1000.dtsi new file +1 -0
+     cgu: jz4780-cgu@10000000 {

not sure jz4780 is appropriate here.

No, it is not. Copy pasted from jz4780.dtsi but missed updating this.

Quoted 11 lines

arch/mips/boot/dts/ingenic/x1000.dtsi line 53

Quoted 8 lines
arch/mips/boot/dts/ingenic/x1000.dtsi new file +8 -0
+             compatible = "ingenic,x1000-cgu";
+             reg = <0x10000000 0x100>;
+
+             clocks = <&ext>, <&rtc>;
+             clock-names = "ext", "rtc";
+
+             #clock-cells = <1>;
+     };

Cheers
James

I used to get my code tested from Domink but I could not reach him for quite some time. Before buying the development board myself I would like to see if anyone can help me in testing. Do you have any contact with Ingenic who can help in testing this?

Thanks,
PrasannaKumar

#7 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 7 lines · 在 2018-03-07三的 19:14 +0530，PrasannaKumar Muralidharan写道：

I used to get my code tested from Domink but I could not reach him for
quite some time. Before buying the development board myself I would like to see if anyone can help me in testing. Do you have any contact with Ingenic who can help in testing this?

Hi PrasannaKumar

I'm resently working on Ingenic chips too. Ingentic guys have sent me a X1000 development broad and it will arrive in about two weeks. I have a ejtag debugger also (but not very suit with X1000 because X1000 have different ejtag interface with standard MIPS cores, maybe we need some modification on openocd). So maybe I can help in testing this after I get my broad. Just ask if you need any help.
Thanks

Signature · 1 line
Jiaxun Yang <[email protected]>
author
#8 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Hi Jiaxun,

Quoted 1 line · Jiaxun Yang

=E5=9C=A8 2018-03-07=E4=B8=89=E7=9A=84 19:14 +0530=EF=BC=8CPrasannaKumar =

Muralidharan=E5=86=99=E9=81=93=EF=BC=9A

Quoted 10 lines
Quoted 7 lines

I used to get my code tested from Domink but I could not reach him for
quite some time. Before buying the development board myself I would like to see if anyone can help me in testing. Do you have any contact with Ingenic who can help in testing this?

Hi PrasannaKumar

Quoted 9 lines

I'm resently working on Ingenic chips too. Ingentic guys have sent me a X1000 development broad and it will arrive in about two weeks. I have a ejtag debugger also (but not very suit with X1000 because X1000 have different ejtag interface with standard MIPS cores, maybe we need some modification on openocd). So maybe I can help in testing this after I get my broad. Just ask if you need any help.
Thanks
--
Jiaxun Yang <[email protected]>

Really nice to hear. I will ask for help once I make changes.

Thanks,
PrasannaKumar

#9 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

In reply to PrasannaKumar Muralidharan
Quoted 4 lines · PrasannaKumar Muralidharan
Quoted 2 lines

Does X1000 use a different PRID, or is it basically just a JZ4780 core with different SoC peripherals?

Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has

Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC | 0x4f, which cpu-probe.c already handles (apparently the D1 company code is used for JZ4770 & JZ4775 too).

Quoted 4 lines

I used to get my code tested from Domink but I could not reach him for quite some time. Before buying the development board myself I would like to see if anyone can help me in testing. Do you have any contact with Ingenic who can help in testing this?

Not personally, but I'll ask around. Of course if nobody much cares about it in practice and nobody has the hardware, there may be little value in supporting it upstream.

Cheers
James

author
#10 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Hi James,

Quoted 9 lines · James Hogan
Quoted 4 lines · PrasannaKumar Muralidharan
Quoted 2 lines

Does X1000 use a different PRID, or is it basically just a JZ4780 core with different SoC peripherals?

Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has

Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC | 0x4f, which cpu-probe.c already handles (apparently the D1 company code is used for JZ4770 & JZ4775 too).

Okay. Does this mean I need not modify get_board_mach_type() and get_system_type()?

Quoted 8 lines
Quoted 4 lines

I used to get my code tested from Domink but I could not reach him for quite some time. Before buying the development board myself I would like to see if anyone can help me in testing. Do you have any contact with Ingenic who can help in testing this?

Not personally, but I'll ask around. Of course if nobody much cares about it in practice and nobody has the hardware, there may be little value in supporting it upstream.

Seems Jiaxun is interested in the board and is willing to help.

I have been told that Ingenic is focusing on IoT market and X1000 is intended for IoT segment. I think that they would be selling several 100Ks of chip over the coming years. But I feel Ingenic spends time only on maintaining their Linux port which is usually based on very old kernel version.

Quoted 2 lines

Cheers
James

Thanks and regards,
PrasannaKumar

#11 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 5 lines · PrasannaKumar Muralidharan
Quoted 4 lines · James Hogan
Quoted 3 lines · PrasannaKumar Muralidharan
Quoted 2 lines

Does X1000 use a different PRID, or is it basically just a JZ4780 core with different SoC peripherals?

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has

Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC | 0x4f, which cpu-probe.c already handles (apparently the D1 company code is used for JZ4770 & JZ4775 too).

Okay. Does this mean I need not modify get_board_mach_type() and get_system_type()?

You still need to modify them, otherwise it won't understand "ingenic,x1000" compatible string, and will call it a JZ4740 in /proc/cpuinfo.

Quoted 10 lines
Quoted 8 lines
Quoted 4 lines

I used to get my code tested from Domink but I could not reach him for quite some time. Before buying the development board myself I would like to see if anyone can help me in testing. Do you have any contact with Ingenic who can help in testing this?

Not personally, but I'll ask around. Of course if nobody much cares about it in practice and nobody has the hardware, there may be little value in supporting it upstream.

Seems Jiaxun is interested in the board and is willing to help.

Okay, cool.

Cheers
James

author
#12 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 12 lines · James Hogan
Quoted 11 lines · PrasannaKumar Muralidharan
Quoted 9 lines · James Hogan
Quoted 4 lines · PrasannaKumar Muralidharan
Quoted 2 lines

Does X1000 use a different PRID, or is it basically just a JZ4780 core with different SoC peripherals?

Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has

Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC | 0x4f, which cpu-probe.c already handles (apparently the D1 company code is used for JZ4770 & JZ4775 too).

Quoted 6 lines
Quoted 2 lines

Okay. Does this mean I need not modify get_board_mach_type() and get_system_type()?

You still need to modify them, otherwise it won't understand "ingenic,x1000" compatible string, and will call it a JZ4740 in /proc/cpuinfo.

Oh okay. Will make the changes.

Quoted 15 lines
Quoted 10 lines
Quoted 8 lines
Quoted 4 lines

I used to get my code tested from Domink but I could not reach him for quite some time. Before buying the development board myself I would like to see if anyone can help me in testing. Do you have any contact with Ingenic who can help in testing this?

Not personally, but I'll ask around. Of course if nobody much cares about it in practice and nobody has the hardware, there may be little value in supporting it upstream.

Seems Jiaxun is interested in the board and is willing to help.

Okay, cool.

Cheers
James

#13 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

In reply to PrasannaKumar Muralidharan
Quoted 9 lines · 在 2018-03-07三的 20:35 +0530，PrasannaKumar Muralidharan写道：

Hi James,

Seems Jiaxun is interested in the board and is willing to help.

I have been told that Ingenic is focusing on IoT market and X1000 is intended for IoT segment. I think that they would be selling several 100Ks of chip over the coming years. But I feel Ingenic spends time only on maintaining their Linux port which is usually based on very old kernel version.

Ingenic is going to release their XBrust2 core with it's products such as X2000 a few days later. Witch is a pure MIPS64r5 with MXU2(A superset of MIPS's MSA SIMD instruction set). The newest kernel port of X1000 maintain by Ingenic is based on Linux-4.4 [1]. After communicated with Ingenic, they said they are forcusing on China domestic market. But they're looking for partners to enter foriegn market.

[1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this Chinese website, ingenic have a gerrit but I don't have access to it. As my experience, it's hard to develop on Chinese-made chips wihout reading Chinese documents.)

Quoted 2 lines
Quoted 2 lines
author
#14 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 1 line · Jiaxun Yang

=E5=9C=A8 2018-03-07=E4=B8=89=E7=9A=84 20:35 +0530=EF=BC=8CPrasannaKumar =

Muralidharan=E5=86=99=E9=81=93=EF=BC=9A

Quoted 17 lines
Quoted 9 lines

Hi James,

Seems Jiaxun is interested in the board and is willing to help.

I have been told that Ingenic is focusing on IoT market and X1000 is intended for IoT segment. I think that they would be selling several 100Ks of chip over the coming years. But I feel Ingenic spends time only on maintaining their Linux port which is usually based on very old kernel version.

Ingenic is going to release their XBrust2 core with it's products such as X2000 a few days later. Witch is a pure MIPS64r5 with MXU2(A superset of MIPS's MSA SIMD instruction set). The newest kernel port of X1000 maintain by Ingenic is based on Linux-4.4 [1]. After communicated with Ingenic, they said they are forcusing on China domestic market. But they're looking for partners to enter foriegn market.

Quoted 4 lines

[1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this Chinese website, ingenic have a gerrit but I don't have access to it. As my experience, it's hard to develop on Chinese-made chips wihout reading Chinese documents.)

Can you take a diff and upload it somewhere else? Download speed is a couple of bytes per second. Can you put the diff in github or similar other service?
I would like to see if the port uses DT.

#15 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 2 lines · PrasannaKumar Muralidharan
Quoted 1 line · Jiaxun Yang

=E5=9C=A8 2018-03-07=E4=B8=89=E7=9A=84 20:35 +0530=EF=BC=8CPrasannaKumar=

Muralidharan=E5=86=99=E9=81=93=EF=BC=9A

Quoted 22 lines
Quoted 17 lines
Quoted 9 lines

Hi James,

Seems Jiaxun is interested in the board and is willing to help.

I have been told that Ingenic is focusing on IoT market and X1000 is intended for IoT segment. I think that they would be selling several 100Ks of chip over the coming years. But I feel Ingenic spends time only on maintaining their Linux port which is usually based on very old kernel version.

Ingenic is going to release their XBrust2 core with it's products such as X2000 a few days later. Witch is a pure MIPS64r5 with MXU2(A superset of MIPS's MSA SIMD instruction set). The newest kernel port of X1000 maintain by Ingenic is based on Linux-4.4 [1]. After communicated with Ingenic, they said they are forcusing on China domestic market. But they're looking for partners to enter foriegn market.

Quoted 4 lines

[1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this Chinese website, ingenic have a gerrit but I don't have access to it. As my experience, it's hard to develop on Chinese-made chips wihout reading Chinese documents.)

Quoted 4 lines

Can you take a diff and upload it somewhere else? Download speed is a couple of bytes per second. Can you put the diff in github or similar other service?
I would like to see if the port uses DT.

Technically this was documented here:

ftp://ftp.ingenic.cn/DevSupport/Linux/Linux-3.0.8/JZ4780/JZ4780_linux_devel= opment_guide_EN.pdf

Go to =C2=A72.1 Download Source Code:

1) Download repo a) $ mkdir b) $ cd c) $ wget
http://git.ingenic.cn:8082/bj/repo d) $ chmod +x repo

However everything seems to be gone (including the gerrit page).

2ctc

#16 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 8 lines · 在 2018-03-07三的 19:13 +0100，Mathieu Malaterre写道：
Quoted 8 lines
Quoted 7 lines

[1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this
Chinese website, ingenic have a gerrit but I don't have access to it.
As my experience, it's hard to develop on Chinese-made chips wihout
reading Chinese documents.)

Quoted 8 lines
Quoted 6 lines

Can you take a diff and upload it somewhere else? Download speed is a
couple of bytes per second. Can you put the diff in github or similar
other service?
I would like to see if the port uses DT.

Technically this was documented here:

Well that's only Technically for the English world. Most Ingeinc costumers are Chinese so they're providing detailed support for Chinese world.
According Ingenic's announcement, the ftp have been deprecated for a long time and it's only exsiting for archive reason.

Quoted 9 lines

ftp://ftp.ingenic.cn/DevSupport/Linux/Linux-3.0.8/JZ4780/JZ4780_linux _development_guide_EN.pdf

Go to §2.1 Download Source Code:

1) Download repo a) $ mkdir b) $ cd c) $ wget
http://git.ingenic.cn:8082/bj/repo d) $ chmod +x repo

Repo is a sourcecode managing system used by Android. The gerrit is still here but need extra premission to reach. Now ingenic release there soucecode by "Baidu Netdisk". It's hard to access by foreign users. So we put the shourcecode here: https://github.com/Ingenic-commu
nity/linux-xburst-bsp

Thanks

Signature · 1 line
Jiaxun Yang <[email protected]>
#17 lore raw

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

In reply to PrasannaKumar Muralidharan

Sorry for the delay.We've uploaded the bsp 4.4 kernel here.

https://github.com/Ingenic-community/linux-xburst-bsp
Thanks.
Best RegardsJiaxun Yang

由： PrasannaKumar Muralidharan <[email protected]> 日期: 2018/3/8 00:25 (GMT+08:00)主题： Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

Quoted 18 lines · Jiaxun Yang
Quoted 9 lines · 在 2018-03-07三的 20:35 +0530，PrasannaKumar Muralidharan写道：

Hi James,

Seems Jiaxun is interested in the board and is willing to help.

I have been told that Ingenic is focusing on IoT market and X1000 is intended for IoT segment. I think that they would be selling several 100Ks of chip over the coming years. But I feel Ingenic spends time only on maintaining their Linux port which is usually based on very old kernel version.

Ingenic is going to release their XBrust2 core with it's products such as X2000 a few days later. Witch is a pure MIPS64r5 with MXU2(A superset of MIPS's MSA SIMD instruction set). The newest kernel port of X1000 maintain by Ingenic is based on Linux-4.4 [1]. After communicated with Ingenic, they said they are forcusing on China domestic market. But they're looking for partners to enter foriegn market.

Quoted 4 lines

[1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this Chinese website, ingenic have a gerrit but I don't have access to it. As my experience, it's hard to develop on Chinese-made chips wihout reading Chinese documents.)

Can you take a diff and upload it somewhere else? Download speed is a couple of bytes per second. Can you put the diff in github or similar other service?
I would like to see if the port uses DT.

author
#18 lore raw

RFC 4/4 MIPS: Ingenic: Add Halley2 development board support

In reply to PrasannaKumar Muralidharan

Halley2 is a development board from Ingenic using X1000 SoC. It comes with either 32MB or 64MB of RAM. Add support for halley2 development board.

Signed-off-by PrasannaKumar Muralidharan <[email protected]>
---
 arch/mips/boot/dts/ingenic/Makefile    |  1 +
 arch/mips/boot/dts/ingenic/halley2.dts | 46 +++++++++++++++++++++++++
 arch/mips/configs/halley2_defconfig    | 61 ++++++++++++++++++++++++++++++++++
 arch/mips/jz4740/Kconfig               |  4 +++
 4 files changed, 112 insertions(+)
 create mode 100644 arch/mips/boot/dts/ingenic/halley2.dts
 create mode 100644 arch/mips/configs/halley2_defconfig
arch/mips/boot/dts/ingenic/Makefile +1 -0
index f2b864f..68e942c 100644
@@ -1,5 +1,6 @@
 dtb-$(CONFIG_JZ4740_QI_LB60)	+= qi_lb60.dtb
 dtb-$(CONFIG_JZ4780_CI20)	+= ci20.dtb
+dtb-$(CONFIG_X1000_HALLEY2)	+= halley2.dtb
 
 obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
arch/mips/boot/dts/ingenic/halley2.dts new file +46 -0

46 lines not on this page · raw message

arch/mips/configs/halley2_defconfig new file +61 -0

61 lines not on this page · raw message

arch/mips/jz4740/Kconfig +4 -0
index 338bc3f..7c66a4b 100644
@@ -11,6 +11,10 @@ config JZ4780_CI20
 	bool "MIPS Creator CI20"
 	select MACH_JZ4780
 
+config X1000_HALLEY2
+	bool "Ingenic X1000 Halley2 Development board"
+	select MACH_X1000
+
 endchoice
 
 config MACH_JZ4740
Signature · 1 line
2.10.0