arm: npcm: Modify NPCM7XX machine code

PATCH In review Tomer Maimon 3 participants 10 messages Mar 15, 2018 – Apr 5, 2018

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/nuvoton npcm architecture

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Tomer Maimon

author maintainer

2018-03-15 23:10 UTC #0 lore raw

cover arm: npcm: Modify NPCM7XX machine code

Addressed patches from:
Arnd Bergmann: https://www.spinics.net/lists/arm-kernel/msg639250.html

			   https://www.spinics.net/lists/arm-kernel/msg639249.html

Modify the NPCM and NPCM7XX configuration and enable L2 cache in the DT_MACHINE_START.

Tomer Maimon (2):
arm: npcm: modify configuration for the NPCM7xx BMC.
arm: npcm: Enable L2 Cache in NPCM7xx

 arch/arm/mach-npcm/Kconfig   | 40 +++++++++++-----------------------------
 arch/arm/mach-npcm/Makefile  |  4 +++-
 arch/arm/mach-npcm/npcm7xx.c |  2 ++
 3 files changed, 16 insertions(+), 30 deletions(-)

Signature · 1 line

2.14.1

Tomer Maimon

author maintainer

2018-03-15 23:10 UTC #1 lore raw

PATCH 1/2 arm: npcm: modify configuration for the NPCM7xx BMC.

Modify configuration and MakeFile
for the Nuvoton NPCM and NPCM7xx BMC.

Signed-off-by Tomer Maimon <[email protected]>

---
 arch/arm/mach-npcm/Kconfig  | 40 +++++++++++-----------------------------
 arch/arm/mach-npcm/Makefile |  4 +++-
 2 files changed, 14 insertions(+), 30 deletions(-)

arch/arm/mach-npcm/Kconfig +11 ~~-29~~

index 6ff9df2636be..684c9c9a32bd 100644
@@ -1,48 +1,30 @@
 menuconfig ARCH_NPCM
 	bool "Nuvoton NPCM Architecture"
-	select ARCH_REQUIRE_GPIOLIB
-	select USE_OF
+	depends on ARCH_MULTI_V7
 	select PINCTRL
-	select PINCTRL_NPCM7XX
 
 if ARCH_NPCM
 
-comment "NPCM7XX CPU type"
-
-config ARCH_NPCM750
-	depends on ARCH_NPCM && ARCH_MULTI_V7
-	bool "Support for NPCM750 BMC CPU (Poleg)"
+config ARCH_NPCM7XX
+	bool "Support for NPCM7xx BMC (Poleg)"
+	depends on ARCH_MULTI_V7
+	select PINCTRL_NPCM7XX
+	select NPCM7XX_TIMER
+	select ARCH_REQUIRE_GPIOLIB
 	select CACHE_L2X0
-	select CPU_V7
 	select ARM_GIC
-	select HAVE_SMP
-	select SMP
-	select SMP_ON_UP
-	select HAVE_ARM_SCU
 	select HAVE_ARM_TWD if SMP
+	select HAVE_ARM_SCU if SMP
+	select ARM_ERRATA_764369 if SMP
 	select ARM_ERRATA_720789
 	select ARM_ERRATA_754322
-	select ARM_ERRATA_764369
 	select ARM_ERRATA_794072
 	select PL310_ERRATA_588369
 	select PL310_ERRATA_727915
-	select USB_EHCI_ROOT_HUB_TT
-	select USB_ARCH_HAS_HCD
-	select USB_ARCH_HAS_EHCI
-	select USB_EHCI_HCD
-	select USB_ARCH_HAS_OHCI
-	select USB_OHCI_HCD
-	select USB
-	select FIQ
-	select CPU_USE_DOMAINS
-	select GENERIC_CLOCKEVENTS
-	select CLKDEV_LOOKUP
-	select COMMON_CLK if OF
-	select NPCM750_TIMER
 	select MFD_SYSCON
 	help
-	  Support for NPCM750 BMC CPU (Poleg).
+	  General support for NPCM7xx BMC (Poleg).
 
-	  Nuvoton NPCM750 BMC based on the Cortex A9.
+	  Nuvoton NPCM7xx BMC based on the Cortex A9.
 
 endif

arch/arm/mach-npcm/Makefile +3 -1

index c7a1316d27c1..0839e8926a84 100644
@@ -1,3 +1,5 @@
 AFLAGS_headsmp.o		+= -march=armv7-a
 
-obj-$(CONFIG_ARCH_NPCM750)	+= npcm7xx.o platsmp.o headsmp.o
+obj-$(CONFIG_ARCH_NPCM7XX)	+= npcm7xx.o
+obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
+

Signature · 1 line

2.14.1

Brendan Higgins

Reviewed-by on v1 1/2

2018-03-16 05:56 UTC #2 lore raw

Re: [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.

Quoted 8 lines · Tomer Maimon

Modify configuration and MakeFile
for the Nuvoton NPCM and NPCM7xx BMC.
Signed-off-by Tomer Maimon <[email protected]>
---
  arch/arm/mach-npcm/Kconfig  | 40 +++++++++++-----------------------------
  arch/arm/mach-npcm/Makefile |  4 +++-
  2 files changed, 14 insertions(+), 30 deletions(-)

<snip>

Reviewed-by Brendan Higgins <[email protected]>

Arnd Bergmann

2018-04-05 12:51 UTC #3 lore raw

Re: [PATCH v1 1/2] arm: npcm: modify configuration for the NPCM7xx BMC.

Quoted 11 lines · Brendan Higgins

Quoted 8 lines · Tomer Maimon
Modify configuration and MakeFile
for the Nuvoton NPCM and NPCM7xx BMC.
Signed-off-by Tomer Maimon <[email protected]>
---
  arch/arm/mach-npcm/Kconfig  | 40 +++++++++++-----------------------------
  arch/arm/mach-npcm/Makefile |  4 +++-
  2 files changed, 14 insertions(+), 30 deletions(-)

Quoted 3 lines

<snip>
Reviewed-by Brendan Higgins <[email protected]>

Sorry for missing this earlier, I did ask for the rework but then didn't see it as it
wasn't in my arm at kernel.org inbox.

Tomer, please make sure that all patches you want to have included in the kernel are sent to that address, while patches you want to have reviewed are not sent to it.

Normally I don't apply patches during the merge window, but this one fixes some build problems, so I've decided to take it.

Arnd

Tomer Maimon

author maintainer

2018-03-15 23:10 UTC #4 lore raw

PATCH 2/2 arm: npcm: Enable L2 Cache in NPCM7xx

In reply to Tomer Maimon

Enable L2 Cache in Nuvoton NPCM7xx BMC.

Signed-off-by Tomer Maimon <[email protected]>

---
 arch/arm/mach-npcm/npcm7xx.c | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/mach-npcm/npcm7xx.c +2 -0

index 5f7cd88103ef..c5f77d854c4f 100644
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
 DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
 	.atag_offset	= 0x100,
 	.dt_compat	= npcm7xx_dt_match,
+	.l2c_aux_val	= 0x0,
+	.l2c_aux_mask	= ~0x0,
 MACHINE_END

Signature · 1 line

2.14.1

Brendan Higgins

2018-03-16 05:52 UTC #5 lore raw

Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx

Quoted 12 lines · Tomer Maimon

Enable L2 Cache in Nuvoton NPCM7xx BMC.
Signed-off-by Tomer Maimon <[email protected]>
---
  arch/arm/mach-npcm/npcm7xx.c | 2 ++
  1 file changed, 2 insertions(+)
arch/arm/mach-npcm/npcm7xx.c +0 -0
index 5f7cd88103ef..c5f77d854c4f 100644

arch/arm/mach-npcm/npcm7xx.c static const char *const npcm7xx_dt_match[] = { · line 21

Quoted 5 lines

arch/arm/mach-npcm/npcm7xx.c +2 -0

@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
  DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
         .atag_offset    = 0x100,
         .dt_compat      = npcm7xx_dt_match,
+       .l2c_aux_val    = 0x0,
+       .l2c_aux_mask   = ~0x0,

You need to limit this to the specific bit(s) you want to set and verify that
the l2c driver does not already manage that bit appropriately and that it can
not be specified via the dtsi.

We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html

Quoted 3 lines

arch/arm/mach-npcm/npcm7xx.c +0 -1
  MACHINE_END
--
2.14.1

Cheers

Tomer Maimon

author maintainer

2018-03-16 21:52 UTC #6 lore raw

Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx

Quoted 9 lines · Brendan Higgins

Quoted 6 lines · Tomer Maimon
Enable L2 Cache in Nuvoton NPCM7xx BMC.
Signed-off-by Tomer Maimon <[email protected]>
---
  arch/arm/mach-npcm/npcm7xx.c | 2 ++
  1 file changed, 2 insertions(+)

Quoted 17 lines

arch/arm/mach-npcm/npcm7xx.c static const char *const npcm7xx_dt_match[] = { · line 21
Quoted 10 lines
arch/arm/mach-npcm/npcm7xx.c +2 -0
index 5f7cd88103ef..c5f77d854c4f 100644
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
  DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
         .atag_offset    = 0x100,
         .dt_compat      = npcm7xx_dt_match,
+       .l2c_aux_val    = 0x0,
+       .l2c_aux_mask   = ~0x0,
You need to limit this to the specific bit(s) you want to set and verify that
the l2c driver does not already manage that bit appropriately and that it can
not be specified via the dtsi.

Do you mean that I need to specify it the same as been done in V7? because when I run with the above l2c_aux_val and l2c_aux_mask parameters I get the same result.

Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to the DT_MACHINE_START
the L2C cache does not initialize.

Quoted 3 lines

We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html

Sorry in this link I see only Russel king comment regarding the L2C

Quoted 9 lines

Quoted 5 lines
arch/arm/mach-npcm/npcm7xx.c +0 -1
  MACHINE_END
--
2.14.1
Cheers

Cheers

Arnd Bergmann

2018-04-05 12:54 UTC #7 lore raw

Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx

Quoted 41 lines · Tomer Maimon

Quoted 10 lines · Brendan Higgins
Quoted 6 lines · Tomer Maimon
Enable L2 Cache in Nuvoton NPCM7xx BMC.
Signed-off-by Tomer Maimon <[email protected]>
---
  arch/arm/mach-npcm/npcm7xx.c | 2 ++
  1 file changed, 2 insertions(+)
Quoted 16 lines
arch/arm/mach-npcm/npcm7xx.c static const char *const npcm7xx_dt_match[] = { · line 21
Quoted 10 lines
arch/arm/mach-npcm/npcm7xx.c +2 -0
index 5f7cd88103ef..c5f77d854c4f 100644
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
  DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
         .atag_offset    = 0x100,
         .dt_compat      = npcm7xx_dt_match,
+       .l2c_aux_val    = 0x0,
+       .l2c_aux_mask   = ~0x0,
You need to limit this to the specific bit(s) you want to set and verify that
the l2c driver does not already manage that bit appropriately and that it can
not be specified via the dtsi.
Do you mean that I need to specify it the same as been done in V7? because when I run with the above l2c_aux_val and l2c_aux_mask parameters I get the same result.
Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to the DT_MACHINE_START
the L2C cache does not initialize.
Quoted 2 lines

Quoted 5 lines

Quoted 2 lines
We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html
Sorry in this link I see only Russel king comment regarding the L2C

I'm not sure what the outcome is, and the patch changelog doesn't explain what the patch is for, so I've not applied it. If you need the patch for correct operation, please resend it with a proper changelog comment explaining why it's needed and why you ended up not setting any of the bits.

The last email in that thread mentions L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?

Arnd

Tomer Maimon

author maintainer

2018-04-05 16:56 UTC #8 lore raw

Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx

Quoted 52 lines · Arnd Bergmann

Quoted 6 lines · Tomer Maimon
Quoted 2 lines · Brendan Higgins
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <[email protected]>
Quoted 9 lines · wrote:
Quoted 9 lines
Review
Quoted 9 lines
Enable L2 Cache in Nuvoton NPCM7xx BMC.
Signed-off-by Tomer Maimon <[email protected]>
---
  arch/arm/mach-npcm/npcm7xx.c | 2 ++
  1 file changed, 2 insertions(+)
(quoted diff) +0 -0
b/arch/arm/mach-npcm/npcm7xx.c
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
index 5f7cd88103ef..c5f77d854c4f 100644
arch/arm/mach-npcm/npcm7xx.c +0 -0
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
  DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
Quoted 8 lines
Quoted 8 lines
arch/arm/mach-npcm/npcm7xx.c static const char *const npcm7xx_dt_match[] = { · line 21
Quoted 4 lines
arch/arm/mach-npcm/npcm7xx.c +2 -0
         .atag_offset    = 0x100,
         .dt_compat      = npcm7xx_dt_match,
+       .l2c_aux_val    = 0x0,
+       .l2c_aux_mask   = ~0x0,
You need to limit this to the specific bit(s) you want to set and verify that
the l2c driver does not already manage that bit appropriately and that
it
Quoted 6 lines
Quoted 2 lines
can
not be specified via the dtsi.
Do you mean that I need to specify it the same as been done in V7? because when I run with the above l2c_aux_val and l2c_aux_mask
parameters I
Quoted 3 lines
get the same result.
Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to
the
Quoted 8 lines
DT_MACHINE_START
the L2C cache does not initialize.
Quoted 4 lines
We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html

Quoted 8 lines

Quoted 1 line
Sorry in this link I see only Russel king comment regarding the L2C
I'm not sure what the outcome is, and the patch changelog doesn't explain what the patch is for, so I've not applied it. If you need the patch for correct operation, please resend it with a proper changelog comment explaining why it's needed and why you ended up not setting any of the bits.

Sorry for not explain it better,

It seems that I have to add l2c_aux_val, l2c_aux_mask parameters to the DT_MACHINE_START
to enable the L2 Cache.

Quoted 4 lines

The last email in that thread mentions L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?

No it is not require this is why I added:
.l2c_aux_val = 0x0,
.l2c_aux_mask = ~0x0,

Quoted 3 lines

Arnd

Can I resend it on Sunday?

Thanks,

Tomer

Arnd Bergmann

2018-04-05 20:42 UTC #9 lore raw

Re: [PATCH v1 2/2] arm: npcm: Enable L2 Cache in NPCM7xx

Quoted 12 lines · Tomer Maimon

Quoted 1 line · Arnd Bergmann
On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <[email protected]> wrote:
It seems that I have to add l2c_aux_val, l2c_aux_mask parameters to the DT_MACHINE_START
to enable the L2 Cache.
Quoted 4 lines
The last email in that thread mentions L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?

Quoted 5 lines

No it is not require this is why I added:
.l2c_aux_val = 0x0,
.l2c_aux_mask = ~0x0,
Can I resend it on Sunday?

Yes, please resend it as soon as you have the time to improve the changelog, no need to wait if you can do it right away. We can always merge bugfixes, but doing it earlier rather than later is better.

Arnd