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Data Port Coherency tests.

RFC In review Tomasz Lis 5 participants 8 messages Mar 20, 2018 – May 4, 2018 Arm/Amlogic Meson SoC support

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Tomasz Lis

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#0 lore raw

RFC 1/1 Data Port Coherency tests.

From: "Lis, Tomasz" <[email protected]>

This adds a new test binary, containing tests for the Data Port Coherency option. The tests check whether the option is correctly set to proper GPU register.

---
 include/drm-uapi/i915_drm.h      |  12 +-
 tests/Makefile.sources           |   1 +
 tests/gem_exec_cache_coherency.c | 307 +++++++++++++++++++++++++++++++++++++++
 tests/meson.build                |   1 +
 4 files changed, 320 insertions(+), 1 deletion(-)
 create mode 100644 tests/gem_exec_cache_coherency.c
include/drm-uapi/i915_drm.h +11 -1
index 16e452a..a84e00f 100644
@@ -529,6 +529,11 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
 
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to switch
+   Data Cache access into Data Port Coherency mode.
+ */
+#define I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY 52
+
 typedef struct drm_i915_getparam {
 	__s32 param;
 	/*
@@ -1048,7 +1053,12 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_FENCE_ARRAY   (1<<19)
 
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
+/* Data Port Coherency capability will be switched before an exec call
+ * which has this flag different than previous call for the context.
+ */
+#define I915_EXEC_DATA_PORT_COHERENT   (1<<20)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_DATA_PORT_COHERENT<<1))
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
tests/Makefile.sources +1 -0
index 4e6f531..1e03011 100644
@@ -73,6 +73,7 @@ TESTS_progs = \
 	gem_exec_basic \
 	gem_exec_big \
 	gem_exec_blt \
+	gem_exec_cache_coherency \
 	gem_exec_capture \
 	gem_exec_create \
 	gem_exec_faulting_reloc \
tests/gem_exec_cache_coherency.c new file +307 -0

307 lines not on this page · raw message

tests/meson.build +1 -0
index 1176463..781fffe 100644
@@ -50,6 +50,7 @@ test_progs = [
 	'gem_exec_basic',
 	'gem_exec_big',
 	'gem_exec_blt',
+	'gem_exec_cache_coherency',
 	'gem_exec_capture',
 	'gem_exec_create',
 	'gem_exec_faulting_reloc',
Signature · 6 lines
2.7.4

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#1 lore raw

Quoting Tomasz Lis (2018-03-20 15:12:32)

Quoted 5 lines

From: "Lis, Tomasz" <[email protected]>

This adds a new test binary, containing tests for the Data Port Coherency option. The tests check whether the option is correctly set to proper GPU register.

But where's the test that it *does* anything? I.e. what's the expected change in user visible behaviour? (What does the flag really mean, now and for years to come?)
-Chris
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#2 lore raw

Its required to support fine grain SVM in OpenCL. This functionality is used by new OCL driver (aka. NEO):
https://github.com/intel/compute-runtime

Starting from commit: 933312e0986d3a7c1ef557e511eb4ced301ea292

-----Original Message-----
From: Chris Wilson [mailto:[email protected]]
Sent: Tuesday, March 20, 2018 4:31 PM
To: Lis, Tomasz <[email protected]>; [email protected]
Cc: Dunajski, Bartosz <[email protected]>; [email protected]; Winiarski, Michal <[email protected]>
Subject: Re: [RFC v1] Data Port Coherency tests.

Quoting Tomasz Lis (2018-03-20 15:12:32)

Quoted 5 lines

From: "Lis, Tomasz" <[email protected]>

This adds a new test binary, containing tests for the Data Port Coherency option. The tests check whether the option is correctly set to proper GPU register.

But where's the test that it *does* anything? I.e. what's the expected change in user visible behaviour? (What does the flag really mean, now and for years to come?) -Chris
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#3 lore raw
In reply to Chris Wilson

Quoting Chris Wilson (2018-03-20 15:30:59)

Quoted 10 lines

Quoting Tomasz Lis (2018-03-20 15:12:32)

Quoted 5 lines

From: "Lis, Tomasz" <[email protected]>

This adds a new test binary, containing tests for the Data Port Coherency option. The tests check whether the option is correctly set to proper GPU register.

But where's the test that it *does* anything? I.e. what's the expected change in user visible behaviour? (What does the flag really mean, now and for years to come?)

To be clear; this test illustrates that it is a context register being tweaked and not an execbuf property.
-Chris
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#4 lore raw
Quoted 10 lines · Chris Wilson

Quoting Chris Wilson (2018-03-20 15:30:59)

Quoted 9 lines

Quoting Tomasz Lis (2018-03-20 15:12:32)

Quoted 5 lines

From: "Lis, Tomasz" <[email protected]>

This adds a new test binary, containing tests for the Data Port Coherency option. The tests check whether the option is correctly set to proper GPU register.

But where's the test that it *does* anything? I.e. what's the expected change in user visible behaviour? (What does the flag really mean, now and for years to come?)

With a test that "does anything" (which I understand as - submitting large workload and checking the coherency while the workload is executing) we would be testing the hardware, not the kernel. I prepared a test binary designed to test the kernel change I proposed. This is what I consider good practices.
Do we have another approach when developing IGT?

Quoted 3 lines

To be clear; this test illustrates that it is a context register being tweaked and not an execbuf property.
-Chris

I agree the hardware flag is within hardware context. Both the kernel patch and the IGT test are accessing that bit, so they both illustrate it is a context register. But both patches also implement UMD interface to that flag via execbuf flag. What do you mean when you write this is "not an execbuf property"?

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#5 lore raw

Quoting Lis, Tomasz (2018-03-20 18:27:44)

Quoted 10 lines · Chris Wilson
Quoted 7 lines

Quoting Chris Wilson (2018-03-20 15:30:59)

Quoted 6 lines

Quoting Tomasz Lis (2018-03-20 15:12:32)

Quoted 5 lines

From: "Lis, Tomasz" <[email protected]>

This adds a new test binary, containing tests for the Data Port Coherency option. The tests check whether the option is correctly set to proper GPU register.

Quoted 7 lines
Quoted 3 lines
Quoted 3 lines

But where's the test that it *does* anything? I.e. what's the expected change in user visible behaviour? (What does the flag really mean, now and for years to come?)

With a test that "does anything" (which I understand as - submitting large workload and checking the coherency while the workload is executing) we would be testing the hardware, not the kernel. I prepared a test binary designed to test the kernel change I proposed. This is what I consider good practices.
Do we have another approach when developing IGT?

What we try to avoid is "visible userspace breakage". So when some added kernel feature introduces a behavioral change for userspace, the accompanying tests should make sure that change is observed with the feature bit flipped. That's pretty much the only way we can make sure the written userspace applications using the feature will keep working when going forward.

Writing to MMIO address X so that the bits Y and Z stick will only guarantee that there is some hardware register in there. It is not very valuable of a test because making sure the feature keeps working will implicitly test the same thing.

Hopefully this answers the question.

Regards, Joonas

Quoted 11 lines
Quoted 4 lines

To be clear; this test illustrates that it is a context register being tweaked and not an execbuf property.
-Chris

I agree the hardware flag is within hardware context. Both the kernel patch and the IGT test are accessing that bit, so they both illustrate it is a context register.
But both patches also implement UMD interface to that flag via execbuf flag. What do you mean when you write this is "not an execbuf property"?

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#6 lore raw

[igt-dev] ✓ Fi.CI.BAT: success for Data Port Coherency tests.

In reply to Tomasz Lis
== Series Details ==

== Series Details ==

Series: Data Port Coherency tests.
URL : https://patchwork.freedesktop.org/series/40288/
State : success

== Summary ==

IGT patchset tested on top of latest successful build 178e7f3da66cd02660a86257df75708a0efa3bbc tests/kms_frontbuffer_tracking: Update check for PSR status

with latest DRM-Tip kernel build CI_DRM_3958
9d737cebc219 drm-tip: 2018y-03m-20d-14h-56m-05s UTC integration manifest

Testlist changes:
+igt@gem_exec_cache_coherency@coherency-hibernate-ctx-render +igt@gem_exec_cache_coherency@coherency-hibernate-ctx-sep-render +igt@gem_exec_cache_coherency@coherency-hibernate-render +igt@gem_exec_cache_coherency@coherency-hibernate-sep-render +igt@gem_exec_cache_coherency@coherency-rc6-ctx-render +igt@gem_exec_cache_coherency@coherency-rc6-ctx-sep-render +igt@gem_exec_cache_coherency@coherency-rc6-render +igt@gem_exec_cache_coherency@coherency-rc6-sep-render +igt@gem_exec_cache_coherency@coherency-reset-ctx-render +igt@gem_exec_cache_coherency@coherency-reset-ctx-sep-render +igt@gem_exec_cache_coherency@coherency-reset-render +igt@gem_exec_cache_coherency@coherency-reset-sep-render +igt@gem_exec_cache_coherency@coherency-settings-ctx-render +igt@gem_exec_cache_coherency@coherency-settings-ctx-sep-render +igt@gem_exec_cache_coherency@coherency-settings-render +igt@gem_exec_cache_coherency@coherency-settings-sep-render +igt@gem_exec_cache_coherency@coherency-suspend-ctx-render +igt@gem_exec_cache_coherency@coherency-suspend-ctx-sep-render +igt@gem_exec_cache_coherency@coherency-suspend-render +igt@gem_exec_cache_coherency@coherency-suspend-sep-render

---- Possible new issues:

Test kms_pipe_crc_basic:

        Subgroup suspend-read-crc-pipe-a:
                incomplete -> PASS       (fi-cfl-s2)

---- Known issues:

Test gem_mmap_gtt:

        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test kms_chamelium:
        Subgroup dp-edid-read:
                pass       -> FAIL       (fi-kbl-7500u) fdo#102505

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:429s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:445s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:383s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:540s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:297s
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:514s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:516s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:516s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:510s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:412s
fi-cfl-s2        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:581s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:512s
fi-cnl-drrs      total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  time:539s
fi-elk-e7500     total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  time:429s
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:317s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:540s
fi-hsw-4770      total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:406s
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:421s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:465s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:432s
fi-kbl-7500u     total:285  pass:259  dwarn:1   dfail:0   fail:1   skip:24  time:477s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:471s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:513s
fi-pnv-d510      total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  time:658s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:441s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:531s
fi-skl-6700hq    total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:540s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:509s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:500s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:430s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:446s
fi-snb-2520m     total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:570s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:403s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1170/issues.html
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#7 lore raw

[igt-dev] ✓ Fi.CI.IGT: success for Data Port Coherency tests.

In reply to Tomasz Lis
== Series Details ==

== Series Details ==

Series: Data Port Coherency tests.
URL : https://patchwork.freedesktop.org/series/40288/
State : success

== Summary ==

---- Known issues:

Test kms_plane_multiple:

        Subgroup atomic-pipe-a-tiling-x:
                pass       -> FAIL       (shard-snb) fdo#103166
Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-apl) fdo#99912
Test kms_vblank:
        Subgroup pipe-b-ts-continuation-dpms-suspend:
                incomplete -> PASS       (shard-hsw) fdo#105054
Test perf:
        Subgroup blocking:
                pass       -> FAIL       (shard-hsw) fdo#102252

fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#105054 https://bugs.freedesktop.org/show_bug.cgi?id=105054
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apl        total:3494 pass:1814 dwarn:1   dfail:0   fail:23  skip:1655 time:13076s
shard-hsw        total:3494 pass:1767 dwarn:1   dfail:0   fail:18  skip:1707 time:11852s
shard-snb        total:3494 pass:1357 dwarn:1   dfail:0   fail:19  skip:2117 time:7203s

Blacklisted hosts:
shard-kbl total:3494 pass:1939 dwarn:1 dfail:0 fail:25 skip:1529 time:9915s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1170/shards.html
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