drm/amd/pp: Initialize default thermal control type for each asic

index 6318438..3f1e822 100644
@@ -33,6 +33,8 @@
 #include "ppsmc.h"
 #include "amd_acpi.h"
 #include "pp_psm.h"
+#include "atombios.h"
+#include "pptable.h"
 
 extern const struct pp_smumgr_func ci_smu_funcs;
 extern const struct pp_smumgr_func smu8_smu_funcs;

@@ -87,6 +89,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 	hwmgr->fan_ctrl_is_in_default_mode = true;
 	hwmgr->reload_fw = 1;
 	hwmgr_init_workload_prority(hwmgr);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_NONE;
 
 	switch (hwmgr->chip_family) {
 	case AMDGPU_FAMILY_CI:

@@ -139,6 +142,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 	case AMDGPU_FAMILY_AI:
 		switch (hwmgr->chip_id) {
 		case CHIP_VEGA10:
+			hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_VEGA10;
 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
 			vega10_hwmgr_init(hwmgr);
 			break;

@@ -418,6 +422,7 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 							PHM_PlatformCaps_TCPRamping);
 	}
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_POLARIS10;
 	return 0;
 }
 

@@ -433,6 +438,7 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 			PHM_PlatformCaps_TDRamping);
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_TCPRamping);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_FIJI;
 	return 0;
 }
 

@@ -453,6 +459,7 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 		      PHM_PlatformCaps_UVDPowerGating);
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 		      PHM_PlatformCaps_VCEPowerGating);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_TONGA;
 	return 0;
 }
 

@@ -468,6 +475,7 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 			PHM_PlatformCaps_TDRamping);
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_TCPRamping);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_ICELAND;
 	return 0;
 }
 

@@ -485,5 +493,6 @@ int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 			PHM_PlatformCaps_MemorySpreadSpectrumSupport);
 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_EngineSpreadSpectrumSupport);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_CISLANDS;
 	return 0;
 }

index 7bb9dd9..f177183 100644
@@ -4830,7 +4830,7 @@ static int vega10_register_irq_handlers(struct pp_hwmgr *hwmgr)
 	source->funcs = &vega10_irq_funcs;
 
 	if (hwmgr->thermal_controller.ucType ==
-			ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 ||
+			hwmgr->default_thermal_ctrl_type ||
 		hwmgr->thermal_controller.ucType ==
 			ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
 

index efdcf31..f32d5db 100644
@@ -720,6 +720,7 @@ struct pp_hwmgr {
 	uint32_t usec_timeout;
 	void *pptable;
 	struct phm_platform_descriptor platform_descriptor;
+	uint8_t default_thermal_ctrl_type;
 	void *backend;
 
 	void *smu_backend;

index 8a81360..5323f74 100644
@@ -3996,8 +3996,41 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
 			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
 }
 
+static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
+	.process = phm_irq_process,
+};
+
 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
 {
+	struct amdgpu_irq_src *source =
+		kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
+
+	if (!source)
+		return -ENOMEM;
+
+	source->funcs = &smu7_irq_funcs;
+
+	if (hwmgr->thermal_controller.ucType ==
+			hwmgr->default_thermal_ctrl_type ||
+		hwmgr->thermal_controller.ucType ==
+			ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
+
+		amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+				AMDGPU_IH_CLIENTID_LEGACY,
+				230,
+				source);
+		amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+				AMDGPU_IH_CLIENTID_LEGACY,
+				231,
+				source);
+	}
+
+	/* Register CTF(GPIO_19) interrupt */
+	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+			AMDGPU_IH_CLIENTID_LEGACY,
+			83,
+			source);
+
 	return 0;
 }
 

index 8a81360..5323f74 100644
@@ -3996,8 +3996,41 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
 }
 
+static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
+       .process = phm_irq_process,
+};
+
 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
 {
+       struct amdgpu_irq_src *source =
+               kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
+
+       if (!source)
+               return -ENOMEM;
+
+       source->funcs = &smu7_irq_funcs;
+
+       if (hwmgr->thermal_controller.ucType ==
+                       hwmgr->default_thermal_ctrl_type ||
+               hwmgr->thermal_controller.ucType ==
+                       ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
+
+               amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+                               AMDGPU_IH_CLIENTID_LEGACY,
+                               230,
+                               source);
+               amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+                               AMDGPU_IH_CLIENTID_LEGACY,
+                               231,
+                               source);
+       }
+
+       /* Register CTF(GPIO_19) interrupt */
+       amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+                       AMDGPU_IH_CLIENTID_LEGACY,
+                       83,
+                       source);
+
         return 0;
 }