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FAILED: patch "[PATCH] MIPS: ralink: Fix booting on MT7621" failed to apply to 4.9-stable tree

PATCH [email protected] 1 participant 1 message Mar 24, 2018

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The patch below does not apply to the 4.9-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From a63d706ea719190a79a6c769e898f70680044d3e Mon Sep 17 00:00:00 2001

From: NeilBrown <[email protected]>
Date: Wed, 21 Mar 2018 14:02:10 +1100
Subject: [PATCH] MIPS: ralink: Fix booting on MT7621

Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 has not been able to boot.

This commit caused mips_cm_probe() to be called before mt7621.c::proc_soc_init().

prom_soc_init() has a comment explaining that mips_cm_probe() "wipes out the bootloader config" and means that configuration registers are no longer available. It has some code to re-enable this config.

Before this re-enable code is run, the sysc register cannot be read, so when SYSC_REG_CHIP_NAME0 is read, a garbage value is returned and panic() is called.

If we move the config-repair code to the top of prom_soc_init(), the registers can be read and boot can proceed.

Very occasionally, the first register read after the reconfiguration returns garbage, so add a call to __sync().

Fixes 3af5a67c86a3 ("MIPS: Fix early CM probing")
Signed-off-by NeilBrown <[email protected]>
Reviewed-by Matt Redfearn <[email protected]>
Cc John Crispin <[email protected]>
Cc Ralf Baechle <[email protected]>
Cc [email protected]
Cc <[email protected]> # 4.5+

Patchwork: https://patchwork.linux-mips.org/patch/18859/

Signed-off-by James Hogan <[email protected]>
arch/mips/ralink/mt7621.c +22 -20
index 1b274742077d..d2718de60b9b 100644
@@ -170,6 +170,28 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 	u32 n1;
 	u32 rev;
 
+	/* Early detection of CMP support */
+	mips_cm_probe();
+	mips_cpc_probe();
+
+	if (mips_cps_numiocu(0)) {
+		/*
+		 * mips_cm_probe() wipes out bootloader
+		 * config for CM regions and we have to configure them
+		 * again. This SoC cannot talk to pamlbus devices
+		 * witout proper iocu region set up.
+		 *
+		 * FIXME: it would be better to do this with values
+		 * from DT, but we need this very early because
+		 * without this we cannot talk to pretty much anything
+		 * including serial.
+		 */
+		write_gcr_reg0_base(MT7621_PALMBUS_BASE);
+		write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
+				    CM_GCR_REGn_MASK_CMTGT_IOCU0);
+		__sync();
+	}
+
 	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 

@@ -194,26 +216,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
 	rt2880_pinmux_data = mt7621_pinmux_data;
 
-	/* Early detection of CMP support */
-	mips_cm_probe();
-	mips_cpc_probe();
-
-	if (mips_cps_numiocu(0)) {
-		/*
-		 * mips_cm_probe() wipes out bootloader
-		 * config for CM regions and we have to configure them
-		 * again. This SoC cannot talk to pamlbus devices
-		 * witout proper iocu region set up.
-		 *
-		 * FIXME: it would be better to do this with values
-		 * from DT, but we need this very early because
-		 * without this we cannot talk to pretty much anything
-		 * including serial.
-		 */
-		write_gcr_reg0_base(MT7621_PALMBUS_BASE);
-		write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
-				    CM_GCR_REGn_MASK_CMTGT_IOCU0);
-	}
 
 	if (!register_cps_smp_ops())
 		return;