io: prevent compiler reordering on the default writeX() implementation

The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX().

In the abscence of a read barrier or when using a strongly ordered architecture, readX() should at least have a compiler barrier in it to prevent commpiler from clobbering the execution order.

Signed-off-by Sinan Kaya <[email protected]>

---
 include/asm-generic/io.h | 28 ++++++++++++++++++++++++----
 1 file changed, 24 insertions(+), 4 deletions(-)

include/asm-generic/io.h +24 -4

index e8c2078..2554f15 100644
@@ -110,7 +110,12 @@ static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
 #define readb readb
 static inline u8 readb(const volatile void __iomem *addr)
 {
-	return __raw_readb(addr);
+	u8 val;
+
+	val = __raw_readb(addr);
+	barrier();
+
+	return val;
 }
 #endif
 

@@ -118,7 +123,12 @@ static inline u8 readb(const volatile void __iomem *addr)
 #define readw readw
 static inline u16 readw(const volatile void __iomem *addr)
 {
-	return __le16_to_cpu(__raw_readw(addr));
+	u16 val;
+
+	val = __le16_to_cpu(__raw_readw(addr));
+	barrier();
+
+	return val;
 }
 #endif
 

@@ -126,7 +136,12 @@ static inline u16 readw(const volatile void __iomem *addr)
 #define readl readl
 static inline u32 readl(const volatile void __iomem *addr)
 {
-	return __le32_to_cpu(__raw_readl(addr));
+	u32 val;
+
+	val = __le32_to_cpu(__raw_readl(addr));
+	barrier();
+
+	return val;
 }
 #endif
 

@@ -135,7 +150,12 @@ static inline u32 readl(const volatile void __iomem *addr)
 #define readq readq
 static inline u64 readq(const volatile void __iomem *addr)
 {
-	return __le64_to_cpu(__raw_readq(addr));
+	u64 val;
+
+	val = __le64_to_cpu(__raw_readq(addr));
+	barrier();
+
+	return val;
 }
 #endif
 #endif /* CONFIG_64BIT */

Signature · 6 lines

2.7.4

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Hi,

Quoted 3 lines · Sinan Kaya

The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX().

Could you please specify what the compiler is potentially reordering __raw_readX() against, and why this would be wrong?

e.g. do we care about prior normal memory accesses, subsequent normal memory accesses, and/or other IO accesses?

I assume that the asm-generic __raw_{read,write}X() implementations are all ordered w.r.t. each other (at least for a specific device).

Quoted 13 lines · Mark Rutland

Hi,

Quoted 3 lines · Sinan Kaya

The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX().

Could you please specify what the compiler is potentially reordering __raw_readX() against, and why this would be wrong?

e.g. do we care about prior normal memory accesses, subsequent normal memory accesses, and/or other IO accesses?

Quoted 2 lines

I assume that the asm-generic __raw_{read,write}X() implementations are all ordered w.r.t. each other (at least for a specific device).

I think that is correct: the compiler won't reorder those because of the 'volatile' pointer dereference, but it can reorder access to a normal pointer against a __raw_readl()/__raw_writel(), which breaks the scenario of using writel to trigger a DMA, or using a readl to see if a DMA has completed.

The question is whether we should use a stronger barrier such as rmb() amd wmb() here rather than a simple compiler barrier.

I would assume that on complex architectures with write buffers and out-of-order prefetching, those are required, while on architectures without those features, the barriers are cheap.

Arnd

Quoted 14 lines · Arnd Bergmann

Quoted 13 lines · Mark Rutland

Hi,

Quoted 3 lines · Sinan Kaya

The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX().

Could you please specify what the compiler is potentially reordering __raw_readX() against, and why this would be wrong?

e.g. do we care about prior normal memory accesses, subsequent normal memory accesses, and/or other IO accesses?

Quoted 8 lines

Quoted 2 lines

I assume that the asm-generic __raw_{read,write}X() implementations are all ordered w.r.t. each other (at least for a specific device).

I think that is correct: the compiler won't reorder those because of the 'volatile' pointer dereference, but it can reorder access to a normal pointer against a __raw_readl()/__raw_writel(), which breaks the scenario of using writel to trigger a DMA, or using a readl to see if a DMA has completed.

Yes, we are worried about memory update vs. IO update ordering here. That was the reason why barrier() was introduced in this patch. I'll try to clarify that better in the commit text.

Quoted 4 lines

The question is whether we should use a stronger barrier such as rmb() amd wmb() here rather than a simple compiler barrier.

Quoted 3 lines

I would assume that on complex architectures with write buffers and out-of-order prefetching, those are required, while on architectures without those features, the barriers are cheap.

That's my reasoning too. I'm trying to follow the x86 example here where there is a compiler barrier in writeX() and readX() family of functions.

Quoted 32 lines · Sinan Kaya

Quoted 14 lines · Arnd Bergmann

Quoted 13 lines · Mark Rutland

Hi,

Quoted 3 lines · Sinan Kaya

The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX().

Could you please specify what the compiler is potentially reordering __raw_readX() against, and why this would be wrong?

e.g. do we care about prior normal memory accesses, subsequent normal memory accesses, and/or other IO accesses?

Quoted 8 lines

Quoted 2 lines

I assume that the asm-generic __raw_{read,write}X() implementations are all ordered w.r.t. each other (at least for a specific device).

I think that is correct: the compiler won't reorder those because of the 'volatile' pointer dereference, but it can reorder access to a normal pointer against a __raw_readl()/__raw_writel(), which breaks the scenario of using writel to trigger a DMA, or using a readl to see if a DMA has completed.

Yes, we are worried about memory update vs. IO update ordering here. That was the reason why barrier() was introduced in this patch. I'll try to clarify that better in the commit text.

Quoted 4 lines

The question is whether we should use a stronger barrier such as rmb() amd wmb() here rather than a simple compiler barrier.

Quoted 6 lines

Quoted 3 lines

I would assume that on complex architectures with write buffers and out-of-order prefetching, those are required, while on architectures without those features, the barriers are cheap.

That's my reasoning too. I'm trying to follow the x86 example here where there is a compiler barrier in writeX() and readX() family of functions.

I think x86 is the special case here because it implicitly guarantees the strict ordering in the hardware, as long as the compiler gets it right. For the asm-generic version, it may be better to play safe and do the safest version, requiring architectures to override that barrier if they want to be faster.

We could use the same macros that riscv has, using __io_br(), __io_ar(), __io_bw() and __io_aw() for before/after read/write.

Arnd

Quoted 32 lines · Sinan Kaya

Quoted 14 lines · Arnd Bergmann

Quoted 13 lines · Mark Rutland

Hi,

Quoted 3 lines · Sinan Kaya

The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX().

Could you please specify what the compiler is potentially reordering __raw_readX() against, and why this would be wrong?

e.g. do we care about prior normal memory accesses, subsequent normal memory accesses, and/or other IO accesses?

Quoted 8 lines

Quoted 2 lines

I assume that the asm-generic __raw_{read,write}X() implementations are all ordered w.r.t. each other (at least for a specific device).

I think that is correct: the compiler won't reorder those because of the 'volatile' pointer dereference, but it can reorder access to a normal pointer against a __raw_readl()/__raw_writel(), which breaks the scenario of using writel to trigger a DMA, or using a readl to see if a DMA has completed.

Yes, we are worried about memory update vs. IO update ordering here. That was the reason why barrier() was introduced in this patch. I'll try to clarify that better in the commit text.

Quoted 4 lines

The question is whether we should use a stronger barrier such as rmb() amd wmb() here rather than a simple compiler barrier.

Quoted 6 lines

Quoted 3 lines

I would assume that on complex architectures with write buffers and out-of-order prefetching, those are required, while on architectures without those features, the barriers are cheap.

That's my reasoning too. I'm trying to follow the x86 example here where there is a compiler barrier in writeX() and readX() family of functions.

I think x86 is the special case here because it implicitly guarantees the strict ordering in the hardware, as long as the compiler gets it right. For the asm-generic version, it may be better to play safe and do the safest version, requiring architectures to override that barrier if they want to be faster.

We could use the same macros that riscv has, using __io_br(), __io_ar(), __io_bw() and __io_aw() for before/after read/write.

Quoted 46 lines · Arnd Bergmann

Quoted 32 lines · Sinan Kaya

Quoted 14 lines · Arnd Bergmann

Quoted 13 lines · Mark Rutland

Hi,

Quoted 3 lines · Sinan Kaya

The default implementation of mapping readX() to __raw_readX() is wrong. readX() has stronger ordering semantics. Compiler is allowed to reorder __raw_readX().

Could you please specify what the compiler is potentially reordering __raw_readX() against, and why this would be wrong?

e.g. do we care about prior normal memory accesses, subsequent normal memory accesses, and/or other IO accesses?

Quoted 8 lines

Quoted 2 lines

I assume that the asm-generic __raw_{read,write}X() implementations are all ordered w.r.t. each other (at least for a specific device).

I think that is correct: the compiler won't reorder those because of the 'volatile' pointer dereference, but it can reorder access to a normal pointer against a __raw_readl()/__raw_writel(), which breaks the scenario of using writel to trigger a DMA, or using a readl to see if a DMA has completed.

Yes, we are worried about memory update vs. IO update ordering here. That was the reason why barrier() was introduced in this patch. I'll try to clarify that better in the commit text.

Quoted 4 lines

The question is whether we should use a stronger barrier such as rmb() amd wmb() here rather than a simple compiler barrier.

Quoted 6 lines

Quoted 3 lines

I would assume that on complex architectures with write buffers and out-of-order prefetching, those are required, while on architectures without those features, the barriers are cheap.

That's my reasoning too. I'm trying to follow the x86 example here where there is a compiler barrier in writeX() and readX() family of functions.

I think x86 is the special case here because it implicitly guarantees the strict ordering in the hardware, as long as the compiler gets it right. For the asm-generic version, it may be better to play safe and do the safest version, requiring architectures to override that barrier if they want to be faster.

Quoted 2 lines

We could use the same macros that riscv has, using __io_br(), __io_ar(), __io_bw() and __io_aw() for before/after read/write.

FWIW, when I wrote this I wasn't sure what the RISC-V memory model was going to be so I just picked something generic.  In other words, it's already a generic interface, just one that we're the only users of :).

Quoted 1 line · Palmer Dabbelt

Are we looking for something like this?

include/asm-generic/io.h +0 -1

 #ifndef readb
 #define readb readb
-static inline u8 readb(const volatile void __iomem *addr)

Quoted 4 lines · Sinan Kaya

Quoted 1 line · Palmer Dabbelt

Are we looking for something like this?

Yes, exactly, plus the same for write and in/out of course.

Quoted 9 lines

include/asm-generic/io.h +2 -4

 #ifndef readb
 #define readb readb
-static inline u8 readb(const volatile void __iomem *addr)
-{
-       return __raw_readb(addr);
-}
+#define readb(c)                               \
+       ({ u8  __v;                             \

include/asm-generic/io.h static inline void __raw_writeq(u64 value, volatile void __iomem *addr) · line 127

Quoted 5 lines

include/asm-generic/io.h +4 -0

+        __io_br();                             \
+        __v = __raw_readb(c);                  \
+        __io_ar();                             \
+        __v; })
 #endif

I would prefer leaving these as inline functions, but that's only a cosmetic difference.

Arnd

Yes, exactly, plus the same for write and in/out of course.

Quoted 1 line · Arnd Bergmann

Yes, exactly, plus the same for write and in/out of course.

I was looking at this...

inb() and outb() seem to be calling writeb(). It gets the wmb/barrier automatically when we fix writeb().

Did I miss something?

Quoted 9 lines · Sinan Kaya

Quoted 1 line · Arnd Bergmann

Yes, exactly, plus the same for write and in/out of course.

I was looking at this...

inb() and outb() seem to be calling writeb(). It gets the wmb/barrier automatically when we fix writeb().

Did I miss something?

At least outb() needs stricter barriers than writeb() in theory, what we want here
is that outb() has not just made it out to the device but that the write has been
confirmed completed by the device. Some architectures can't do it, but those that can should have an easy way to hook into that using a separate set of barriers.

Using the riscv barrier names, we could do this like

#ifndef __io_bw()
#define __io_bw() wmb()
#endif

#ifndef __io_aw
#define __io_aw() barrier()
#endif

#ifndef __io_pbw
#define __io_pbw() __io_bw()
#endif

#ifndef __io_paw
#define __io_paw() __io_aw()
#endif

and the same thing for reads. This way, an architecture could override any of those, but still get reasonable defaults for the others. For __io_bw(), I picked barrier() instead of do {} while (0), no idea if that's any better, I just play safe here.

Arnd