reset: socfpga: add reset driver for SoCFPGA platform
PATCH 1/1 reset: socfpga: add reset driver for SoCFPGA platform
Add a DM compatible reset driver for the SoCFPGA platform.
--- drivers/reset/Kconfig | 7 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/reset/reset-socfpga.c
drivers/reset/Kconfig +7 -0
@@ -83,4 +83,11 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_SOCFPGA + bool "Reset controller driver for SoCFPGA" + depends on DM_RESET && ARCH_SOCFPGA + default y + help + Support for reset controller on SoCFPGA platform. + endmenu
drivers/reset/Makefile +1 -0
@@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
drivers/reset/reset-socfpga.c new file +111 -0
111 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH 1/1 reset: socfpga: add reset driver for SoCFPGA platform
Quoted 73 lines · Dinh Nguyen
Add a DM compatible reset driver for the SoCFPGA platform.
Signed-off-by Dinh Nguyen <[email protected]>--- drivers/reset/Kconfig | 7 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/reset/reset-socfpga.cdrivers/reset/Kconfig +7
-0@@ -83,4 +83,11 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_SOCFPGA + bool "Reset controller driver for SoCFPGA" + depends on DM_RESET && ARCH_SOCFPGA + default y + help + Support for reset controller on SoCFPGA platform. + endmenudrivers/reset/Makefile +1
-0@@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.odrivers/reset/reset-socfpga.c new file +32
-0@@ -0,0 +1,111 @@ +/* +* Socfpga Reset Controller Driver +* +* Copyright 2014 Steffen Trumtrar <[email protected]> +* +* based on +* Allwinner SoCs Reset Controller driver +* +* Copyright 2013 Maxime Ripard +* +* Maxime Ripard <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <dm/of_access.h> +#include <reset-uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 + +struct socfpga_reset_data { +void __iomem *membase; +}; + +static int socfpga_reset_assert (struct reset_ctl *reset_ctl) +{
drivers/reset/reset-socfpga.c line 42
Quoted 10 lines
drivers/reset/reset-socfpga.c new file +10
-0+struct socfpga_reset_data *data =dev_get_priv (reset_ctl->dev); +int id = reset_ctl->id; +int reg_width =sizeof (u32); +int bank = id / (reg_width *BITS_PER_BYTE ); +int offset = id % (reg_width *BITS_PER_BYTE ); +unsigned long flags; +u32 reg; + + reg =readl (data->membase + (bank *BANK_INCREMENT )); +writel (reg |BIT (offset), data->membase + (bank *BANK_INCREMENT ));
setbits_le32() ?
Quoted 5 lines
drivers/reset/reset-socfpga.c new file +5
-0+return 0 ; +} + +static int socfpga_reset_deassert (struct reset_ctl *reset_ctl) +{
drivers/reset/reset-socfpga.c line 57
Quoted 10 lines
drivers/reset/reset-socfpga.c new file +10
-0+struct socfpga_reset_data *data =dev_get_priv (reset_ctl->dev); +int id = reset_ctl->id; +int reg_width =sizeof (u32); +int bank = id / (reg_width *BITS_PER_BYTE ); +int offset = id % (reg_width *BITS_PER_BYTE ); +unsigned long flags; +u32 reg; + + reg =readl (data->membase + (bank *BANK_INCREMENT )); +writel (reg & ~BIT (offset), data->membase + (bank *BANK_INCREMENT ));
clrbits_le32() ?
[...]
What I do not see is any user of this code, nor any conversion of existing systems to use this code. Is that expected to happen ? I do not want to see dead code piling up in U-Boot.
Signature · 2 lines
Best regards, Marek Vasut
PATCH 1/1 reset: socfpga: add reset driver for SoCFPGA platform
Quoted 78 lines · Marek Vasut
Quoted 77 lines · Dinh Nguyen
Add a DM compatible reset driver for the SoCFPGA platform.
Signed-off-by Dinh Nguyen <[email protected]>--- drivers/reset/Kconfig | 7 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/reset/reset-socfpga.cdrivers/reset/Kconfig +7
-0@@ -83,4 +83,11 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_SOCFPGA + bool "Reset controller driver for SoCFPGA" + depends on DM_RESET && ARCH_SOCFPGA + default y + help + Support for reset controller on SoCFPGA platform. + endmenudrivers/reset/Makefile +1
-0@@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.odrivers/reset/reset-socfpga.c new file +36
-0@@ -0,0 +1,111 @@ +/* +* Socfpga Reset Controller Driver +* +* Copyright 2014 Steffen Trumtrar <[email protected]> +* +* based on +* Allwinner SoCs Reset Controller driver +* +* Copyright 2013 Maxime Ripard +* +* Maxime Ripard <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <dm/of_access.h> +#include <reset-uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 + +struct socfpga_reset_data { +void __iomem *membase; +}; + +static int socfpga_reset_assert (struct reset_ctl *reset_ctl) +{ +struct socfpga_reset_data *data =dev_get_priv (reset_ctl->dev); +int id = reset_ctl->id; +int reg_width =sizeof (u32); +int bank = id / (reg_width *BITS_PER_BYTE );
Quoted 9 lines
drivers/reset/reset-socfpga.c line 42
Quoted 6 lines
drivers/reset/reset-socfpga.c new file +6
-0+int offset = id % (reg_width *BITS_PER_BYTE ); +unsigned long flags; +u32 reg; + + reg =readl (data->membase + (bank *BANK_INCREMENT )); +writel (reg |BIT (offset), data->membase + (bank *BANK_INCREMENT ));
setbits_le32()?
Ok..
Quoted 9 lines
Quoted 9 lines
drivers/reset/reset-socfpga.c new file +9
-0+return 0 ; +} + +static int socfpga_reset_deassert (struct reset_ctl *reset_ctl) +{ +struct socfpga_reset_data *data =dev_get_priv (reset_ctl->dev); +int id = reset_ctl->id; +int reg_width =sizeof (u32); +int bank = id / (reg_width *BITS_PER_BYTE );
Quoted 9 lines
drivers/reset/reset-socfpga.c line 57
Quoted 6 lines
drivers/reset/reset-socfpga.c new file +6
-0+int offset = id % (reg_width *BITS_PER_BYTE ); +unsigned long flags; +u32 reg; + + reg =readl (data->membase + (bank *BANK_INCREMENT )); +writel (reg & ~BIT (offset), data->membase + (bank *BANK_INCREMENT ));
clrbits_le32()?
Ok..
Quoted 6 lines
[...]
What I do not see is any user of this code, nor any conversion of existing systems to use this code. Is that expected to happen ? I do not want to see dead code piling up in U-Boot.
I have a patchset that tested this code, the i2c support in SoCFPGA was converted to DM, and uses this reset framework. Should I send that along with this patch in v2?
Dinh
PATCH 1/1 reset: socfpga: add reset driver for SoCFPGA platform
Quoted 116 lines · Dinh Nguyen
Quoted 78 lines · Marek Vasut
Quoted 77 lines · Dinh Nguyen
Add a DM compatible reset driver for the SoCFPGA platform.
Signed-off-by Dinh Nguyen <[email protected]>--- drivers/reset/Kconfig | 7 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-socfpga.c | 111 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) create mode 100644 drivers/reset/reset-socfpga.cdrivers/reset/Kconfig +7
-0@@ -83,4 +83,11 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_SOCFPGA + bool "Reset controller driver for SoCFPGA" + depends on DM_RESET && ARCH_SOCFPGA + default y + help + Support for reset controller on SoCFPGA platform. + endmenudrivers/reset/Makefile +1
-0@@ -13,3 +13,4 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.odrivers/reset/reset-socfpga.c new file +36
-0@@ -0,0 +1,111 @@ +/* +* Socfpga Reset Controller Driver +* +* Copyright 2014 Steffen Trumtrar <[email protected]> +* +* based on +* Allwinner SoCs Reset Controller driver +* +* Copyright 2013 Maxime Ripard +* +* Maxime Ripard <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <dm/of_access.h> +#include <reset-uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 + +struct socfpga_reset_data { +void __iomem *membase; +}; + +static int socfpga_reset_assert (struct reset_ctl *reset_ctl) +{ +struct socfpga_reset_data *data =dev_get_priv (reset_ctl->dev); +int id = reset_ctl->id; +int reg_width =sizeof (u32); +int bank = id / (reg_width *BITS_PER_BYTE );Quoted 9 lines
drivers/reset/reset-socfpga.c line 42
Quoted 6 lines
drivers/reset/reset-socfpga.c new file +6
-0+int offset = id % (reg_width *BITS_PER_BYTE ); +unsigned long flags; +u32 reg; + + reg =readl (data->membase + (bank *BANK_INCREMENT )); +writel (reg |BIT (offset), data->membase + (bank *BANK_INCREMENT ));
setbits_le32()?Ok..
Quoted 9 lines
Quoted 9 lines
drivers/reset/reset-socfpga.c new file +9
-0+return 0 ; +} + +static int socfpga_reset_deassert (struct reset_ctl *reset_ctl) +{ +struct socfpga_reset_data *data =dev_get_priv (reset_ctl->dev); +int id = reset_ctl->id; +int reg_width =sizeof (u32); +int bank = id / (reg_width *BITS_PER_BYTE );Quoted 9 lines
drivers/reset/reset-socfpga.c line 57
Quoted 6 lines
drivers/reset/reset-socfpga.c new file +6
-0+int offset = id % (reg_width *BITS_PER_BYTE ); +unsigned long flags; +u32 reg; + + reg =readl (data->membase + (bank *BANK_INCREMENT )); +writel (reg & ~BIT (offset), data->membase + (bank *BANK_INCREMENT ));
clrbits_le32()?Ok..
Quoted 2 lines
[...]
Quoted 8 lines
Quoted 4 lines
What I do not see is any user of this code, nor any conversion of existing systems to use this code. Is that expected to happen ? I do not want to see dead code piling up in U-Boot.
I have a patchset that tested this code, the i2c support in SoCFPGA was converted to DM, and uses this reset framework. Should I send that along with this patch in v2?
Yes please, otherwise this will be just another dead code.
Signature · 2 lines
Best regards, Marek Vasut
PATCH 1/1 reset: socfpga: add reset driver for SoCFPGA platform
On 04/03/2018 09:07 AM, Marek Vasut wrote:
[...]
Quoted 8 lines
Quoted 5 lines
I have a patchset that tested this code, the i2c support in SoCFPGA was converted to DM, and uses this reset framework. Should I send that along with this patch in v2?
Yes please, otherwise this will be just another dead code.
Ok will do! A question: ideally I'd like to have the Stratix10 SPL use the reset manager framework, so I'd not have to add a another platform specific reset_manager_s10. Would that be possible? I think it is, but wanted to confirm.
Thanks,
Dinh
PATCH 1/1 reset: socfpga: add reset driver for SoCFPGA platform
Quoted 11 lines · Dinh Nguyen
On 04/03/2018 09:07 AM, Marek Vasut wrote:
[...]
Quoted 6 lines
Quoted 5 lines
I have a patchset that tested this code, the i2c support in SoCFPGA was converted to DM, and uses this reset framework. Should I send that along with this patch in v2?
Quoted 5 lines
Quoted 2 lines
Yes please, otherwise this will be just another dead code.
Ok will do! A question: ideally I'd like to have the Stratix10 SPL use the reset manager framework,
Awesome
Quoted 3 lines
so I'd not have to add a another platform
specificreset_manager_s10. Would that be possible? I think it is, but wanted to confirm.
I think so, the reset handling on socfpga looks trivial.
Signature · 2 lines
Best regards, Marek Vasut