mtd: spi-nor: Add Micron MT25QU02 support
Subsystems (2)
PATCH 1/1 mtd: spi-nor: Add Micron MT25QU02 support
From: Thor Thayer <[email protected]>
Add support for a new Micron 2Gb Flash memory part. Datasheet is available: mt25q_qlkt_l_02g_cbb_0.pdf
Testing was done on a Stratix10 SoCFPGA Development Kit.
--- drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+)
drivers/mtd/spi-nor/spi-nor.c +1 -0
@@ -1087,6 +1087,7 @@ static const struct flash_info spi_nor_ids[] = { { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },/* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
Signature · 1 line
2.7.4
Quoted 11 lines · On 04/05/2018 09:12 PM, [email protected] wrote:
From: Thor Thayer <[email protected]>
Add support for a new Micron 2Gb Flash memory part. Datasheet is available: mt25q_qlkt_l_02g_cbb_0.pdf
Testing was done on a Stratix10 SoCFPGA Development Kit.
Reported-by Sujith Chidurala <[email protected]>Tested-by Paul Kim <[email protected]>Signed-off-by Thor Thayer <[email protected]>---
Do we need this or can this be recognized as a SFDP flash ?
Signature · 2 lines
Best regards, Marek Vasut
Hi Marek,
Quoted 6 lines · Marek Vasut
Quoted 5 lines · On 04/05/2018 09:12 PM, [email protected] wrote:
From: Thor Thayer <[email protected]>
Add support for a new Micron 2Gb Flash memory part. Datasheet is available: mt25q_qlkt_l_02g_cbb_0.pdf
Quoted 9 lines
Quoted 6 lines
Testing was done on a Stratix10 SoCFPGA Development Kit.
Reported-by Sujith Chidurala <[email protected]>Tested-by Paul Kim <[email protected]>Signed-off-by Thor Thayer <[email protected]>---
Do we need this or can this be recognized as a SFDP flash ?
The error is
"cadence-qspi ff8d2000.spi: unrecognized JEDEC id bytes: 20, bb, 22" which is fixed with this table addition. Is there a better way to handle this?
Thanks for reviewing and the reply.
Thor
Marek Vasut
Acked-byQuoted 16 lines · Thor Thayer
Hi Marek,
Quoted 13 lines · Marek Vasut
Quoted 11 lines · On 04/05/2018 09:12 PM, [email protected] wrote:
From: Thor Thayer <[email protected]>
Add support for a new Micron 2Gb Flash memory part. Datasheet is available: mt25q_qlkt_l_02g_cbb_0.pdf
Testing was done on a Stratix10 SoCFPGA Development Kit.
Reported-by Sujith Chidurala <[email protected]>Tested-by Paul Kim <[email protected]>Signed-off-by Thor Thayer <[email protected]>---
Quoted 6 lines
Quoted 2 lines
Do we need this or can this be recognized as a SFDP flash ?
The error is
"cadence-qspi ff8d2000.spi: unrecognized JEDEC id bytes: 20, bb, 22" which is fixed with this table addition. Is there a better way to handle this?
Seems like even with the SFDP parsing in place, we still need to track the supported IDs, oh well.
Signature · 2 lines
Best regards, Marek Vasut
Boris Brezillon
AppliedQuoted 10 lines · On Thu, 5 Apr 2018 14:12:49 -0500 [email protected] wrote:
From: Thor Thayer <[email protected]>
Add support for a new Micron 2Gb Flash memory part. Datasheet is available: mt25q_qlkt_l_02g_cbb_0.pdf
Testing was done on a Stratix10 SoCFPGA Development Kit.
Reported-by Sujith Chidurala <[email protected]>Tested-by Paul Kim <[email protected]>Signed-off-by Thor Thayer <[email protected]>
Applied to spi-nor/next.
Thanks,
Boris
Quoted 16 lines
--- drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+)drivers/mtd/spi-nor/spi-nor.c +1
-0@@ -1087,6 +1087,7 @@ static const struct flash_info spi_nor_ids[] = { { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },/* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },