drm/i915/dp: Send DPCD ON for MST before phy_up
Subsystems (3)
PATCH v4 1/1 drm/i915/dp: Send DPCD ON for MST before phy_up
When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial power_up_phy() to start timing out. This would only be observed in the last action before the sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought this might be an issue with us accidentally shutting off the aux block when putting the sink into D3, but since the DP spec mandates that sinks must wake up within 1ms while we have 100ms to respond to an ESI irq, this didn't really add up. Turns out that the problem is more subtle then that:
It turns out that the timeout is from us not enabling DPMS on the MST hub before actually trying to initiate sideband communications. This would cause the first sideband communication (power_up_phy()), to start timing out because the sink wasn't ready to respond. Afterwards, we would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in intel_ddi_pre_enable_dp(), which would actually result in waking up the sink so that sideband requests would work again.
Since DPMS is what lets us actually bring the hub up into a state where sideband communications become functional again, we just need to make sure to enable DPMS on the display before attempting to perform sideband communications.
Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala
--- drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++- 2 files changed, 13 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_ddi.c +6 -2
@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,intel_prepare_dp_ddi_buffers (encoder, crtc_state);intel_ddi_init_dp_buf_reg (encoder); -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON );intel_dp_start_link_train (intel_dp);if (port !=PORT_A ||INTEL_GEN (dev_priv) >=9 )intel_dp_stop_link_train (intel_dp);
@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev);struct intel_digital_port *dig_port =enc_to_dig_port (&encoder->base);struct intel_dp *intel_dp = &dig_port->dp; +bool is_mst =intel_crtc_has_type (old_crtc_state, +INTEL_OUTPUT_DP_MST );/* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. */ -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF );intel_disable_ddi_buf (encoder);
drivers/gpu/drm/i915/intel_dp_mst.c +7 -1
@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dp->active_mst_links--; intel_mst->connector =NULL ; -if (intel_dp->active_mst_links ==0 ) +if (intel_dp->active_mst_links ==0 ) { +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); intel_dig_port->base.post_disable (&intel_dig_port->base, old_crtc_state,NULL ); + }DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); }
@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); +if (intel_dp->active_mst_links ==0 ) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +drm_dp_send_power_updown_phy (&intel_dp->mst_mgr, connector->port, true); +if (intel_dp->active_mst_links ==0 ) intel_dig_port->base.pre_enable (&intel_dig_port->base, pipe_config,NULL );
Signature · 1 line
2.14.3
Quoted 18 lines · Lyude Paul
When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial
power_up_phy()to start timing out. This would only be observed in the last action before the sink went into D3 mode wasintel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought this might be an issue with us accidentally shutting off the aux block when putting the sink into D3, but since the DP spec mandates that sinks must wake up within 1ms while we have 100ms to respond to an ESI irq, this didn't really add up. Turns out that the problem is more subtle then that:It turns out that the timeout is from us not enabling DPMS on the MST hub before actually trying to initiate sideband communications. This would cause the first sideband communication (
power_up_phy()), to start timing out because the sink wasn't ready to respond. Afterwards, we would callintel_dp_sink_dpms(DRM_MODE_DPMS_ON)inintel_ddi_pre_enable_dp(), which would actually result in waking up the sink so that sideband requests would work again.
Quoted 5 lines
Since DPMS is what lets us actually bring the hub up into a state where sideband communications become functional again, we just need to make sure to enable DPMS on the display before attempting to perform sideband communications.
Matches my understanding of the problem
It's better to get an ack from Ville considering I was okay with the D3_AUX_ON solution too.
Quoted 82 lines
Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Moveintel_dp_sink_dpms()for MST intointel_dp_post_disable_mst()to keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check againstis_mst, notintel_dp->is_mst- dhnkrn/vsyrjalaSigned-off-by Lyude Paul <[email protected]>Cc Dhinakaran Pandiyan <[email protected]>Cc Ville Syrjälä <[email protected]>Cc Laura Abbott <[email protected]>Fixes ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")--- drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++- 2 files changed, 13 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/intel_ddi.c +6
-2@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,intel_prepare_dp_ddi_buffers (encoder, crtc_state);intel_ddi_init_dp_buf_reg (encoder); -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON );intel_dp_start_link_train (intel_dp);if (port !=PORT_A ||INTEL_GEN (dev_priv) >=9 )intel_dp_stop_link_train (intel_dp);@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev);struct intel_digital_port *dig_port =enc_to_dig_port (&encoder->base);struct intel_dp *intel_dp = &dig_port->dp; +bool is_mst =intel_crtc_has_type (old_crtc_state, +INTEL_OUTPUT_DP_MST );/* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. */ -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF );intel_disable_ddi_buf (encoder);drivers/gpu/drm/i915/intel_dp_mst.c +7
-1@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dp->active_mst_links--; intel_mst->connector =NULL ; -if (intel_dp->active_mst_links ==0 ) +if (intel_dp->active_mst_links ==0 ) { +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); intel_dig_port->base.post_disable (&intel_dig_port->base, old_crtc_state,NULL ); + }DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); }@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); +if (intel_dp->active_mst_links ==0 ) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +drm_dp_send_power_updown_phy (&intel_dp->mst_mgr, connector->port, true); +if (intel_dp->active_mst_links ==0 ) intel_dig_port->base.pre_enable (&intel_dig_port->base, pipe_config,NULL );
Ville Syrjälä
Reviewed-byQuoted 28 lines · Dhinakaran Pandiyan
Quoted 18 lines · Lyude Paul
When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial
power_up_phy()to start timing out. This would only be observed in the last action before the sink went into D3 mode wasintel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought this might be an issue with us accidentally shutting off the aux block when putting the sink into D3, but since the DP spec mandates that sinks must wake up within 1ms while we have 100ms to respond to an ESI irq, this didn't really add up. Turns out that the problem is more subtle then that:It turns out that the timeout is from us not enabling DPMS on the MST hub before actually trying to initiate sideband communications. This would cause the first sideband communication (
power_up_phy()), to start timing out because the sink wasn't ready to respond. Afterwards, we would callintel_dp_sink_dpms(DRM_MODE_DPMS_ON)inintel_ddi_pre_enable_dp(), which would actually result in waking up the sink so that sideband requests would work again.Quoted 5 lines
Since DPMS is what lets us actually bring the hub up into a state where sideband communications become functional again, we just need to make sure to enable DPMS on the display before attempting to perform sideband communications.
Quoted 6 lines
Matches my understanding of the problem
Reviewed-by Dhinakaran Pandiyan <[email protected]>It's better to get an ack from Ville considering I was okay with the
D3_AUX_ONsolution too.
lgtm
Quoted 84 lines
Quoted 84 lines
Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Moveintel_dp_sink_dpms()for MST intointel_dp_post_disable_mst()to keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check againstis_mst, notintel_dp->is_mst- dhnkrn/vsyrjalaSigned-off-by Lyude Paul <[email protected]>Cc Dhinakaran Pandiyan <[email protected]>Cc Ville Syrjälä <[email protected]>Cc Laura Abbott <[email protected]>Fixes ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")--- drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++- 2 files changed, 13 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/intel_ddi.c +6
-2@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,intel_prepare_dp_ddi_buffers (encoder, crtc_state);intel_ddi_init_dp_buf_reg (encoder); -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON );intel_dp_start_link_train (intel_dp);if (port !=PORT_A ||INTEL_GEN (dev_priv) >=9 )intel_dp_stop_link_train (intel_dp);@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev);struct intel_digital_port *dig_port =enc_to_dig_port (&encoder->base);struct intel_dp *intel_dp = &dig_port->dp; +bool is_mst =intel_crtc_has_type (old_crtc_state, +INTEL_OUTPUT_DP_MST );/* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. */ -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF );intel_disable_ddi_buf (encoder);drivers/gpu/drm/i915/intel_dp_mst.c +7
-1@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dp->active_mst_links--; intel_mst->connector =NULL ; -if (intel_dp->active_mst_links ==0 ) +if (intel_dp->active_mst_links ==0 ) { +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); intel_dig_port->base.post_disable (&intel_dig_port->base, old_crtc_state,NULL ); + }DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); }@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); +if (intel_dp->active_mst_links ==0 ) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +drm_dp_send_power_updown_phy (&intel_dp->mst_mgr, connector->port, true); +if (intel_dp->active_mst_links ==0 ) intel_dig_port->base.pre_enable (&intel_dig_port->base, pipe_config,NULL );
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 23 lines · Lyude Paul
When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial
power_up_phy()to start timing out. This would only be observed in the last action before the sink went into D3 mode wasintel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought this might be an issue with us accidentally shutting off the aux block when putting the sink into D3, but since the DP spec mandates that sinks must wake up within 1ms while we have 100ms to respond to an ESI irq, this didn't really add up. Turns out that the problem is more subtle then that:It turns out that the timeout is from us not enabling DPMS on the MST hub before actually trying to initiate sideband communications. This would cause the first sideband communication (
power_up_phy()), to start timing out because the sink wasn't ready to respond. Afterwards, we would callintel_dp_sink_dpms(DRM_MODE_DPMS_ON)inintel_ddi_pre_enable_dp(), which would actually result in waking up the sink so that sideband requests would work again.Since DPMS is what lets us actually bring the hub up into a state where sideband communications become functional again, we just need to make sure to enable DPMS on the display before attempting to perform sideband communications.
Quoted 11 lines
Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Moveintel_dp_sink_dpms()for MST intointel_dp_post_disable_mst()to keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check againstis_mst, notintel_dp->is_mst- dhnkrn/vsyrjala
For the booting docked with lid down case:
Quoted 62 lines
Signed-off-by Lyude Paul <[email protected]>Cc Dhinakaran Pandiyan <[email protected]>Cc Ville Syrjälä <[email protected]>Cc Laura Abbott <[email protected]>Fixes ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")--- drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++- 2 files changed, 13 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/intel_ddi.c +6
-2@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,intel_prepare_dp_ddi_buffers (encoder, crtc_state);intel_ddi_init_dp_buf_reg (encoder); -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON );intel_dp_start_link_train (intel_dp);if (port !=PORT_A ||INTEL_GEN (dev_priv) >=9 )intel_dp_stop_link_train (intel_dp);@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev);struct intel_digital_port *dig_port =enc_to_dig_port (&encoder->base);struct intel_dp *intel_dp = &dig_port->dp; +bool is_mst =intel_crtc_has_type (old_crtc_state, +INTEL_OUTPUT_DP_MST );/* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. */ -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF );intel_disable_ddi_buf (encoder);drivers/gpu/drm/i915/intel_dp_mst.c +3
-1@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dp->active_mst_links--; intel_mst->connector =NULL ; -if (intel_dp->active_mst_links ==0 ) +if (intel_dp->active_mst_links ==0 ) { +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); intel_dig_port->base.post_disable (&intel_dig_port->base, old_crtc_state,NULL ); + }DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); }@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
drivers/gpu/drm/i915/intel_dp_mst.c static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, · line 235
Quoted 10 lines
drivers/gpu/drm/i915/intel_dp_mst.c +4
-0DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); +if (intel_dp->active_mst_links ==0 ) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +drm_dp_send_power_updown_phy (&intel_dp->mst_mgr, connector->port, true); +if (intel_dp->active_mst_links ==0 ) intel_dig_port->base.pre_enable (&intel_dig_port->base, pipe_config,NULL );
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 36 lines · Laura Abbott
Quoted 23 lines · Lyude Paul
When doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial
power_up_phy()to start timing out. This would only be observed in the last action before the sink went into D3 mode wasintel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought this might be an issue with us accidentally shutting off the aux block when putting the sink into D3, but since the DP spec mandates that sinks must wake up within 1ms while we have 100ms to respond to an ESI irq, this didn't really add up. Turns out that the problem is more subtle then that:It turns out that the timeout is from us not enabling DPMS on the MST hub before actually trying to initiate sideband communications. This would cause the first sideband communication (
power_up_phy()), to start timing out because the sink wasn't ready to respond. Afterwards, we would callintel_dp_sink_dpms(DRM_MODE_DPMS_ON)inintel_ddi_pre_enable_dp(), which would actually result in waking up the sink so that sideband requests would work again.Since DPMS is what lets us actually bring the hub up into a state where sideband communications become functional again, we just need to make sure to enable DPMS on the display before attempting to perform sideband communications.
Quoted 11 lines
Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Moveintel_dp_sink_dpms()for MST intointel_dp_post_disable_mst()to keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check againstis_mst, notintel_dp->is_mst- dhnkrn/vsyrjala
Quoted 3 lines
For the booting docked with lid down case:
Tested-by Laura Abbott <[email protected]>
Awesome, will push once the CI run finishes. Thanks for the help!
Quoted 84 lines
Quoted 82 lines
Signed-off-by Lyude Paul <[email protected]>Cc Dhinakaran Pandiyan <[email protected]>Cc Ville Syrjälä <[email protected]>Cc Laura Abbott <[email protected]>Fixes ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MSThub.")
--- drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++- 2 files changed, 13 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/intel_ddi.c +2
-1@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(structintel_encoder *encoder,intel_prepare_dp_ddi_buffers (encoder ,crtc_state );intel_ddi_init_dp_buf_reg (encoder); -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON );intel_dp_start_link_train (intel_dp);if (port !=PORT_A ||INTEL_GEN (dev_priv) >=9 )intel_dp_stop_link_train(intel_dp);drivers/gpu/drm/i915/intel_ddi.c +4
-1@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(structintel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);struct intel_digital_port *dig_port =enc_to_dig_port (&encoder- >base);struct intel_dp *intel_dp = &dig_port->dp; +bool is_mst =intel_crtc_has_type (old_crtc_state, +INTEL_OUTPUT_DP_MST );/* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. */ -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF );intel_disable_ddi_buf(encoder);drivers/gpu/drm/i915/intel_dp_mst.c +3
-1@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dp->active_mst_links--; intel_mst->connector =NULL ; -if (intel_dp->active_mst_links ==0 ) +if (intel_dp->active_mst_links ==0 ) { +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); intel_dig_port->base.post_disable (&intel_dig_port->base, old_crtc_state,NULL ); + }DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links);}drivers/gpu/drm/i915/intel_dp_mst.c +4
-0@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); +if (intel_dp->active_mst_links ==0 ) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +drm_dp_send_power_updown_phy (&intel_dp->mst_mgr, connector- >port, true); +if (intel_dp->active_mst_links ==0 )intel_dig_port->base.pre_enable(&intel_dig_port->base,
pipe_config, NULL);
Signature · 2 lines
Cheers, Lyude Paul
Patchwork
CI✓ Fi.CI.BAT: success for drm/i915/dp: Send DPCD ON for MST before phy_up
In reply to Lyude Paul== Series Details ==
== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up
URL : https://patchwork.freedesktop.org/series/41297/
State : success
== Summary ==
Series 41297v1 drm/i915/dp: Send DPCD ON for MST before phy_up
https://patchwork.freedesktop.org/api/1.0/series/41297/revisions/1/mbox/
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (fi-skl-6700k2) fdo#103191fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:430s fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:447s fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:380s fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:538s fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:300s fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:514s fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:515s fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:520s fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:510s fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:412s fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:559s fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:513s fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:582s fi-elk-e7500 total:285 pass:226 dwarn:0 dfail:0 fail:0 skip:59 time:423s fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:318s fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:488s fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:403s fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:424s fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:476s fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:432s fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:475s fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:465s fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:512s fi-pnv-d510 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:646s fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:442s fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:532s fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:503s fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:506s fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:431s fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:449s fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:397s
e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC integration manifest 34a2da81056d drm/i915/dp: Send DPCD ON for MST before phy_up
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8628/issues.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✗ Fi.CI.IGT: failure for drm/i915/dp: Send DPCD ON for MST before phy_up
In reply to Lyude Paul== Series Details ==
== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up
URL : https://patchwork.freedesktop.org/series/41297/
State : failure
== Summary ==
---- Possible new issues:
Test gem_pwrite:
Subgroup big-gtt-backwards:
pass -> SKIP (shard-apl)
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail -> PASS (shard-snb)
Test kms_chv_cursor_fail:
Subgroup pipe-a-256x256-left-edge:
pass -> FAIL (shard-snb)
Subgroup pipe-b-256x256-right-edge:
pass -> FAIL (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail -> PASS (shard-snb)
Subgroup cursor-256x256-offscreen:
fail -> PASS (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail -> PASS (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail -> PASS (shard-snb)
Subgroup fbc-2p-scndscrn-indfb-msflip-blt:
skip -> FAIL (shard-snb)
Subgroup fbc-modesetfrombusy:
fail -> PASS (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
skip -> FAIL (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-rgb101010-draw-pwrite:
skip -> FAIL (shard-snb)
Subgroup psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
skip -> FAIL (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
skip -> FAIL (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail -> SKIP (shard-snb)
Subgroup psr-2p-primscrn-pri-shrfb-draw-blt:
skip -> FAIL (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail -> SKIP (shard-snb)
Test kms_mmap_write_crc:
fail -> PASS (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail -> PASS (shard-snb)---- Known issues:
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
fail -> PASS (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail -> SKIP (shard-snb) fdo#103167 +1
Test kms_sysfs_edid_timing:
warn -> PASS (shard-apl) fdo#100047
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-apl total:2680 pass:1835 dwarn:1 dfail:0 fail:7 skip:837 time:12615s shard-hsw total:2680 pass:1786 dwarn:1 dfail:0 fail:1 skip:891 time:11464s shard-snb total:2680 pass:1375 dwarn:1 dfail:0 fail:12 skip:1292 time:6944s
Blacklisted hosts:
shard-kbl total:2680 pass:1950 dwarn:10 dfail:0 fail:8 skip:712 time:9043s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8628/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH v5 1/1 drm/i915/dp: Send DPCD ON for MST before phy_up
In reply to Lyude PaulWhen doing a modeset where the sink is transitioning from D3 to D0 , it would sometimes be possible for the initial power_up_phy() to start timing out. This would only be observed in the last action before the sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We originally thought this might be an issue with us accidentally shutting off the aux block when putting the sink into D3, but since the DP spec mandates that sinks must wake up within 1ms while we have 100ms to respond to an ESI irq, this didn't really add up. Turns out that the problem is more subtle then that:
It turns out that the timeout is from us not enabling DPMS on the MST hub before actually trying to initiate sideband communications. This would cause the first sideband communication (power_up_phy()), to start timing out because the sink wasn't ready to respond. Afterwards, we would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in intel_ddi_pre_enable_dp(), which would actually result in waking up the sink so that sideband requests would work again.
Since DPMS is what lets us actually bring the hub up into a state where sideband communications become functional again, we just need to make sure to enable DPMS on the display before attempting to perform sideband communications.
Changes since v1:
- Remove comment above if (!intel_dp->is_mst) - vsryjala
- Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to keep enable/disable paths symmetrical
- Improve commit message - dhnkrn
Changes since v2:
- Only send DPMS off when we're disabling the last sink, and only send DPMS on when we're enabling the first sink - dhnkrn
Changes since v3:
- Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala
---
No actual changes other than t-b and r-bs. Resending because I don't have access to the "test latest revision again" button and I'm very much sure these CI results are bogus.
drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++- 2 files changed, 13 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/intel_ddi.c +6 -2
@@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,intel_prepare_dp_ddi_buffers (encoder, crtc_state);intel_ddi_init_dp_buf_reg (encoder); -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON );intel_dp_start_link_train (intel_dp);if (port !=PORT_A ||INTEL_GEN (dev_priv) >=9 )intel_dp_stop_link_train (intel_dp);
@@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,struct drm_i915_private *dev_priv =to_i915 (encoder->base.dev);struct intel_digital_port *dig_port =enc_to_dig_port (&encoder->base);struct intel_dp *intel_dp = &dig_port->dp; +bool is_mst =intel_crtc_has_type (old_crtc_state, +INTEL_OUTPUT_DP_MST );/* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. */ -intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); +if (!is_mst) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF );intel_disable_ddi_buf (encoder);
drivers/gpu/drm/i915/intel_dp_mst.c +7 -1
@@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dp->active_mst_links--; intel_mst->connector =NULL ; -if (intel_dp->active_mst_links ==0 ) +if (intel_dp->active_mst_links ==0 ) { +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_OFF ); intel_dig_port->base.post_disable (&intel_dig_port->base, old_crtc_state,NULL ); + }DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); }
@@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,DRM_DEBUG_KMS ("active links %d\n" , intel_dp->active_mst_links); +if (intel_dp->active_mst_links ==0 ) +intel_dp_sink_dpms (intel_dp,DRM_MODE_DPMS_ON ); +drm_dp_send_power_updown_phy (&intel_dp->mst_mgr, connector->port, true); +if (intel_dp->active_mst_links ==0 ) intel_dig_port->base.pre_enable (&intel_dig_port->base, pipe_config,NULL );
Signature · 6 lines
2.14.3 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.BAT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
In reply to Lyude Paul== Series Details ==
== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL : https://patchwork.freedesktop.org/series/41297/
State : success
== Summary ==
Series 41297v2 drm/i915/dp: Send DPCD ON for MST before phy_up
https://patchwork.freedesktop.org/api/1.0/series/41297/revisions/2/mbox/
---- Known issues:
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (fi-skl-6770hq) fdo#100368
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (fi-skl-6700k2) fdo#103191
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-guc) fdo#104108fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:432s fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:442s fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:381s fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:541s fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:297s fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:513s fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:517s fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:510s fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:412s fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:562s fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:513s fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:585s fi-elk-e7500 total:285 pass:226 dwarn:0 dfail:0 fail:0 skip:59 time:425s fi-gdg-551 total:285 pass:177 dwarn:0 dfail:0 fail:0 skip:108 time:314s fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:544s fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:488s fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:407s fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:420s fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:470s fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:432s fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:471s fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:464s fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:510s fi-pnv-d510 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:665s fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:438s fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:532s fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:502s fi-skl-6770hq total:285 pass:264 dwarn:0 dfail:0 fail:1 skip:20 time:508s fi-skl-guc total:285 pass:256 dwarn:0 dfail:0 fail:1 skip:28 time:429s fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:441s fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:582s fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:399s
e023242a3ebab3e7a4e5d7647d7b08c0d2be5d4c drm-tip: 2018y-04m-06d-19h-07m-27s UTC integration manifest 7c0d355a8411 drm/i915/dp: Send DPCD ON for MST before phy_up
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8633/issues.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Patchwork
CI✓ Fi.CI.IGT: success for drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
In reply to Lyude Paul== Series Details ==
== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL : https://patchwork.freedesktop.org/series/41297/
State : success
== Summary ==
---- Possible new issues:
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail -> PASS (shard-snb)
Test kms_cursor_crc:
Subgroup cursor-256x256-dpms:
fail -> PASS (shard-snb)
Subgroup cursor-256x256-offscreen:
fail -> PASS (shard-snb)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-pwrite:
fail -> PASS (shard-snb)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
fail -> PASS (shard-snb)
Subgroup fbc-modesetfrombusy:
fail -> PASS (shard-snb)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-render:
fail -> SKIP (shard-snb)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
fail -> SKIP (shard-snb)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
fail -> SKIP (shard-snb)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
fail -> SKIP (shard-snb)
Test kms_mmap_write_crc:
fail -> PASS (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy-hang:
fail -> PASS (shard-snb)---- Known issues:
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass -> FAIL (shard-hsw) fdo#102887
Subgroup plain-flip-fb-recreate:
fail -> PASS (shard-hsw) fdo#100368 +3
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
pass -> FAIL (shard-snb) fdo#105798
Subgroup fbc-2p-primscrn-shrfb-pgflip-blt:
fail -> SKIP (shard-snb) fdo#103167
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252 +1fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#105798 https://bugs.freedesktop.org/show_bug.cgi?id=105798
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-apl total:2680 pass:1835 dwarn:1 dfail:0 fail:7 skip:836 time:12676s shard-hsw total:2680 pass:1782 dwarn:1 dfail:0 fail:5 skip:891 time:11388s shard-snb total:2680 pass:1376 dwarn:1 dfail:0 fail:4 skip:1299 time:6935s
Blacklisted hosts:
shard-kbl total:2680 pass:1962 dwarn:1 dfail:0 fail:8 skip:709 time:9262s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8633/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.").
The bot has also determined it's probably a bug fixing patch. (score: 95.4452)
The bot has tested the following trees: v4.16.1, v4.15.16.
v4.16.1: Build OK!
v4.15.16: Failed to apply! Possible dependencies:
1939ba51fd05 ("drm/i915: Pass a crtc state to ddi post_disable from MST code")