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arm: npcm: enable L2 cache in NPCM7xx architecture

PATCH In review Tomer Maimon 2 participants 4 messages Apr 8, 2018 – Apr 11, 2018

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/nuvoton npcm architecture
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Tomer Maimon

author maintainer
#0 lore raw

cover arm: npcm: enable L2 cache in NPCM7xx architecture

This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure.

At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module.
- https://www.spinics.net/lists/arm-kernel/msg613212.html

After checking again the L2 cache use in the NPCM7xx,
the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree:
https://patchwork.kernel.org/patch/10063497/

L2 cache flag mask allowed all the flag option.

Tomer Maimon (1):
arm: npcm: enable L2 cache in NPCM7xx architecture

 arch/arm/mach-npcm/npcm7xx.c | 2 ++
 1 file changed, 2 insertions(+)
Signature · 1 line
2.14.1
author maintainer
#1 lore raw

PATCH 1/1 arm: npcm: enable L2 cache in NPCM7xx architecture

Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure.

Signed-off-by Tomer Maimon <[email protected]>
---
 arch/arm/mach-npcm/npcm7xx.c | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/mach-npcm/npcm7xx.c +2 -0
index 5f7cd88103ef..c5f77d854c4f 100644
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
 DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
 	.atag_offset	= 0x100,
 	.dt_compat	= npcm7xx_dt_match,
+	.l2c_aux_val	= 0x0,
+	.l2c_aux_mask	= ~0x0,
 MACHINE_END
Signature · 1 line
2.14.1
#2 lore raw
In reply to Tomer Maimon
Quoted 7 lines · Tomer Maimon

This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure.

At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module.
- https://www.spinics.net/lists/arm-kernel/msg613212.html

Quoted 6 lines

After checking again the L2 cache use in the NPCM7xx,
the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree:
https://patchwork.kernel.org/patch/10063497/

L2 cache flag mask allowed all the flag option.

I've applied the patch to my fixes branch now, but took your description above instead of the two-line text that you had in the patch itself. I liked the longer
text much better.

Arnd

author maintainer
#3 lore raw
Quoted 15 lines · Arnd Bergmann
Quoted 7 lines · Tomer Maimon

This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure.

At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module.
- https://www.spinics.net/lists/arm-kernel/msg613212.html

Quoted 6 lines

After checking again the L2 cache use in the NPCM7xx,
the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree:
https://patchwork.kernel.org/patch/10063497/

L2 cache flag mask allowed all the flag option.

Quoted 8 lines

I've applied the patch to my fixes branch now, but took your description above
instead of the two-line text that you had in the patch itself. I liked the longer
text much better.

Arnd

O.K.

Thanks a lot!