Patch "clk: divider: fix incorrect usage of container_of" has been added to the 4.14-stable tree

PATCH [email protected] 1 participant 1 message Apr 9, 2018

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2018-04-09 12:04 UTC #0 lore raw

This is a note to let you know that I've just added the patch titled

clk: divider: fix incorrect usage of container_of

to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
clk-divider-fix-incorrect-usage-of-container_of.patch
and it can be found in the queue-4.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From foo@baz Mon Apr 9 13:58:16 CEST 2018

From: Jerome Brunet <[email protected]>
Date: Thu, 21 Dec 2017 17:30:54 +0100
Subject: clk: divider: fix incorrect usage of container_of

From: Jerome Brunet <[email protected]>

[ Upstream commit 12a26c298d2a8b1cab498533fa65198e49e3afd3 ]

divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider'

At the following line:

Quoted 1 line

div = _get_div(table, val, flags, divider->width);

in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider'

Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before

Fixes afe76c8fd030 ("clk: allow a clk divider with max divisor when zero")

Signed-off-by Jerome Brunet <[email protected]>

Acked-by Alexandre Belloni <[email protected]>

Acked-by Sylvain Lemieux <[email protected]>

Signed-off-by Stephen Boyd <[email protected]>

Signed-off-by Sasha Levin <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 drivers/clk/clk-divider.c                  |    7 +++----
 drivers/clk/hisilicon/clkdivider-hi6220.c  |    2 +-
 drivers/clk/nxp/clk-lpc32xx.c              |    2 +-
 drivers/clk/qcom/clk-regmap-divider.c      |    2 +-
 drivers/clk/sunxi-ng/ccu_div.c             |    2 +-
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c |    2 +-
 drivers/rtc/rtc-ac100.c                    |    6 ++++--
 include/linux/clk-provider.h               |    2 +-
 8 files changed, 13 insertions(+), 12 deletions(-)

drivers/clk/clk-divider.c +3 -4

@@ -118,12 +118,11 @@ static unsigned int _get_val(const struc
 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
 				  unsigned int val,
 				  const struct clk_div_table *table,
-				  unsigned long flags)
+				  unsigned long flags, unsigned long width)
 {
-	struct clk_divider *divider = to_clk_divider(hw);
 	unsigned int div;
 
-	div = _get_div(table, val, flags, divider->width);
+	div = _get_div(table, val, flags, width);
 	if (!div) {
 		WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
 			"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",

@@ -145,7 +144,7 @@ static unsigned long clk_divider_recalc_
 	val &= div_mask(divider->width);
 
 	return divider_recalc_rate(hw, parent_rate, val, divider->table,
-				   divider->flags);
+				   divider->flags, divider->width);
 }
 
 static bool _is_valid_table_div(const struct clk_div_table *table,

drivers/clk/hisilicon/clkdivider-hi6220.c +1 -1

@@ -56,7 +56,7 @@ static unsigned long hi6220_clkdiv_recal
 	val &= div_mask(dclk->width);
 
 	return divider_recalc_rate(hw, parent_rate, val, dclk->table,
-				   CLK_DIVIDER_ROUND_CLOSEST);
+				   CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
 }
 
 static long hi6220_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/nxp/clk-lpc32xx.c +1 -1

@@ -956,7 +956,7 @@ static unsigned long clk_divider_recalc_
 	val &= div_mask(divider->width);
 
 	return divider_recalc_rate(hw, parent_rate, val, divider->table,
-				   divider->flags);
+				   divider->flags, divider->width);
 }
 
 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/qcom/clk-regmap-divider.c +1 -1

@@ -59,7 +59,7 @@ static unsigned long div_recalc_rate(str
 	div &= BIT(divider->width) - 1;
 
 	return divider_recalc_rate(hw, parent_rate, div, NULL,
-				   CLK_DIVIDER_ROUND_CLOSEST);
+				   CLK_DIVIDER_ROUND_CLOSEST, divider->width);
 }
 
 const struct clk_ops clk_regmap_div_ops = {

drivers/clk/sunxi-ng/ccu_div.c +1 -1

@@ -71,7 +71,7 @@ static unsigned long ccu_div_recalc_rate
 						  parent_rate);
 
 	val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
-				  cd->div.flags);
+				  cd->div.flags, cd->div.width);
 
 	if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		val /= cd->fixed_post_div;

drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c +1 -1

@@ -698,7 +698,7 @@ static unsigned long dsi_pll_14nm_postdi
 	val &= div_mask(width);
 
 	return divider_recalc_rate(hw, parent_rate, val, NULL,
-				   postdiv->flags);
+				   postdiv->flags, width);
 }
 
 static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,

drivers/rtc/rtc-ac100.c +4 -2

@@ -137,13 +137,15 @@ static unsigned long ac100_clkout_recalc
 		div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
 			((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
 		prate = divider_recalc_rate(hw, prate, div,
-					    ac100_clkout_prediv, 0);
+					    ac100_clkout_prediv, 0,
+					    AC100_CLKOUT_PRE_DIV_WIDTH);
 	}
 
 	div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
 		(BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
 	return divider_recalc_rate(hw, prate, div, NULL,
-				   CLK_DIVIDER_POWER_OF_TWO);
+				   CLK_DIVIDER_POWER_OF_TWO,
+				   AC100_CLKOUT_DIV_WIDTH);
 }
 
 static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,

include/linux/clk-provider.h +1 -1

@@ -412,7 +412,7 @@ extern const struct clk_ops clk_divider_
 
 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
 		unsigned int val, const struct clk_div_table *table,
-		unsigned long flags);
+		unsigned long flags, unsigned long width);
 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
 			       unsigned long rate, unsigned long *prate,
 			       const struct clk_div_table *table,

Patches currently in stable-queue which might be from [email protected] are

queue-4.14/clk-divider-fix-incorrect-usage-of-container_of.patch queue-4.14/clk-meson-mpll-use-64-bit-maths-in-params_from_rate.patch