Skip to contentSkip to conversation

Add UART support to r8a7743

PATCH New Fabrizio Castro 2 participants 24 messages Mar 5, 2018 – Apr 10, 2018

Subsystems (3)
Device tree bindings TTY layer and serial drivers Arm and arm64 SoC sub-architectures (common parts)
lore
Share & tools
lore

Fabrizio Castro

author
#0 lore raw

cover Add UART support to r8a7743

This series aims at adding UART support to r8a7743 by backporting the relevant patches from upstream.
As per upstream, since two of the serial interfaces live on the camera daughter board, we rework the DT architecture to better accomodate all the possible HW variants.

Finally, in order to get CTS/RTS to work this series backports fixes made by Geert some time ago.

Thanks,
Fabrizio

Biju Das (1):
ARM: dts: iwg20d-q7: Add chosen node

Fabrizio Castro (3):
ARM: dts: iwg20d-q7: Rework DT architecture
ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB
ARM: dts: iwg20d-q7: Add support for ttySC3

Geert Uytterhoeven (11):
serial: sh-sci: Update DT binding documentation for GPIO modem lines
serial: sh-sci: Update DT binding documentation for dedicated RTS/CTS
serial: sh-sci: Always set TIOCM_CTS in .get_mctrl() callback
serial: sh-sci: Add support for GPIO-controlled modem lines
serial: sh-sci: Do not open-code sci_getreg()
serial: sh-sci: Add more Serial Port Register documentation
serial: sh-sci: Add more Serial Port Control/Data Register
documentation
serial: sh-sci: Correct pin initialization on (H)SCIF
serial: sh-sci: Add pin initialization for SCIFA/SCIFB
serial: sh-sci: Fix support for hardware-assisted RTS/CTS
serial: sh-sci: Add DT support for dedicated RTS/CTS

 .../bindings/serial/renesas,sci-serial.txt         |   4 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/iwg20d-q7-common.dtsi            | 127 +++++++++++++++
 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi           |  43 +++++
 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts    |  19 +++
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts            | 100 +-----------
 drivers/tty/serial/Kconfig                         |   1 +
 drivers/tty/serial/sh-sci.c                        | 177 ++++++++++++++++++---
 drivers/tty/serial/sh-sci.h                        |  24 ++-
 9 files changed, 365 insertions(+), 131 deletions(-)
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
 create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH 1/15 serial: sh-sci: Update DT binding documentation for GPIO modem lines

From: Geert Uytterhoeven <[email protected]>

Amend the DT bindings for the Renesas SCI driver to allow describing optional GPIO-controlled modem lines, which can be used where dedicated modem lines are not available.

The property naming is dictated by the Generic Serial DT Bindings.

Signed-off-by Geert Uytterhoeven <[email protected]>
Acked-by Rob Herring <[email protected]>
Cc devicetree at vger.kernel.org
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit 0c529b3fc6c66e618088aa3a998d760d1ad05272)
Signed-off-by Fabrizio Castro <[email protected]>
---
 Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++
 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +2 -0
index cbcfdc0..e0fd7ee 100644
@@ -59,6 +59,8 @@ Optional properties:
   - dmas: Must contain a list of two references to DMA specifiers, one for
 	  transmission, and one for reception.
   - dma-names: Must contain a list of two DMA names, "tx" and "rx".
+  - {cts,dsr,dcd,rng,rts,dtr}-gpios: Specify GPIOs for modem lines, cfr. the
+    generic serial DT bindings in serial.txt.
 
 Example:
 	aliases {
Signature · 1 line
2.7.4
author
#2 lore raw

PATCH 2/15 serial: sh-sci: Update DT binding documentation for dedicated RTS/CTS

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Some Renesas SCIF UARTs have dedicated lines for RTS/CTS hardware flow control. Whether these lines exist depends on SoC and UART instance inside the SoC. Whether these lines can be used for hardware flow control depends on board wiring.

Amend the DT bindings with an optional property to indicate that RTS/CTS hardware flow control lines exist, and can be used as such, according to the Generic Serial DT Bindings.

Signed-off-by Geert Uytterhoeven <[email protected]>
Acked-by Rob Herring <[email protected]>
Cc devicetree at vger.kernel.org
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit b0405dc998e425bbb1f64488b6fda781b627056b)
Signed-off-by Fabrizio Castro <[email protected]>
---
 Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++
 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +2 -0
index e0fd7ee..211f193 100644
@@ -61,6 +61,8 @@ Optional properties:
   - dma-names: Must contain a list of two DMA names, "tx" and "rx".
   - {cts,dsr,dcd,rng,rts,dtr}-gpios: Specify GPIOs for modem lines, cfr. the
     generic serial DT bindings in serial.txt.
+  - uart-has-rtscts: Indicates dedicated lines for RTS/CTS hardware flow
+    control, cfr. the generic serial DT bindings in serial.txt.
 
 Example:
 	aliases {
Signature · 1 line
2.7.4
author
#3 lore raw

PATCH 3/15 serial: sh-sci: Always set TIOCM_CTS in .get_mctrl() callback

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Documentation/serial/driver clearly states:

If the port does not support CTS, DCD or DSR, the driver should indicate that the signal is permanently active.

Hence always set TIOCM_CTS, as we currently don't look at the CTS hardware line state at all.

FWIW, this fixes the transmit path when hardware-assisted flow control is enabled, and userspace enables CRTSCTS.
The receive path is still broken, as RTS is never asserted.

Signed-off-by Geert Uytterhoeven <[email protected]>
Reviewed-by Peter Hurley <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit 71e98e0e2aede08d6e0a0f3d94ea28b591ef4306)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/tty/serial/sh-sci.c +2 -2
index 80d0ffe..5f148f3 100644
@@ -1756,9 +1756,9 @@ static unsigned int sci_get_mctrl(struct uart_port *port)
 {
 	/*
 	 * CTS/RTS is handled in hardware when supported, while nothing
-	 * else is wired up. Keep it simple and simply assert DSR/CAR.
+	 * else is wired up. Keep it simple and simply assert CTS/DSR/CAR.
 	 */
-	return TIOCM_DSR | TIOCM_CAR;
+	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
 }
 
 static void sci_break_ctl(struct uart_port *port, int break_state)
Signature · 1 line
2.7.4
author
#4 lore raw

PATCH 4/15 serial: sh-sci: Add support for GPIO-controlled modem lines

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Enhance the Renesas SCI UART driver to add support for GPIO-controlled modem lines (CTS, DSR, DCD, RNG, RTS, DTR), using the serial_mctrl_gpio helpers.

GPIO-controlled modem lines can be used when dedicated modem lines are not available. Invalid configurations specifying both GPIO RTS/CTS and dedicated RTS/CTS are rejected.

Signed-off-by Geert Uytterhoeven <[email protected]>
Reviewed-by Peter Hurley <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit f907c9ea88355ac9fe065ffbd6acc914408b4232)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/Kconfig  |  1 +
 drivers/tty/serial/sh-sci.c | 46 ++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 46 insertions(+), 1 deletion(-)
drivers/tty/serial/Kconfig +1 -0
index f38beb2..05a2b2c 100644
@@ -731,6 +731,7 @@ config SERIAL_SH_SCI
 	tristate "SuperH SCI(F) serial port support"
 	depends on SUPERH || ARCH_SHMOBILE || H8300 || COMPILE_TEST
 	select SERIAL_CORE
+	select SERIAL_MCTRL_GPIO if GPIOLIB
 
 config SERIAL_SH_SCI_NR_UARTS
 	int "Maximum number of SCI(F) serial ports"
drivers/tty/serial/sh-sci.c +45 -1

102 lines not on this page · raw message

Signature · 1 line
2.7.4
author
#5 lore raw

PATCH 5/15 serial: sh-sci: Do not open-code sci_getreg()

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Replace open-coded variants of sci_getreg() by function calls, and drop intermediate variables where appropriate.

Signed-off-by Geert Uytterhoeven <[email protected]>
Reviewed-by Peter Hurley <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit abbf121fb6dae6657388a32feac346e5e1debdbd)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)
drivers/tty/serial/sh-sci.c +2 -5
index cf91172..f96f44c 100644
@@ -624,7 +624,6 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
 {
 	struct sci_port *s = to_sci_port(port);
-	const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
 
 	/*
 	 * Use port-specific handler if provided.

@@ -638,7 +637,7 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
 	 * For the generic path SCSPTR is necessary. Bail out if that's
 	 * unavailable, too.
 	 */
-	if (!reg->size)
+	if (!sci_getreg(port, SCSPTR)->size)
 		return;
 
 	if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&

@@ -1787,12 +1786,10 @@ static void sci_enable_ms(struct uart_port *port)
 
 static void sci_break_ctl(struct uart_port *port, int break_state)
 {
-	struct sci_port *s = to_sci_port(port);
-	const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
 	unsigned short scscr, scsptr;
 
 	/* check wheter the port has SCSPTR */
-	if (!reg->size) {
+	if (!sci_getreg(port, SCSPTR)->size) {
 		/*
 		 * Not supported by hardware. Most parts couple break and rx
 		 * interrupts together, with break detection always enabled.
Signature · 1 line
2.7.4
author
#6 lore raw

PATCH 6/15 serial: sh-sci: Add more Serial Port Register documentation

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Improve documentation for the (H)SCIF Serial Port Register:
- Make it clear the RTS and CTS lines are active-low,
- Document the bits related to the serial port's clock pin.

Signed-off-by Geert Uytterhoeven <[email protected]>
Reviewed-by Peter Hurley <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit ef5e90e8ccb7b715c0a1509339f730b2bf9698a2)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)
drivers/tty/serial/sh-sci.h +6 -4
index bf69bbd..fa560c0 100644
@@ -91,10 +91,12 @@ enum {
 #define SCLSR_ORER	BIT(0)	/* Overrun Error */
 
 /* SCSPTR (Serial Port Register), optional */
-#define SCSPTR_RTSIO	BIT(7)	/* Serial Port RTS Pin Input/Output */
-#define SCSPTR_RTSDT	BIT(6)	/* Serial Port RTS Pin Data */
-#define SCSPTR_CTSIO	BIT(5)	/* Serial Port CTS Pin Input/Output */
-#define SCSPTR_CTSDT	BIT(4)	/* Serial Port CTS Pin Data */
+#define SCSPTR_RTSIO	BIT(7)	/* Serial Port RTS# Pin Input/Output */
+#define SCSPTR_RTSDT	BIT(6)	/* Serial Port RTS# Pin Data */
+#define SCSPTR_CTSIO	BIT(5)	/* Serial Port CTS# Pin Input/Output */
+#define SCSPTR_CTSDT	BIT(4)	/* Serial Port CTS# Pin Data */
+#define SCSPTR_SCKIO	BIT(3)	/* Serial Port Clock Pin Input/Output */
+#define SCSPTR_SCKDT	BIT(2)	/* Serial Port Clock Pin Data */
 #define SCSPTR_SPB2IO	BIT(1)	/* Serial Port Break Input/Output */
 #define SCSPTR_SPB2DT	BIT(0)	/* Serial Port Break Data */
Signature · 1 line
2.7.4
author
#7 lore raw

PATCH 7/15 serial: sh-sci: Add more Serial Port Control/Data Register documentation

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Improve documentation for the SCIFA/SCIFB Serial Port Control and Data Registers:
- State clearly that the RTS and CTS lines are active-low,
- Document the bits related to the serial port's SCK, RXD, and TXD pins.

Signed-off-by Geert Uytterhoeven <[email protected]>
Reviewed-by Peter Hurley <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit 4780c09f7a0926674c96c0a40dfeb7469f759c8e)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.h | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)
drivers/tty/serial/sh-sci.h +10 -4
index fa560c0..1b699ea 100644
@@ -104,12 +104,18 @@ enum {
 #define HSCIF_SRE	BIT(15)	/* Sampling Rate Register Enable */
 
 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
-#define SCPCR_RTSC	BIT(4)	/* Serial Port RTS Pin / Output Pin */
-#define SCPCR_CTSC	BIT(3)	/* Serial Port CTS Pin / Input Pin */
+#define SCPCR_RTSC	BIT(4)	/* Serial Port RTS# Pin / Output Pin */
+#define SCPCR_CTSC	BIT(3)	/* Serial Port CTS# Pin / Input Pin */
+#define SCPCR_SCKC	BIT(2)	/* Serial Port SCK Pin / Output Pin */
+#define SCPCR_RXDC	BIT(1)	/* Serial Port RXD Pin / Input Pin */
+#define SCPCR_TXDC	BIT(0)	/* Serial Port TXD Pin / Output Pin */
 
 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
-#define SCPDR_RTSD	BIT(4)	/* Serial Port RTS Output Pin Data */
-#define SCPDR_CTSD	BIT(3)	/* Serial Port CTS Input Pin Data */
+#define SCPDR_RTSD	BIT(4)	/* Serial Port RTS# Output Pin Data */
+#define SCPDR_CTSD	BIT(3)	/* Serial Port CTS# Input Pin Data */
+#define SCPDR_SCKD	BIT(2)	/* Serial Port SCK Output Pin Data */
+#define SCPDR_RXDD	BIT(1)	/* Serial Port RXD Input Pin Data */
+#define SCPDR_TXDD	BIT(0)	/* Serial Port TXD Output Pin Data */
 
 
 #define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
Signature · 1 line
2.7.4
author
#8 lore raw

PATCH 8/15 serial: sh-sci: Correct pin initialization on (H)SCIF

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Correct pin initialization on (H)SCIF:
- RTS must be deasserted (it's active low),
- SCK must be an input, as it may be used as the optional external clock input.

Initial pin configuration must always be done:
- Regardless of the presence of dedicated RTS and CTS pins: if the register exists, the RTS/CTS bits exist, too,
- Regardless of hardware flow control being enabled or not: RTS must be deasserted.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit d2b9775d795ec05fb42504c0f47dd06ba5fd709e)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.c | 23 ++++++++---------------
 1 file changed, 8 insertions(+), 15 deletions(-)
drivers/tty/serial/sh-sci.c +8 -15
index f96f44c..e725023 100644
@@ -633,21 +633,14 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
 		return;
 	}
 
-	/*
-	 * For the generic path SCSPTR is necessary. Bail out if that's
-	 * unavailable, too.
-	 */
-	if (!sci_getreg(port, SCSPTR)->size)
-		return;
-
-	if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
-	    ((!(cflag & CRTSCTS)))) {
-		unsigned short status;
-
-		status = serial_port_in(port, SCSPTR);
-		status &= ~SCSPTR_CTSIO;
-		status |= SCSPTR_RTSIO;
-		serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
+	if (sci_getreg(port, SCSPTR)->size) {
+		u16 status = serial_port_in(port, SCSPTR);
+
+		/* RTS# is output, driven 1 */
+		status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
+		/* CTS# and SCK are inputs */
+		status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
+		serial_port_out(port, SCSPTR, status);
 	}
 }
Signature · 1 line
2.7.4
author
#9 lore raw

PATCH 9/15 serial: sh-sci: Add pin initialization for SCIFA/SCIFB

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Before, the driver relied on initialization by the boot loader, or by implicit reset state.

Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated RTS/CTS pins are available, which depends on the SoC and UART instance.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit e9d7a45a039913497a57887d85f5decfda4679f0)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)
drivers/tty/serial/sh-sci.c +15 -1
index e725023..e351c6f 100644
@@ -633,7 +633,21 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
 		return;
 	}
 
-	if (sci_getreg(port, SCSPTR)->size) {
+	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+		u16 ctrl = serial_port_in(port, SCPCR);
+
+		/* Enable RXD and TXD pin functions */
+		ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
+		if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
+			/* RTS# is output, driven 1 */
+			ctrl |= SCPCR_RTSC;
+			serial_port_out(port, SCPDR,
+				serial_port_in(port, SCPDR) | SCPDR_RTSD);
+			/* Enable CTS# pin function */
+			ctrl &= ~SCPCR_CTSC;
+		}
+		serial_port_out(port, SCPCR, ctrl);
+	} else if (sci_getreg(port, SCSPTR)->size) {
 		u16 status = serial_port_in(port, SCSPTR);
 
 		/* RTS# is output, driven 1 */
Signature · 1 line
2.7.4
#10 lore raw

PATCH 9/15 serial: sh-sci: Add pin initialization for SCIFA/SCIFB

Quoted 5 lines · Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Before, the driver relied on initialization by the boot loader, or by implicit reset state.

Quoted 7 lines

Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated RTS/CTS pins are available, which depends on the SoC and UART instance.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit e9d7a45a039913497a57887d85f5decfda4679f0)
Signed-off-by Fabrizio Castro <[email protected]>

[...]

Shouldn't we also take:

5f76895e4c71 serial: sh-sci: Fix late enablement of AUTORTS cfa6eb239154 serial: sh-sci: Fix (AUTO)RTS in sci_init_pins()

Ben.

Signature · 2 lines
Ben Hutchings
Software Developer, Codethink Ltd.
author
#11 lore raw

PATCH 9/15 serial: sh-sci: Add pin initialization for SCIFA/SCIFB

Hi Ben,

Quoted 18 lines

Subject: Re: [cip-dev][PATCH 09/15] serial: sh-sci: Add pin initialization for SCIFA/SCIFB

[This sender failed our fraud detection checks and may not be who they appear to be. Learn about spoofing at
http://aka.ms/LearnAboutSpoofing]

Quoted 5 lines · Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Before, the driver relied on initialization by the boot loader, or by implicit reset state.

Quoted 7 lines

Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated RTS/CTS pins are available, which depends on the SoC and UART instance.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit e9d7a45a039913497a57887d85f5decfda4679f0)
Signed-off-by Fabrizio Castro <[email protected]>
Quoted 6 lines

[...]

Shouldn't we also take:

5f76895e4c71 serial: sh-sci: Fix late enablement of AUTORTS cfa6eb239154 serial: sh-sci: Fix (AUTO)RTS in sci_init_pins()

I had a quick look at those patches before submitting the series, and it looks like the second patch comes with a little bit of baggage (more backporting), and I wasn't sure where to draw the line.
If you feel like those fixes are necessary I'll backport them, just let me know.

Thanks,
Fab

Quoted 6 lines

Ben.

--
Ben Hutchings
Software Developer, Codethink Ltd.

Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

#12 lore raw

PATCH 9/15 serial: sh-sci: Add pin initialization for SCIFA/SCIFB

Quoted 25 lines · Fabrizio Castro

Hi Ben,

Quoted 23 lines

Subject: Re: [cip-dev][PATCH 09/15] serial: sh-sci: Add pin initialization for SCIFA/SCIFB

[This sender failed our fraud detection checks and may not be who they appear to be. Learn about spoofing at
http://aka.ms/LearnAboutSpoofing]

Quoted 5 lines · Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Before, the driver relied on initialization by the boot loader, or by implicit reset state.

Quoted 7 lines

Note that unlike on (H)SCIF, the RTS/CTS bits exist only if dedicated RTS/CTS pins are available, which depends on the SoC and UART instance.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit e9d7a45a039913497a57887d85f5decfda4679f0)
Signed-off-by Fabrizio Castro <[email protected]>

[...]

Shouldn't we also take:

Quoted 7 lines
Quoted 2 lines

5f76895e4c71 serial: sh-sci: Fix late enablement of AUTORTS cfa6eb239154 serial: sh-sci: Fix (AUTO)RTS in sci_init_pins()

I had a quick look at those patches before submitting the series, and it looks like the second patch comes with a little bit of baggage (more backporting), and I wasn't sure where to draw the line.
If you feel like those fixes are necessary I'll backport them, just let me know.

I'll accept your decision; I just wanted to make sure you didn't accidentally leave them out.

Ben.

Signature · 2 lines
Ben Hutchings
Software Developer, Codethink Ltd.
author
#13 lore raw

PATCH 10/15 serial: sh-sci: Fix support for hardware-assisted RTS/CTS

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

The existing support for hardware-assisted RTS/CTS is rudimentary and doesn't work.

Add support for hardware-assisted RTS/CTS hardware flow control for the (H)SCIF, SCIFA, and SCIFB variants.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit 33f50ffc253854cf6cd556786ae893c7454a1a67)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.c | 90 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 83 insertions(+), 7 deletions(-)
drivers/tty/serial/sh-sci.c +83 -7
index e351c6f..4e53fa4 100644
@@ -117,6 +117,8 @@ struct sci_port {
 	struct timer_list		rx_timer;
 	unsigned int			rx_timeout;
 #endif
+
+	bool autorts;
 };
 
 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS

@@ -1732,6 +1734,46 @@ static unsigned int sci_tx_empty(struct uart_port *port)
 	return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
 }
 
+static void sci_set_rts(struct uart_port *port, bool state)
+{
+	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+		u16 data = serial_port_in(port, SCPDR);
+
+		/* Active low */
+		if (state)
+			data &= ~SCPDR_RTSD;
+		else
+			data |= SCPDR_RTSD;
+		serial_port_out(port, SCPDR, data);
+
+		/* RTS# is output */
+		serial_port_out(port, SCPCR,
+				serial_port_in(port, SCPCR) | SCPCR_RTSC);
+	} else if (sci_getreg(port, SCSPTR)->size) {
+		u16 ctrl = serial_port_in(port, SCSPTR);
+
+		/* Active low */
+		if (state)
+			ctrl &= ~SCSPTR_RTSDT;
+		else
+			ctrl |= SCSPTR_RTSDT;
+		serial_port_out(port, SCSPTR, ctrl);
+	}
+}
+
+static bool sci_get_cts(struct uart_port *port)
+{
+	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+		/* Active low */
+		return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
+	} else if (sci_getreg(port, SCSPTR)->size) {
+		/* Active low */
+		return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
+	}
+
+	return true;
+}
+
 /*
  * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
  * CTS/RTS is supported in hardware by at least one port and controlled

@@ -1762,6 +1804,31 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	}
 
 	mctrl_gpio_set(s->gpios, mctrl);
+
+	if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
+		return;
+
+	if (!(mctrl & TIOCM_RTS)) {
+		/* Disable Auto RTS */
+		serial_port_out(port, SCFCR,
+				serial_port_in(port, SCFCR) & ~SCFCR_MCE);
+
+		/* Clear RTS */
+		sci_set_rts(port, 0);
+	} else if (s->autorts) {
+		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+			/* Enable RTS# pin function */
+			serial_port_out(port, SCPCR,
+				serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
+		}
+
+		/* Enable Auto RTS */
+		serial_port_out(port, SCFCR,
+				serial_port_in(port, SCFCR) | SCFCR_MCE);
+	} else {
+		/* Set RTS */
+		sci_set_rts(port, 1);
+	}
 }
 
 static unsigned int sci_get_mctrl(struct uart_port *port)

@@ -1774,10 +1841,14 @@ static unsigned int sci_get_mctrl(struct uart_port *port)
 
 	/*
 	 * CTS/RTS is handled in hardware when supported, while nothing
-	 * else is wired up. Keep it simple and simply assert CTS/DSR/CAR.
+	 * else is wired up.
 	 */
-	if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)))
+	if (s->autorts) {
+		if (sci_get_cts(port))
+			mctrl |= TIOCM_CTS;
+	} else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
 		mctrl |= TIOCM_CTS;
+	}
 	if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
 		mctrl |= TIOCM_DSR;
 	if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))

@@ -1850,6 +1921,7 @@ static void sci_shutdown(struct uart_port *port)
 
 	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
 
+	s->autorts = false;
 	mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
 
 	spin_lock_irqsave(&port->lock, flags);

@@ -2035,15 +2107,18 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	sci_init_pins(port, termios->c_cflag);
 
+	port->status &= ~UPSTAT_AUTOCTS;
+	s->autorts = false;
 	reg = sci_getreg(port, SCFCR);
 	if (reg->size) {
 		unsigned short ctrl = serial_port_in(port, SCFCR);
 
-		if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
-			if (termios->c_cflag & CRTSCTS)
-				ctrl |= SCFCR_MCE;
-			else
-				ctrl &= ~SCFCR_MCE;
+		if ((port->flags & UPF_HARD_FLOW) &&
+		    (termios->c_cflag & CRTSCTS)) {
+			/* There is no CTS interrupt to restart the hardware */
+			port->status |= UPSTAT_AUTOCTS;
+			/* MCE is enabled when RTS is raised */
+			s->autorts = true;
 		}
 
 		/*

@@ -2687,6 +2762,7 @@ static int sci_probe_single(struct platform_device *dev,
 			dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
 			return -EINVAL;
 		}
+		sciport->port.flags |= UPF_HARD_FLOW;
 	}
 
 	ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
Signature · 1 line
2.7.4
author
#14 lore raw

PATCH 11/15 serial: sh-sci: Add DT support for dedicated RTS/CTS

In reply to Fabrizio Castro

From: Geert Uytterhoeven <[email protected]>

Add support for indicating the availability of dedicated lines for RTS/CTS hardware flow control, using the standard "uart-has-rtscts" DT property.

Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
(cherry picked from commit 861a70abb483645d4474a6bc006471c2db59a78d)
Signed-off-by Fabrizio Castro <[email protected]>
---
 drivers/tty/serial/sh-sci.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/tty/serial/sh-sci.c +3 -0
index 4e53fa4..b09db16 100644
@@ -2728,6 +2728,9 @@ sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
 	p->regtype = info->regtype;
 	p->scscr = SCSCR_RE | SCSCR_TE;
 
+	if (of_find_property(np, "uart-has-rtscts", NULL))
+		p->capabilities |= SCIx_HAVE_RTSCTS;
+
 	return p;
 }
Signature · 1 line
2.7.4
author
#15 lore raw

PATCH 12/15 ARM: dts: iwg20d-q7: Rework DT architecture

In reply to Fabrizio Castro

Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier board definitions, and its content is basically the same as the previous version of r8a7743-iwg20d-q7.dts, only it has no reference to the SoM .dtsi, and that's why the filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board .dtsi defined by this very patch, along with "model" and "compatible" properties.
The final DT architecture to describe the board is now:

r8a7743-iwg20d-q7.dts           # Carrier Board + SoM
??? r8a7743-iwg20m.dtsi         # SoM
??? ??? r8a7743.dtsi            # SoC
??? iwg20d-q7-common.dtsi       # Carrier Board

and maximizes the reuse of the definitions for the carrier board and for the SoM.

Signed-off-by Fabrizio Castro <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>
(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)
Signed-off-by Fabrizio Castro <[email protected]>
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +----------------------------
 2 files changed, 110 insertions(+), 98 deletions(-)
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +108 -0
new file mode 100644
index 0000000..1a0bb24
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/ {
+	aliases {
+		serial0 = &scif0;
+		ethernet0 = &avb;
+	};
+
+	vcc_sdhi1: regulator-vcc-sdhi1 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI1 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+	};
+
+	vccq_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
+};
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&phy3>;
+	phy-mode = "gmii";
+	renesas,no-ether-link;
+	status = "okay";
+
+	phy3: ethernet-phy at 3 {
+		reg = <3>;
+		micrel,led-mode = <1>;
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	rtc at 68 {
+		compatible = "bq32000";
+		reg = <0x68>;
+	};
+};
+
+&pfc {
+	avb_pins: avb {
+		groups = "avb_mdio", "avb_gmii";
+		function = "avb";
+	};
+
+	i2c2_pins: i2c2 {
+		groups = "i2c2";
+		function = "i2c2";
+	};
+
+	scif0_pins: scif0 {
+		groups = "scif0_data_d";
+		function = "scif0";
+	};
+
+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&vcc_sdhi1>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +2 -98

112 lines not on this page · raw message

Signature · 1 line
2.7.4
#16 lore raw

PATCH 12/15 ARM: dts: iwg20d-q7: Rework DT architecture

Quoted 11 lines · Fabrizio Castro

Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier ? board definitions, and its content is basically the same ? as the previous version of r8a7743-iwg20d-q7.dts, only it ? has no reference to the SoM .dtsi, and that's why the ? filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together ? the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board ? .dtsi defined by this very patch, along with "model" and

Quoted 8 lines

? "compatible" properties.
The final DT architecture to describe the board is now:
r8a7743-iwg20d-q7.dts???????????# Carrier Board + SoM ??? r8a7743-iwg20m.dtsi?????????# SoM
??? ??? r8a7743.dtsi????????????# SoC
??? iwg20d-q7-common.dtsi???????# Carrier Board
and maximizes the reuse of the definitions for the carrier board and for the SoM.

I got a conflict at this point. It looks like this series has to be applied on top of the SDHI changes, which you posted later! Please be explicit about any such ordering dependencies.

Ben.

Quoted 251 lines
Signed-off-by Fabrizio Castro <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>
(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)
Signed-off-by Fabrizio Castro <[email protected]>

---
?arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108
++++++++++++++++++++++++++++++++
?arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +---------------------
-------
?2 files changed, 110 insertions(+), 98 deletions(-) ?create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +6 -0
new file mode 100644
index 0000000..1a0bb24
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public

License
+ * version 2.??This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +99 -0
+
+/ {
+	aliases {
+		serial0 = &scif0;
+		ethernet0 = &avb;
+	};
+
+	vcc_sdhi1: regulator-vcc-sdhi1 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI1 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+	};
+
+	vccq_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			??1800000 0>;
+	};
+};
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+
+	phy-handle = <&phy3>;
+	phy-mode = "gmii";
+	renesas,no-ether-link;
+	status = "okay";
+
+	phy3: ethernet-phy at 3 {
+		reg = <3>;
+		micrel,led-mode = <1>;
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	rtc at 68 {
+		compatible = "bq32000";
+		reg = <0x68>;
+	};
+};
+
+&pfc {
+	avb_pins: avb {
+		groups = "avb_mdio", "avb_gmii";
+		function = "avb";
+	};
+
+	i2c2_pins: i2c2 {
+		groups = "i2c2";
+		function = "i2c2";
+	};
+
+	scif0_pins: scif0 {
+		groups = "scif0_data_d";
+		function = "scif0";
+	};
+
+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&vcc_sdhi1>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -0
index 0bd9754..6aa6b74 100644
@@ -1,5 +1,5 @@

?/*
- * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ * Device Tree Source for the iWave-RZ/G1M Qseven board ? *
? * Copyright (C) 2017 Renesas Electronics Corp.
? *

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -0
@@ -10,105 +10,9 @@

?
?/dts-v1/;
?#include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
?
?/ {
? model = "iWave Systems RainboW-G20D-Qseven board based on
RZ/G1M";
? compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -97
-
-	aliases {
-		serial0 = &scif0;
-		ethernet0 = &avb;
-	};
-
-	vcc_sdhi1: regulator-vcc-sdhi1 {
-		compatible = "regulator-fixed";
-
-		regulator-name = "SDHI1 Vcc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
-	};
-
-	vccq_sdhi1: regulator-vccq-sdhi1 {
-		compatible = "regulator-gpio";
-
-		regulator-name = "SDHI1 VccQ";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
-		gpios-states = <1>;
-		states = <3300000 1
-			??1800000 0>;
-	};
-};
-
-&pfc {
-	i2c2_pins: i2c2 {
-		groups = "i2c2";
-		function = "i2c2";
-	};
-
-	scif0_pins: scif0 {
-		groups = "scif0_data_d";
-		function = "scif0";
-	};
-
-	avb_pins: avb {
-		groups = "avb_mdio", "avb_gmii";
-		function = "avb";
-	};
-
-	sdhi1_pins: sd1 {
-		groups = "sdhi1_data4", "sdhi1_ctrl";
-		function = "sdhi1";
-		power-source = <3300>;
-	};
-};
-
-&scif0 {
-	pinctrl-0 = <&scif0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&avb {
-	pinctrl-0 = <&avb_pins>;
-	pinctrl-names = "default";
-
-	phy-handle = <&phy3>;
-	phy-mode = "gmii";
-	renesas,no-ether-link;
-	status = "okay";
-
-	phy3: ethernet-phy at 3 {
-		reg = <3>;
-		micrel,led-mode = <1>;
-	};
-};
-
-&sdhi1 {
-	pinctrl-0 = <&sdhi1_pins>;
-	pinctrl-names = "default";
-
-	vmmc-supply = <&vcc_sdhi1>;
-	vqmmc-supply = <&vccq_sdhi1>;
-	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&i2c2 {
-	pinctrl-0 = <&i2c2_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-	clock-frequency = <400000>;
-
-	rtc at 68 {
-		compatible = "bq32000";
-		reg = <0x68>;
-	};

?};

Signature · 2 lines
Ben Hutchings
Software Developer, Codethink Ltd.
#17 lore raw

PATCH 12/15 ARM: dts: iwg20d-q7: Rework DT architecture

Quoted 21 lines · Ben Hutchings
Quoted 11 lines · Fabrizio Castro

Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier ? board definitions, and its content is basically the same ? as the previous version of r8a7743-iwg20d-q7.dts, only it ? has no reference to the SoM .dtsi, and that's why the ? filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together ? the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board ? .dtsi defined by this very patch, along with "model" and

Quoted 8 lines

? "compatible" properties.
The final DT architecture to describe the board is now:
r8a7743-iwg20d-q7.dts???????????# Carrier Board + SoM ??? r8a7743-iwg20m.dtsi?????????# SoM
??? ??? r8a7743.dtsi????????????# SoC
??? iwg20d-q7-common.dtsi???????# Carrier Board
and maximizes the reuse of the definitions for the carrier board and for the SoM.

Quoted 3 lines

I got a conflict at this point.??It looks like this series has to be applied on top of the SDHI changes, which you posted later!??Please be explicit about any such ordering dependencies.

My mistake, you posted the SDHI changes earlier but they got reordered in my mailbox. Still, please let me know if any patch series you send depends on any other patch series that I haven't yet applied.

Ben.

Quoted 254 lines

Ben.

Quoted 251 lines
Quoted 4 lines
Quoted 4 lines
Signed-off-by Fabrizio Castro <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>

(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)

Quoted 1 line
Quoted 1 line
Signed-off-by Fabrizio Castro <[email protected]>

---
?arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108
++++++++++++++++++++++++++++++++
?arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +---------------------
-------
?2 files changed, 110 insertions(+), 98 deletions(-) ?create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +6 -0
new file mode 100644
index 0000000..1a0bb24
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public

License
+ * version 2.??This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+
+/ {
Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 15

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+	aliases {
+		serial0 = &scif0;
+		ethernet0 = &avb;
+	};

+

Quoted 2 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 18

Quoted 2 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+	vcc_sdhi1: regulator-vcc-sdhi1 {
+		compatible = "regulator-fixed";

+

Quoted 3 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 22

Quoted 3 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+		regulator-name = "SDHI1 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;

+

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+	};

+

Quoted 2 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 28

Quoted 2 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+	vccq_sdhi1: regulator-vccq-sdhi1 {
+		compatible = "regulator-gpio";

+

Quoted 3 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 32

Quoted 3 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;

+

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +5 -0
+		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+		gpios-states = <1>;
+		states = <3300000 1
+			??1800000 0>;
+	};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&avb {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";

+

Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 48

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+	phy-handle = <&phy3>;
+	phy-mode = "gmii";
+	renesas,no-ether-link;
+	status = "okay";

+

Quoted 4 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +1 -0
+	phy3: ethernet-phy at 3 {
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+		reg = <3>;
+		micrel,led-mode = <1>;
+	};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&i2c2 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";

+

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+	status = "okay";
+	clock-frequency = <400000>;

+

Quoted 4 lines
Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+	rtc at 68 {
+		compatible = "bq32000";
+		reg = <0x68>;
+	};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&pfc {
Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 73

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+	avb_pins: avb {
+		groups = "avb_mdio", "avb_gmii";
+		function = "avb";
+	};

+

Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 78

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+	i2c2_pins: i2c2 {
+		groups = "i2c2";
+		function = "i2c2";
+	};

+

Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 83

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+	scif0_pins: scif0 {
+		groups = "scif0_data_d";
+		function = "scif0";
+	};

+

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +5 -0
+	sdhi1_pins: sd1 {
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
+		power-source = <3300>;
+	};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&scif0 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";

+

Quoted 1 line
Quoted 1 line
(quoted diff) +1 -0
+	status = "okay";
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&sdhi1 {
Quoted 2 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 101

Quoted 2 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-names = "default";

+

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +5 -0
+	vmmc-supply = <&vcc_sdhi1>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +1 -0
+};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -0
index 0bd9754..6aa6b74 100644
@@ -1,5 +1,5 @@

?/*
- * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ * Device Tree Source for the iWave-RZ/G1M Qseven board ? *
? * Copyright (C) 2017 Renesas Electronics Corp.
? *

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -0
@@ -10,105 +10,9 @@

?
?/dts-v1/;
?#include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
?
?/ {

Quoted 1 line
Quoted 1 line

? model = "iWave Systems RainboW-G20D-Qseven board based on

RZ/G1M";

Quoted 1 line
Quoted 1 line

? compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 21

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-	aliases {
-		serial0 = &scif0;
-		ethernet0 = &avb;
-	};

-

Quoted 2 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 24

Quoted 2 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -2
-	vcc_sdhi1: regulator-vcc-sdhi1 {
-		compatible = "regulator-fixed";

-

Quoted 3 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 28

Quoted 3 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-		regulator-name = "SDHI1 Vcc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;

-

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
-	};

-

Quoted 2 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 34

Quoted 2 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -2
-	vccq_sdhi1: regulator-vccq-sdhi1 {
-		compatible = "regulator-gpio";

-

Quoted 3 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 38

Quoted 3 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-		regulator-name = "SDHI1 VccQ";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;

-

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -5
-		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
-		gpios-states = <1>;
-		states = <3300000 1
-			??1800000 0>;
-	};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&pfc {
Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 51

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-	i2c2_pins: i2c2 {
-		groups = "i2c2";
-		function = "i2c2";
-	};

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 56

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-	scif0_pins: scif0 {
-		groups = "scif0_data_d";
-		function = "scif0";
-	};

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 61

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-	avb_pins: avb {
-		groups = "avb_mdio", "avb_gmii";
-		function = "avb";
-	};

-

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -5
-	sdhi1_pins: sd1 {
-		groups = "sdhi1_data4", "sdhi1_ctrl";
-		function = "sdhi1";
-		power-source = <3300>;
-	};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&scif0 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-	pinctrl-0 = <&scif0_pins>;
-	pinctrl-names = "default";

-

Quoted 1 line
Quoted 1 line
(quoted diff) +0 -1
-	status = "okay";
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&avb {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-	pinctrl-0 = <&avb_pins>;
-	pinctrl-names = "default";

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 84

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-	phy-handle = <&phy3>;
-	phy-mode = "gmii";
-	renesas,no-ether-link;
-	status = "okay";

-

Quoted 4 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -1
-	phy3: ethernet-phy at 3 {
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-		reg = <3>;
-		micrel,led-mode = <1>;
-	};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&sdhi1 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-	pinctrl-0 = <&sdhi1_pins>;
-	pinctrl-names = "default";

-

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -5
-	vmmc-supply = <&vcc_sdhi1>;
-	vqmmc-supply = <&vccq_sdhi1>;
-	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-	status = "okay";
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&i2c2 {
Quoted 2 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 105

Quoted 2 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -2
-	pinctrl-0 = <&i2c2_pins>;
-	pinctrl-names = "default";

-

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-	status = "okay";
-	clock-frequency = <400000>;

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 113

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-	rtc at 68 {
-		compatible = "bq32000";
-		reg = <0x68>;
-	};

?};

Signature · 2 lines
Ben Hutchings
Software Developer, Codethink Ltd.
author
#18 lore raw

PATCH 12/15 ARM: dts: iwg20d-q7: Rework DT architecture

Hi Ben,

Quoted 29 lines

-----Original Message-----
From: Ben Hutchings [mailto:ben.hutchings at codethink.co.uk]
Sent: 07 March 2018 17:49
To: Fabrizio Castro <[email protected]>
Cc: cip-dev at lists.cip-project.org; Chris Paterson <[email protected]>; Biju Das <[email protected]>
Subject: Re: [cip-dev][PATCH 12/15] ARM: dts: iwg20d-q7: Rework DT architecture

Quoted 21 lines · Ben Hutchings
Quoted 19 lines · Fabrizio Castro

Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier board definitions, and its content is basically the same as the previous version of r8a7743-iwg20d-q7.dts, only it has no reference to the SoM .dtsi, and that's why the filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board .dtsi defined by this very patch, along with "model" and "compatible" properties.
The final DT architecture to describe the board is now:

r8a7743-iwg20d-q7.dts           # Carrier Board + SoM
??? r8a7743-iwg20m.dtsi         # SoM
?   ??? r8a7743.dtsi            # SoC
??? iwg20d-q7-common.dtsi       # Carrier Board

and maximizes the reuse of the definitions for the carrier board and for the SoM.

Quoted 6 lines
Quoted 3 lines

I got a conflict at this point. It looks like this series has to be applied on top of the SDHI changes, which you posted later! Please be explicit about any such ordering dependencies.

My mistake, you posted the SDHI changes earlier but they got reordered in my mailbox.

Ah ok

Quoted 2 lines

Still, please let me know if any patch series you send depends on any other patch series that I haven't yet applied.

sorry I'll be more careful

Thanks,
Fab

Quoted 252 lines

Ben.

Quoted 249 lines

Ben.

Quoted 246 lines
Quoted 4 lines
Quoted 4 lines
Signed-off-by Fabrizio Castro <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>

(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)

Quoted 1 line
Quoted 1 line
Signed-off-by Fabrizio Castro <[email protected]>
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108
++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +---------------------
-------
 2 files changed, 110 insertions(+), 98 deletions(-)
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +6 -0
new file mode 100644
index 0000000..1a0bb24
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public

License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+
+/ {
Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 15

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+aliases {
+serial0 = &scif0;
+ethernet0 = &avb;
+};

+

Quoted 2 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 18

Quoted 2 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+vcc_sdhi1: regulator-vcc-sdhi1 {
+compatible = "regulator-fixed";

+

Quoted 3 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 22

Quoted 3 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+regulator-name = "SDHI1 Vcc";
+regulator-min-microvolt = <3300000>;
+regulator-max-microvolt = <3300000>;

+

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+};

+

Quoted 2 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 28

Quoted 2 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+vccq_sdhi1: regulator-vccq-sdhi1 {
+compatible = "regulator-gpio";

+

Quoted 3 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 32

Quoted 3 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+regulator-name = "SDHI1 VccQ";
+regulator-min-microvolt = <1800000>;
+regulator-max-microvolt = <3300000>;

+

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +5 -0
+gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+gpios-states = <1>;
+states = <3300000 1
+  1800000 0>;
+};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&avb {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+pinctrl-0 = <&avb_pins>;
+pinctrl-names = "default";

+

Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 48

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+phy-handle = <&phy3>;
+phy-mode = "gmii";
+renesas,no-ether-link;
+status = "okay";

+

Quoted 4 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line

+phy3: ethernet-phy at 3 {

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+reg = <3>;
+micrel,led-mode = <1>;
+};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&i2c2 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+pinctrl-0 = <&i2c2_pins>;
+pinctrl-names = "default";

+

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+status = "okay";
+clock-frequency = <400000>;

+

Quoted 4 lines
Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+rtc at 68 {
+compatible = "bq32000";
+reg = <0x68>;
+};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&pfc {
Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 73

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+avb_pins: avb {
+groups = "avb_mdio", "avb_gmii";
+function = "avb";
+};

+

Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 78

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+i2c2_pins: i2c2 {
+groups = "i2c2";
+function = "i2c2";
+};

+

Quoted 4 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 83

Quoted 4 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +4 -0
+scif0_pins: scif0 {
+groups = "scif0_data_d";
+function = "scif0";
+};

+

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +5 -0
+sdhi1_pins: sd1 {
+groups = "sdhi1_data4", "sdhi1_ctrl";
+function = "sdhi1";
+power-source = <3300>;
+};
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&scif0 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+pinctrl-0 = <&scif0_pins>;
+pinctrl-names = "default";

+

Quoted 1 line
Quoted 1 line

+status = "okay";

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +3 -0
+};
+
+&sdhi1 {
Quoted 2 lines

arch/arm/boot/dts/iwg20d-q7-common.dtsi line 101

Quoted 2 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +2 -0
+pinctrl-0 = <&sdhi1_pins>;
+pinctrl-names = "default";

+

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +5 -0
+vmmc-supply = <&vcc_sdhi1>;
+vqmmc-supply = <&vccq_sdhi1>;
+cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+status = "okay";
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +1 -0
+};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +2 -1
index 0bd9754..6aa6b74 100644
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ * Device Tree Source for the iWave-RZ/G1M Qseven board
  *
  * Copyright (C) 2017 Renesas Electronics Corp.
  *

@@ -10,105 +10,9 @@
 
 /dts-v1/;
 #include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
 
 / {
Quoted 1 line
Quoted 1 line

model = "iWave Systems RainboW-G20D-Qseven board based on

RZ/G1M";

Quoted 1 line
Quoted 1 line

compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 21

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-aliases {
-serial0 = &scif0;
-ethernet0 = &avb;
-};

-

Quoted 2 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 24

Quoted 2 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -2
-vcc_sdhi1: regulator-vcc-sdhi1 {
-compatible = "regulator-fixed";

-

Quoted 3 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 28

Quoted 3 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-regulator-name = "SDHI1 Vcc";
-regulator-min-microvolt = <3300000>;
-regulator-max-microvolt = <3300000>;

-

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
-};

-

Quoted 2 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 34

Quoted 2 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -2
-vccq_sdhi1: regulator-vccq-sdhi1 {
-compatible = "regulator-gpio";

-

Quoted 3 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 38

Quoted 3 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-regulator-name = "SDHI1 VccQ";
-regulator-min-microvolt = <1800000>;
-regulator-max-microvolt = <3300000>;

-

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -5
-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
-gpios-states = <1>;
-states = <3300000 1
-  1800000 0>;
-};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&pfc {
Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 51

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-i2c2_pins: i2c2 {
-groups = "i2c2";
-function = "i2c2";
-};

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 56

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-scif0_pins: scif0 {
-groups = "scif0_data_d";
-function = "scif0";
-};

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 61

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-avb_pins: avb {
-groups = "avb_mdio", "avb_gmii";
-function = "avb";
-};

-

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -5
-sdhi1_pins: sd1 {
-groups = "sdhi1_data4", "sdhi1_ctrl";
-function = "sdhi1";
-power-source = <3300>;
-};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&scif0 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-pinctrl-0 = <&scif0_pins>;
-pinctrl-names = "default";

-

Quoted 1 line
Quoted 1 line

-status = "okay";

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&avb {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-pinctrl-0 = <&avb_pins>;
-pinctrl-names = "default";

-

Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 84

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-phy-handle = <&phy3>;
-phy-mode = "gmii";
-renesas,no-ether-link;
-status = "okay";

-

Quoted 4 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line

-phy3: ethernet-phy at 3 {

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-reg = <3>;
-micrel,led-mode = <1>;
-};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&sdhi1 {
Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-pinctrl-0 = <&sdhi1_pins>;
-pinctrl-names = "default";

-

Quoted 5 lines
Quoted 5 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -5
-vmmc-supply = <&vcc_sdhi1>;
-vqmmc-supply = <&vccq_sdhi1>;
-cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
-wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-status = "okay";
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -3
-};
-
-&i2c2 {
Quoted 2 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 105

Quoted 2 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -2
-pinctrl-0 = <&i2c2_pins>;
-pinctrl-names = "default";

-

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +0 -2
-status = "okay";
-clock-frequency = <400000>;

-

Quoted 9 lines
Quoted 5 lines
Quoted 5 lines
Quoted 4 lines

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts line 113

Quoted 4 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-rtc at 68 {
-compatible = "bq32000";
-reg = <0x68>;
-};

};

--
Ben Hutchings
Software Developer, Codethink Ltd.

Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

author
#19 lore raw

PATCH 12/15 ARM: dts: iwg20d-q7: Rework DT architecture

In reply to Ben Hutchings

Hi Ben,

Quoted 23 lines

Subject: Re: [cip-dev][PATCH 12/15] ARM: dts: iwg20d-q7: Rework DT architecture

Quoted 19 lines · Fabrizio Castro

Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier board definitions, and its content is basically the same as the previous version of r8a7743-iwg20d-q7.dts, only it has no reference to the SoM .dtsi, and that's why the filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board .dtsi defined by this very patch, along with "model" and "compatible" properties.
The final DT architecture to describe the board is now:

r8a7743-iwg20d-q7.dts           # Carrier Board + SoM
??? r8a7743-iwg20m.dtsi         # SoM
?   ??? r8a7743.dtsi            # SoC
??? iwg20d-q7-common.dtsi       # Carrier Board

and maximizes the reuse of the definitions for the carrier board and for the SoM.

first of all, I am very sorry but my mail server is misbehaving quite badly at the moment, it looks like most (but not all) of the emails addressed to you or coming from you have reached my junk folder for no reason, and I have discovered this only today unfortunately.
Hopefully I'll find all of your emails...

Quoted 2 lines

I got a conflict at this point. It looks like this series has to be applied on top of the SDHI changes, which you posted later!

did you receive them later? I have sent the SDHI patches out on the 2nd, but I don't trust my mail server right now.

Quoted 1 line

Please be explicit about any such ordering dependencies.

Ooops, I usually do explicit this kind of dependencies, I am very sorry for the pain.

Thanks,
Fab

Quoted 249 lines

Ben.

Quoted 246 lines
Signed-off-by Fabrizio Castro <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>
(cherry picked from commit 4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7)
Signed-off-by Fabrizio Castro <[email protected]>
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 108
++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 100 +---------------------
-------
 2 files changed, 110 insertions(+), 98 deletions(-)
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi
arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +6 -0
new file mode 100644
index 0000000..1a0bb24
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public

License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */

arch/arm/boot/dts/iwg20d-q7-common.dtsi new file +99 -0
+
+/ {
+aliases {
+serial0 = &scif0;
+ethernet0 = &avb;
+};
+
+vcc_sdhi1: regulator-vcc-sdhi1 {
+compatible = "regulator-fixed";
+
+regulator-name = "SDHI1 Vcc";
+regulator-min-microvolt = <3300000>;
+regulator-max-microvolt = <3300000>;
+
+gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
+};
+
+vccq_sdhi1: regulator-vccq-sdhi1 {
+compatible = "regulator-gpio";
+
+regulator-name = "SDHI1 VccQ";
+regulator-min-microvolt = <1800000>;
+regulator-max-microvolt = <3300000>;
+
+gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+gpios-states = <1>;
+states = <3300000 1
+  1800000 0>;
+};
+};
+
+&avb {
+pinctrl-0 = <&avb_pins>;
+pinctrl-names = "default";
+
+phy-handle = <&phy3>;
+phy-mode = "gmii";
+renesas,no-ether-link;
+status = "okay";
+
+phy3: ethernet-phy at 3 {
+reg = <3>;
+micrel,led-mode = <1>;
+};
+};
+
+&i2c2 {
+pinctrl-0 = <&i2c2_pins>;
+pinctrl-names = "default";
+
+status = "okay";
+clock-frequency = <400000>;
+
+rtc at 68 {
+compatible = "bq32000";
+reg = <0x68>;
+};
+};
+
+&pfc {
+avb_pins: avb {
+groups = "avb_mdio", "avb_gmii";
+function = "avb";
+};
+
+i2c2_pins: i2c2 {
+groups = "i2c2";
+function = "i2c2";
+};
+
+scif0_pins: scif0 {
+groups = "scif0_data_d";
+function = "scif0";
+};
+
+sdhi1_pins: sd1 {
+groups = "sdhi1_data4", "sdhi1_ctrl";
+function = "sdhi1";
+power-source = <3300>;
+};
+};
+
+&scif0 {
+pinctrl-0 = <&scif0_pins>;
+pinctrl-names = "default";
+
+status = "okay";
+};
+
+&sdhi1 {
+pinctrl-0 = <&sdhi1_pins>;
+pinctrl-names = "default";
+
+vmmc-supply = <&vcc_sdhi1>;
+vqmmc-supply = <&vccq_sdhi1>;
+cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+status = "okay";
+};
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +2 -94
index 0bd9754..6aa6b74 100644
@@ -1,5 +1,5 @@
 /*
- * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ * Device Tree Source for the iWave-RZ/G1M Qseven board
  *
  * Copyright (C) 2017 Renesas Electronics Corp.
  *

@@ -10,105 +10,9 @@
 
 /dts-v1/;
 #include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
 
 / {
 model = "iWave Systems RainboW-G20D-Qseven board based on
 RZ/G1M";
 compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
-
-aliases {
-serial0 = &scif0;
-ethernet0 = &avb;
-};
-
-vcc_sdhi1: regulator-vcc-sdhi1 {
-compatible = "regulator-fixed";
-
-regulator-name = "SDHI1 Vcc";
-regulator-min-microvolt = <3300000>;
-regulator-max-microvolt = <3300000>;
-
-gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
-};
-
-vccq_sdhi1: regulator-vccq-sdhi1 {
-compatible = "regulator-gpio";
-
-regulator-name = "SDHI1 VccQ";
-regulator-min-microvolt = <1800000>;
-regulator-max-microvolt = <3300000>;
-
-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
-gpios-states = <1>;
-states = <3300000 1
-  1800000 0>;
-};
-};
-
-&pfc {
-i2c2_pins: i2c2 {
-groups = "i2c2";
-function = "i2c2";
-};
-
-scif0_pins: scif0 {
-groups = "scif0_data_d";
-function = "scif0";
-};
-
-avb_pins: avb {
-groups = "avb_mdio", "avb_gmii";
-function = "avb";
-};
-
-sdhi1_pins: sd1 {
-groups = "sdhi1_data4", "sdhi1_ctrl";
-function = "sdhi1";
-power-source = <3300>;
-};
-};
-
-&scif0 {
-pinctrl-0 = <&scif0_pins>;
-pinctrl-names = "default";
-
-status = "okay";
-};
-
-&avb {
-pinctrl-0 = <&avb_pins>;
-pinctrl-names = "default";
-
-phy-handle = <&phy3>;
-phy-mode = "gmii";
-renesas,no-ether-link;
-status = "okay";
-
-phy3: ethernet-phy at 3 {
-reg = <3>;
-micrel,led-mode = <1>;
-};
-};
-
-&sdhi1 {
-pinctrl-0 = <&sdhi1_pins>;
-pinctrl-names = "default";
-
-vmmc-supply = <&vcc_sdhi1>;
-vqmmc-supply = <&vccq_sdhi1>;
-cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
-wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
-status = "okay";
-};
-
-&i2c2 {
-pinctrl-0 = <&i2c2_pins>;
-pinctrl-names = "default";
-
-status = "okay";
-clock-frequency = <400000>;
-
Quoted 8 lines
Quoted 5 lines
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +0 -4
-rtc at 68 {
-compatible = "bq32000";
-reg = <0x68>;
-};

};

--
Ben Hutchings
Software Developer, Codethink Ltd.

Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

author
#20 lore raw

PATCH 13/15 ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB

In reply to Fabrizio Castro

This patch adds a .dtsi that describes the camera daughter board and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's RZ/G1M/G1N Qseven carrier board, and the camera daughter board. The camera daughter board .dtsi adds support for ttySC[14].

Signed-off-by Fabrizio Castro <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>
(cherry picked from commit 2ee18841ff649e973d62afc6096b892396a676ef)
Signed-off-by Fabrizio Castro <[email protected]>
---
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi        | 43 +++++++++++++++++++++++++
 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 19 +++++++++++
 3 files changed, 63 insertions(+)
 create mode 100644 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
 create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
arch/arm/boot/dts/Makefile +1 -0
index f8fd692..22fc8ab 100644
@@ -545,6 +545,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
 	r8a73a4-ape6evm.dtb \
 	r8a7740-armadillo800eva.dtb \
 	r8a7743-iwg20d-q7.dtb \
+	r8a7743-iwg20d-q7-dbcm-ca.dtb \
 	r8a7778-bockw.dtb \
 	r8a7779-marzen.dtb \
 	r8a7790-lager.dtb \
arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi new file +43 -0

43 lines not on this page · raw message

arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts new file +19 -0
new file mode 100644
index 0000000..d90eb84
@@ -0,0 +1,19 @@
+/*
+ * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+#include "iwg20d-q7-dbcm-ca.dtsi"
+
+/ {
+	model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
+	compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
+};
Signature · 1 line
2.7.4
author
#21 lore raw

PATCH 14/15 ARM: dts: iwg20d-q7: Add support for ttySC3

In reply to Fabrizio Castro
Signed-off-by Fabrizio Castro <[email protected]>
Signed-off-by Chris Paterson <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Signed-off-by Simon Horman <[email protected]>
(cherry picked from commit 77014a7c654c76e1c0cf82563cc48e07c546461c)
Signed-off-by Fabrizio Castro <[email protected]>
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm/boot/dts/iwg20d-q7-common.dtsi +14 -0
index 1a0bb24..7d93a7c 100644
@@ -11,6 +11,7 @@
 / {
 	aliases {
 		serial0 = &scif0;
+		serial3 = &scifb1;
 		ethernet0 = &avb;
 	};
 

@@ -82,6 +83,11 @@
 		function = "scif0";
 	};
 
+	scifb1_pins: scifb1 {
+		groups = "scifb1_data_d", "scifb1_ctrl";
+		function = "scifb1";
+	};
+
 	sdhi1_pins: sd1 {
 		groups = "sdhi1_data4", "sdhi1_ctrl";
 		function = "sdhi1";

@@ -96,6 +102,14 @@
 	status = "okay";
 };
 
+&scifb1 {
+	pinctrl-0 = <&scifb1_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+	status = "okay";
+};
+
 &sdhi1 {
 	pinctrl-0 = <&sdhi1_pins>;
 	pinctrl-names = "default";
Signature · 1 line
2.7.4
author
#22 lore raw

PATCH 15/15 ARM: dts: iwg20d-q7: Add chosen node

In reply to Fabrizio Castro

From: Biju Das <[email protected]>

Signed-off-by Biju Das <[email protected]>
Signed-off-by Simon Horman <[email protected]>
(cherry picked from commit f9c1e87e77ca1ef1c4de2d419b0dcb42e4a47043)
Signed-off-by Fabrizio Castro <[email protected]>
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 5 +++++
 1 file changed, 5 insertions(+)
arch/arm/boot/dts/iwg20d-q7-common.dtsi +5 -0
index 7d93a7c..5dec247 100644
@@ -15,6 +15,11 @@
 		ethernet0 = &avb;
 	};
 
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		stdout-path = "serial0:115200n8";
+	};
+
 	vcc_sdhi1: regulator-vcc-sdhi1 {
 		compatible = "regulator-fixed";
Signature · 1 line
2.7.4
Applied
#23 lore raw

cover Add UART support to r8a7743

In reply to Fabrizio Castro

I've applied this series, thanks.

Ben.

Quoted 48 lines · Fabrizio Castro

This series aims at adding UART support to r8a7743 by backporting the relevant patches from upstream.
As per upstream, since two of the serial interfaces live on the camera daughter board, we rework the DT architecture to better accomodate all the possible HW variants.

Finally, in order to get CTS/RTS to work this series backports fixes made by Geert some time ago.

Thanks,
Fabrizio

Biju Das (1):
? ARM: dts: iwg20d-q7: Add chosen node

Fabrizio Castro (3):
? ARM: dts: iwg20d-q7: Rework DT architecture
? ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB ? ARM: dts: iwg20d-q7: Add support for ttySC3

Geert Uytterhoeven (11):
? serial: sh-sci: Update DT binding documentation for GPIO modem lines ? serial: sh-sci: Update DT binding documentation for dedicated RTS/CTS ? serial: sh-sci: Always set TIOCM_CTS in .get_mctrl() callback ? serial: sh-sci: Add support for GPIO-controlled modem lines ? serial: sh-sci: Do not open-code sci_getreg()
? serial: sh-sci: Add more Serial Port Register documentation ? serial: sh-sci: Add more Serial Port Control/Data Register ????documentation
? serial: sh-sci: Correct pin initialization on (H)SCIF
? serial: sh-sci: Add pin initialization for SCIFA/SCIFB
? serial: sh-sci: Fix support for hardware-assisted RTS/CTS ? serial: sh-sci: Add DT support for dedicated RTS/CTS

?.../bindings/serial/renesas,sci-serial.txt?????????|???4 +
?arch/arm/boot/dts/Makefile?????????????????????????|???1 +
?arch/arm/boot/dts/iwg20d-q7-common.dtsi????????????| 127 +++++++++++++++
?arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi???????????|??43 +++++
?arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts????|??19 +++
?arch/arm/boot/dts/r8a7743-iwg20d-q7.dts????????????| 100 +-----------
?drivers/tty/serial/Kconfig?????????????????????????|???1 +
?drivers/tty/serial/sh-sci.c????????????????????????| 177 ++++++++++++++++++---
?drivers/tty/serial/sh-sci.h????????????????????????|??24 ++-

?9 files changed, 365 insertions(+), 131 deletions(-) ?create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi ?create mode 100644 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi ?create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts

Signature · 2 lines
Ben Hutchings
Software Developer, Codethink Ltd.