Switch DPU to use upstream DSI driver for SDM845

Upstream DSI driver doesn't support DSC panels yet. Remove the support for compression from DPU for now.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/Makefile                       |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c      |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 476 +--------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h        |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   7 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  25 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c         | 252 -----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h         | 100 -----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |  17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c    |  48 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h    |  22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c         |  13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h         |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             |  55 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |   8 -
 drivers/gpu/drm/msm/msm_drv.h                      |  16 -
 20 files changed, 7 insertions(+), 1084 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

drivers/gpu/drm/msm/Makefile +0 -1

index 9c27991..b23a001 100644
@@ -64,7 +64,6 @@ msm-y := \
 	disp/dpu1/dpu_hw_color_processing_v1_7.o \
 	disp/dpu1/dpu_hw_ctl.o \
 	disp/dpu1/dpu_hw_ds.o \
-	disp/dpu1/dpu_hw_dsc.o \
 	disp/dpu1/dpu_hw_dspp.o \
 	disp/dpu1/dpu_hw_interrupts.o \
 	disp/dpu1/dpu_hw_intf.o \

drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c +0 -4

index 36607e3..1237efc 100644
@@ -39,12 +39,8 @@
 static const struct drm_prop_enum_list e_topology_name[] = {
 	{DPU_RM_TOPOLOGY_NONE,	"dpu_none"},
 	{DPU_RM_TOPOLOGY_SINGLEPIPE,	"dpu_singlepipe"},
-	{DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,	"dpu_singlepipe_dsc"},
 	{DPU_RM_TOPOLOGY_DUALPIPE,	"dpu_dualpipe"},
-	{DPU_RM_TOPOLOGY_DUALPIPE_DSC,	"dpu_dualpipe_dsc"},
 	{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,	"dpu_dualpipemerge"},
-	{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,	"dpu_dualpipemerge_dsc"},
-	{DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE,	"dpu_dualpipe_dscmerge"},
 	{DPU_RM_TOPOLOGY_PPSPLIT,	"dpu_ppsplit"},
 };
 static const struct drm_prop_enum_list e_topology_control[] = {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +0 -0

index 8756b2b..fade658 100644

static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +0 -87

 			struct msm_display_info *disp_info)
 {

@@ -1109,102 +761,8 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 
 		hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
 	}
-}
-
-static int _dpu_encoder_dsc_disable(struct dpu_encoder_virt *dpu_enc)
-{
-	enum dpu_rm_topology_name topology;
-	struct drm_connector *drm_conn;
-	int i, ret = 0;
-	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
-	struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC] = {NULL};
-	int pp_count = 0;
-	int dsc_count = 0;
-
-	if (!dpu_enc || !dpu_enc->phys_encs[0] ||
-			!dpu_enc->phys_encs[0]->connector) {
-		DPU_ERROR("invalid params %d %d\n",
-			!dpu_enc, dpu_enc ? !dpu_enc->phys_encs[0] : -1);
-		return -EINVAL;
-	}
-
-	drm_conn = dpu_enc->phys_encs[0]->connector;
-
-	topology = dpu_connector_get_topology_name(drm_conn);
-	if (topology == DPU_RM_TOPOLOGY_NONE) {
-		DPU_ERROR_ENC(dpu_enc, "topology not set yet\n");
-		return -EINVAL;
-	}
-
-	switch (topology) {
-	case DPU_RM_TOPOLOGY_SINGLEPIPE:
-	case DPU_RM_TOPOLOGY_SINGLEPIPE_DSC:
-		/* single PP */
-		hw_pp[0] = dpu_enc->hw_pp[0];
-		hw_dsc[0] = dpu_enc->hw_dsc[0];
-		pp_count = 1;
-		dsc_count = 1;
-		break;
-	case DPU_RM_TOPOLOGY_DUALPIPE_DSC:
-	case DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC:
-	case DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE:
-		/* dual dsc */
-		for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
-			hw_dsc[i] = dpu_enc->hw_dsc[i];
-			if (hw_dsc[i])
-				dsc_count++;
-		}
-		/* fall through */
-	case DPU_RM_TOPOLOGY_DUALPIPE:
-	case DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:
-		/* dual pp */
-		for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
-			hw_pp[i] = dpu_enc->hw_pp[i];
-			if (hw_pp[i])
-				pp_count++;
-		}
-		break;
-	default:
-		DPU_DEBUG_ENC(dpu_enc, "Unexpected topology:%d\n", topology);
-		return -EINVAL;
-	};
-
-	DPU_EVT32(DRMID(&dpu_enc->base), topology, pp_count, dsc_count);
-
-	if (pp_count > MAX_CHANNELS_PER_ENC ||
-		dsc_count > MAX_CHANNELS_PER_ENC) {
-		DPU_ERROR_ENC(dpu_enc, "Wrong count pp:%d dsc:%d top:%d\n",
-				pp_count, dsc_count, topology);
-		return -EINVAL;
-	}
-
-	/* Disable DSC for all the pp's present in this topology */
-	for (i = 0; i < pp_count; i++) {
-
-		if (!hw_pp[i]) {
-			DPU_ERROR_ENC(dpu_enc, "null pp:%d top:%d cnt:%d\n",
-					i, topology, pp_count);
-			return -EINVAL;
-		}
-
-		if (hw_pp[i]->ops.disable_dsc)
-			hw_pp[i]->ops.disable_dsc(hw_pp[i]);
-	}
-
-	/* Disable DSC HW */
-	for (i = 0; i < dsc_count; i++) {
-
-		if (!hw_dsc[i]) {
-			DPU_ERROR_ENC(dpu_enc, "null dsc:%d top:%d cnt:%d\n",

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +0 -4

@@ -232,7 +232,6 @@ struct dpu_encoder_irq {
  * @split_role:		Role to play in a split-panel configuration
  * @intf_mode:		Interface mode
  * @intf_idx:		Interface index on dpu hardware
- * @comp_type:      Type of compression supported
  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
  * @enable_state:	Enable state tracking
  * @vblank_refcount:	Reference count of vblank request

@@ -262,7 +261,6 @@ struct dpu_encoder_phys {
 	enum dpu_enc_split_role split_role;
 	enum dpu_intf_mode intf_mode;
 	enum dpu_intf intf_idx;
-	enum msm_display_compression_type comp_type;
 	spinlock_t *enc_spinlock;
 	enum dpu_enc_enable_state enable_state;
 	atomic_t vblank_refcount;

@@ -384,7 +382,6 @@ struct dpu_encoder_phys_wb {
  * @split_role:		Role to play in a split-panel configuration
  * @intf_idx:		Interface index this phys_enc will control
  * @wb_idx:		Writeback index this phys_enc will control
- * @comp_type:      Type of compression supported
  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
  */
 struct dpu_enc_phys_init_params {

@@ -394,7 +391,6 @@ struct dpu_enc_phys_init_params {
 	enum dpu_enc_split_role split_role;
 	enum dpu_intf intf_idx;
 	enum dpu_wb wb_idx;
-	enum msm_display_compression_type comp_type;
 	spinlock_t *enc_spinlock;
 };
 

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Ping pong split topology was meant for low end soc's which doesn't have enough layer mixers to support split panels. Considering how uncommon the topology is for current chipset's and also to simply the driver programming, striping off the support for SDM845.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c      |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           |  19 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 179 +--------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   5 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 110 +------------
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c         |  33 ----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h         |  11 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h           |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             |  37 +----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |   2 -
 13 files changed, 15 insertions(+), 415 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c +1 -1

index 1237efc..f7e9f76 100644
@@ -41,8 +41,8 @@
 	{DPU_RM_TOPOLOGY_SINGLEPIPE,	"dpu_singlepipe"},
 	{DPU_RM_TOPOLOGY_DUALPIPE,	"dpu_dualpipe"},
 	{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,	"dpu_dualpipemerge"},
-	{DPU_RM_TOPOLOGY_PPSPLIT,	"dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
 	{DPU_RM_TOPCTL_RESERVE_LOCK,	"reserve_lock"},
 	{DPU_RM_TOPCTL_RESERVE_CLEAR,	"reserve_clear"},

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +0 -19

index 516458e..8e464fa 100644
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
 	mutex_unlock(&dpu_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-	int i;
-	struct dpu_crtc_state *cstate;
-
-	cstate = to_dpu_crtc_state(state);
-
-	cstate->is_ppsplit = false;
-	for (i = 0; i < cstate->num_connectors; i++) {
-		struct drm_connector *conn = cstate->connectors[i];
-
-		if (dpu_connector_get_topology_name(conn) ==
-				DPU_RM_TOPOLOGY_PPSPLIT)
-			cstate->is_ppsplit = true;
-	}
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {

@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
 	if (!dpu_crtc->num_mixers) {
 		_dpu_crtc_setup_mixers(crtc);
-		_dpu_crtc_setup_is_ppsplit(crtc->state);
 		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
 	}
 

@@ -2901,7 +2883,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 	mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-	_dpu_crtc_setup_is_ppsplit(state);
 	_dpu_crtc_setup_lm_bounds(crtc, state);
 
 	 /* get plane state for all drm planes associated with crtc state */

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +1 -178

index 6f12355..32375b1 100644
@@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
 	struct dpu_encoder_virt *dpu_enc;
 	struct split_pipe_cfg cfg = { 0 };
 	struct dpu_hw_mdp *hw_mdptop;
-	enum dpu_rm_topology_name topology;
 	struct msm_display_info *disp_info;
 
 	if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {

@@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
 	if (phys_enc->split_role == ENC_ROLE_SOLO) {
 		if (hw_mdptop->ops.setup_split_pipe)
 			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
-		if (hw_mdptop->ops.setup_pp_split)
-			hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
 		return;
 	}
 

@@ -582,29 +579,11 @@ void dpu_encoder_helper_split_config(
 			phys_enc->ops.needs_single_flush(phys_enc))
 		cfg.split_flush_en = true;
 
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-		cfg.pp_split_slave = cfg.intf;
-	else
-		cfg.pp_split_slave = INTF_MAX;
-
 	if (phys_enc->split_role == ENC_ROLE_MASTER) {
 		DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 
 		if (hw_mdptop->ops.setup_split_pipe)
 			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
-	} else if (dpu_enc->hw_pp[0]) {
-		/*
-		 * slave encoder
-		 * - determine split index from master index,
-		 *   assume master is first pp
-		 */
-		cfg.pp_split_index = dpu_enc->hw_pp[0]->idx - PINGPONG_0;
-		DPU_DEBUG_ENC(dpu_enc, "master using pp%d\n",
-				cfg.pp_split_index);
-
-		if (hw_mdptop->ops.setup_pp_split)
-			hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
 	}
 }
 

@@ -1665,14 +1644,6 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
 		return;
 	}
 
-	if (phys->split_role == ENC_ROLE_SKIP) {
-		DPU_DEBUG_ENC(to_dpu_encoder_virt(phys->parent),
-				"skip flush pp%d ctl%d\n",
-				phys->hw_pp->idx - PINGPONG_0,
-				ctl->idx - CTL_0);
-		return;
-	}
-
 	pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
 
 	if (extra_flush_bits && ctl->ops.update_pending_flush)

@@ -1694,8 +1665,6 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
  */
 static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
 {
-	struct dpu_hw_ctl *ctl;
-
 	if (!phys) {
 		DPU_ERROR("invalid argument(s)\n");
 		return;

@@ -1706,14 +1675,6 @@ static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
 		return;
 	}
 
-	ctl = phys->hw_ctl;
-	if (phys->split_role == ENC_ROLE_SKIP) {
-		DPU_DEBUG_ENC(to_dpu_encoder_virt(phys->parent),
-				"skip start pp%d ctl%d\n",
-				phys->hw_pp->idx - PINGPONG_0,
-				ctl->idx - CTL_0);
-		return;
-	}
 	if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
 		phys->ops.trigger_start(phys);
 }

@@ -1832,7 +1793,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
 	/* don't perform flush/start operations for slave encoders */
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-		enum dpu_rm_topology_name topology = DPU_RM_TOPOLOGY_NONE;
 
 		if (!phys || phys->enable_state == DPU_ENC_DISABLED)
 			continue;

@@ -1841,17 +1801,7 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
 		if (!ctl)
 			continue;
 
-		if (phys->connector)
-			topology = dpu_connector_get_topology_name(
-					phys->connector);
-
-		/*
-		 * don't wait on ppsplit slaves or skipped encoders because
-		 * they dont receive irqs
-		 */
-		if (!(topology == DPU_RM_TOPOLOGY_PPSPLIT &&
-				phys->split_role == ENC_ROLE_SLAVE) &&
-				phys->split_role != ENC_ROLE_SKIP)
+		if (phys->split_role != ENC_ROLE_SLAVE)
 			set_bit(i, dpu_enc->frame_busy_mask);
 		if (phys->hw_ctl->ops.reg_dma_flush)
 			phys->hw_ctl->ops.reg_dma_flush(phys->hw_ctl);

@@ -1875,126 +1825,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
 }
 
-static void _dpu_encoder_ppsplit_swap_intf_for_right_only_update(
-		struct drm_encoder *drm_enc,
-		unsigned long *affected_displays,
-		int num_active_phys)
-{
-	struct dpu_encoder_virt *dpu_enc;
-	struct dpu_encoder_phys *master;
-	enum dpu_rm_topology_name topology;
-	bool is_right_only;
-
-	if (!drm_enc || !affected_displays)
-		return;
-
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
-	master = dpu_enc->cur_master;
-	if (!master || !master->connector)
-		return;
-
-	topology = dpu_connector_get_topology_name(master->connector);
-	if (topology != DPU_RM_TOPOLOGY_PPSPLIT)
-		return;
-
-	/*
-	 * For pingpong split, the slave pingpong won't generate IRQs. For
-	 * right-only updates, we can't swap pingpongs, or simply swap the
-	 * master/slave assignment, we actually have to swap the interfaces
-	 * so that the master physical encoder will use a pingpong/interface
-	 * that generates irqs on which to wait.
-	 */
-	is_right_only = !test_bit(0, affected_displays) &&
-			test_bit(1, affected_displays);
-
-	if (is_right_only && !dpu_enc->intfs_swapped) {
-		/* right-only update swap interfaces */
-		swap(dpu_enc->phys_encs[0]->intf_idx,
-				dpu_enc->phys_encs[1]->intf_idx);
-		dpu_enc->intfs_swapped = true;
-	} else if (!is_right_only && dpu_enc->intfs_swapped) {
-		/* left-only or full update, swap back */
-		swap(dpu_enc->phys_encs[0]->intf_idx,
-				dpu_enc->phys_encs[1]->intf_idx);
-		dpu_enc->intfs_swapped = false;
-	}
-
-	DPU_DEBUG_ENC(dpu_enc,
-			"right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
-			is_right_only, dpu_enc->intfs_swapped,
-			dpu_enc->phys_encs[0]->intf_idx - INTF_0,
-			dpu_enc->phys_encs[1]->intf_idx - INTF_0);
-	DPU_EVT32(DRMID(drm_enc), is_right_only, dpu_enc->intfs_swapped,
-			dpu_enc->phys_encs[0]->intf_idx - INTF_0,
-			dpu_enc->phys_encs[1]->intf_idx - INTF_0,
-			*affected_displays);
-
-	/* ppsplit always uses master since ppslave invalid for irqs*/
-	if (num_active_phys == 1)
-		*affected_displays = BIT(0);
-}
-
-static void _dpu_encoder_update_master(struct drm_encoder *drm_enc,
-		struct dpu_encoder_kickoff_params *params)
-{
-	struct dpu_encoder_virt *dpu_enc;
-	struct dpu_encoder_phys *phys;
-	int i, num_active_phys;
-	bool master_assigned = false;
-
-	if (!drm_enc || !params)
-		return;
-
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
-
-	if (dpu_enc->num_phys_encs <= 1)
-		return;
-
-	/* count bits set */
-	num_active_phys = hweight_long(params->affected_displays);
-
-	DPU_DEBUG_ENC(dpu_enc, "affected_displays 0x%lx num_active_phys %d\n",
-			params->affected_displays, num_active_phys);
-
-	/* for left/right only update, ppsplit master switches interface */
-	_dpu_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
-			&params->affected_displays, num_active_phys);
-
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-		enum dpu_enc_split_role prv_role, new_role;
-		bool active;
-
-		phys = dpu_enc->phys_encs[i];
-		if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
-			continue;
-
-		active = test_bit(i, &params->affected_displays);
-		prv_role = phys->split_role;
-
-		if (active && num_active_phys == 1)
-			new_role = ENC_ROLE_SOLO;
-		else if (active && !master_assigned)
-			new_role = ENC_ROLE_MASTER;
-		else if (active)
-			new_role = ENC_ROLE_SLAVE;
-		else
-			new_role = ENC_ROLE_SKIP;
-
-		phys->ops.update_split_role(phys, new_role);
-		if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
-			dpu_enc->cur_master = phys;
-			master_assigned = true;
-		}
-
-		DPU_DEBUG_ENC(dpu_enc, "pp %d role prv %d new %d active %d\n",
-				phys->hw_pp->idx - PINGPONG_0, prv_role,
-				phys->split_role, active);
-		DPU_EVT32(DRMID(drm_enc), params->affected_displays,
-				phys->hw_pp->idx - PINGPONG_0, prv_role,
-				phys->split_role, active, num_active_phys);
-	}
-}
-
 bool dpu_encoder_check_mode(struct drm_encoder *drm_enc, u32 mode)
 {
 	struct dpu_encoder_virt *dpu_enc;

@@ -2048,15 +1878,10 @@ static void _dpu_encoder_setup_dither(struct dpu_encoder_phys *phys)
 	void *dither_cfg;
 	int ret = 0;
 	size_t len = 0;
-	enum dpu_rm_topology_name topology;
 
 	if (!phys || !phys->connector || !phys->hw_pp ||
 			!phys->hw_pp->ops.setup_dither)
 		return;
-	topology = dpu_connector_get_topology_name(phys->connector);
-	if ((topology == DPU_RM_TOPOLOGY_PPSPLIT) &&
-			(phys->split_role == ENC_ROLE_SLAVE))
-		return;
 
 	ret = dpu_connector_get_dither_cfg(phys->connector,
 				phys->connector->state, &dither_cfg, &len);

@@ -2267,8 +2092,6 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
 		}
 	}
 
-	_dpu_encoder_update_master(drm_enc, params);
-
 	if (dpu_enc->cur_master && dpu_enc->cur_master->connector) {
 		rc = dpu_connector_pre_kickoff(dpu_enc->cur_master->connector);
 		if (rc)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +0 -5

index 4e2e6c6..69ec2b6 100644
@@ -40,13 +40,11 @@
  * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
  * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
  * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
- * @ENC_ROLE_SKIP:	This encoder is not participating in kickoffs
  */
 enum dpu_enc_split_role {
 	ENC_ROLE_SOLO,
 	ENC_ROLE_MASTER,
 	ENC_ROLE_SLAVE,
-	ENC_ROLE_SKIP
 };
 
 /**

@@ -123,7 +121,6 @@ struct dpu_encoder_virt_ops {
  * @hw_reset:			Issue HW recovery such as CTL reset and clear
  *				DPU_ENC_ERR_NEEDS_HW_RESET state
  * @irq_control:		Handler to enable/disable all the encoder IRQs
- * @update_split_role:		Update the split role of the phys enc
  * @prepare_idle_pc:		phys encoder can update the vsync_enable status
  *                              on idle power collapse prepare
  * @restore:			Restore all the encoder configs.

@@ -167,8 +164,6 @@ struct dpu_encoder_phys_ops {
 	u32 (*collect_misr)(struct dpu_encoder_phys *phys_enc);
 	void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
 	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
-	void (*update_split_role)(struct dpu_encoder_phys *phys_enc,
-			enum dpu_enc_split_role role);
 	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
 	void (*restore)(struct dpu_encoder_phys *phys);
 	bool (*is_autorefresh_enabled)(struct dpu_encoder_phys *phys);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +8 -102

index 71e2e5a..3436788 100644
@@ -114,29 +114,6 @@ static void _dpu_encoder_phys_cmd_config_autorefresh(
 		hw_pp->ops.setup_autorefresh(hw_pp, cfg_cur);
 }
 
-static void _dpu_encoder_phys_cmd_update_flush_mask(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc =
-			to_dpu_encoder_phys_cmd(phys_enc);
-	struct dpu_hw_ctl *ctl;
-	u32 flush_mask = 0;
-
-	if (!phys_enc)
-		return;
-
-	ctl = phys_enc->hw_ctl;
-	if (!ctl || !ctl->ops.get_bitmask_intf ||
-			!ctl->ops.update_pending_flush)
-		return;
-
-	ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx);
-	ctl->ops.update_pending_flush(ctl, flush_mask);
-
-	DPU_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d flush_mask %x\n",
-			ctl->idx - CTL_0, flush_mask);
-}
-
 static void _dpu_encoder_phys_cmd_update_intf_cfg(
 		struct dpu_encoder_phys *phys_enc)
 {

@@ -324,20 +301,6 @@ static void dpu_encoder_phys_cmd_mode_set(
 	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
 }
 
-static bool _dpu_encoder_phys_is_ppsplit(struct dpu_encoder_phys *phys_enc)
-{
-	enum dpu_rm_topology_name topology;
-
-	if (!phys_enc)
-		return false;
-
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-		return true;
-
-	return false;
-}
-
 static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
 		struct dpu_encoder_phys *phys_enc)
 {

@@ -389,16 +352,6 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
 	return -ETIMEDOUT;
 }
 
-static bool _dpu_encoder_phys_is_ppsplit_slave(
-		struct dpu_encoder_phys *phys_enc)
-{
-	if (!phys_enc)
-		return false;
-
-	return _dpu_encoder_phys_is_ppsplit(phys_enc) &&
-			phys_enc->split_role == ENC_ROLE_SLAVE;
-}
-
 static int _dpu_encoder_phys_cmd_poll_write_pointer_started(
 		struct dpu_encoder_phys *phys_enc)
 {

@@ -483,10 +436,6 @@ static int _dpu_encoder_phys_cmd_wait_for_idle(
 	wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 
-	/* slave encoder doesn't enable for ppsplit */
-	if (_dpu_encoder_phys_is_ppsplit_slave(phys_enc))
-		return 0;
-
 	ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_PINGPONG,
 			&wait_info);
 	if (ret == -ETIMEDOUT)

@@ -588,7 +537,7 @@ void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
 {
 	struct dpu_encoder_phys_cmd *cmd_enc;
 
-	if (!phys_enc || _dpu_encoder_phys_is_ppsplit_slave(phys_enc))
+	if (!phys_enc)
 		return;
 
 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);

@@ -726,18 +675,18 @@ static void _dpu_encoder_phys_cmd_pingpong_config(
 			phys_enc->hw_pp->idx - PINGPONG_0);
 	drm_mode_debug_printmodeline(&phys_enc->cached_mode);
 
-	if (!_dpu_encoder_phys_is_ppsplit_slave(phys_enc))
-		_dpu_encoder_phys_cmd_update_intf_cfg(phys_enc);
+	_dpu_encoder_phys_cmd_update_intf_cfg(phys_enc);
 	dpu_encoder_phys_cmd_tearcheck_config(phys_enc);
 }
 
 static bool dpu_encoder_phys_cmd_needs_single_flush(
 		struct dpu_encoder_phys *phys_enc)
 {
-	if (!phys_enc)
-		return false;
-
-	return _dpu_encoder_phys_is_ppsplit(phys_enc);
+	/**
+	 * we do separate flush for each CTL and let
+	 * CTL_START synchronize them
+	 */
+	return false;
 }
 
 static void dpu_encoder_phys_cmd_enable_helper(

@@ -755,12 +704,7 @@ static void dpu_encoder_phys_cmd_enable_helper(
 
 	_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
 
-	/*
-	 * For pp-split, skip setting the flush bit for the slave intf, since
-	 * both intfs use same ctl and HW will only flush the master.
-	 */
-	if (_dpu_encoder_phys_is_ppsplit(phys_enc) &&
-		!dpu_encoder_phys_cmd_is_master(phys_enc))
+	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
 		goto skip_flush;
 
 	ctl = phys_enc->hw_ctl;

@@ -963,10 +907,6 @@ static int _dpu_encoder_phys_cmd_wait_for_ctl_start(
 	wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt;
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 
-	/* slave encoder doesn't enable for ppsplit */
-	if (_dpu_encoder_phys_is_ppsplit_slave(phys_enc))
-		return 0;
-
 	ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_CTL_START,
 			&wait_info);
 	if (ret == -ETIMEDOUT) {

@@ -1053,39 +993,6 @@ static int dpu_encoder_phys_cmd_wait_for_vblank(
 	return rc;
 }
 
-static void dpu_encoder_phys_cmd_update_split_role(
-		struct dpu_encoder_phys *phys_enc,
-		enum dpu_enc_split_role role)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc;
-	enum dpu_enc_split_role old_role;
-	bool is_ppsplit;
-
-	if (!phys_enc)
-		return;
-
-	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
-	old_role = phys_enc->split_role;
-	is_ppsplit = _dpu_encoder_phys_is_ppsplit(phys_enc);
-
-	phys_enc->split_role = role;
-
-	DPU_DEBUG_CMDENC(cmd_enc, "old role %d new role %d\n",
-			old_role, role);
-
-	/*
-	 * ppsplit solo needs to reprogram because intf may have swapped without
-	 * role changing on left-only, right-only back-to-back commits
-	 */
-	if (!(is_ppsplit && role == ENC_ROLE_SOLO) &&
-			(role == old_role || role == ENC_ROLE_SKIP))
-		return;
-
-	dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
-	_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
-	_dpu_encoder_phys_cmd_update_flush_mask(phys_enc);
-}
-
 static void dpu_encoder_phys_cmd_prepare_commit(
 		struct dpu_encoder_phys *phys_enc)
 {

@@ -1191,7 +1098,6 @@ static void dpu_encoder_phys_cmd_init_ops(
 	ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
 	ops->hw_reset = dpu_encoder_helper_hw_reset;
 	ops->irq_control = dpu_encoder_phys_cmd_irq_control;
-	ops->update_split_role = dpu_encoder_phys_cmd_update_split_role;
 	ops->restore = dpu_encoder_phys_cmd_enable_helper;
 	ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
 	ops->is_autorefresh_enabled =

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +2 -19

index d6b72a3..b680718 100644
@@ -354,20 +354,6 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
 			phys_enc);
 }
 
-static bool _dpu_encoder_phys_is_ppsplit(struct dpu_encoder_phys *phys_enc)
-{
-	enum dpu_rm_topology_name topology;
-
-	if (!phys_enc)
-		return false;
-
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-		return true;
-
-	return false;
-}
-
 static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 {
 	enum dpu_rm_topology_name topology;

@@ -385,8 +371,7 @@ static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 static bool dpu_encoder_phys_vid_needs_single_flush(
 		struct dpu_encoder_phys *phys_enc)
 {
-	return phys_enc && (_dpu_encoder_phys_is_ppsplit(phys_enc) ||
-		_dpu_encoder_phys_is_dual_ctl(phys_enc));
+	return (phys_enc && _dpu_encoder_phys_is_dual_ctl(phys_enc));
 }
 
 static void _dpu_encoder_phys_vid_setup_irq_hw_idx(

@@ -609,9 +594,7 @@ static int _dpu_encoder_phys_vid_wait_for_vblank(
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 
 	if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
-		/* signal done for slave video encoder, unless it is pp-split */
-		if (!_dpu_encoder_phys_is_ppsplit(phys_enc) &&
-			notify && phys_enc->parent_ops.handle_frame_done)
+		if (notify && phys_enc->parent_ops.handle_frame_done)
 			phys_enc->parent_ops.handle_frame_done(
 					phys_enc->parent, phys_enc,
 					DPU_ENCODER_FRAME_EVENT_DONE);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +2 -3

index 14e66ca..8e779c0 100644
@@ -43,7 +43,7 @@
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
 #define PINGPONG_SDM845_SPLIT_MASK \
-	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_SPLIT) | BIT(DPU_PINGPONG_TE2))
+	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define WB2_SDM845_MASK \
 	(BIT(DPU_WB_LINE_MODE) | BIT(DPU_WB_TRAFFIC_SHAPER) | BIT(DPU_WB_CDP) |\

@@ -119,8 +119,7 @@
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x2000, .len = 0xE4,
-	.features = BIT(DPU_CTL_SPLIT_DISPLAY) |
-		BIT(DPU_CTL_PINGPONG_SPLIT)
+	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +0 -2

index ceff3b7..39bec0a 100644
@@ -214,12 +214,10 @@ enum {
 /**
  * CTL sub-blocks
  * @DPU_CTL_SPLIT_DISPLAY       CTL supports video mode split display
- * @DPU_CTL_PINGPONG_SPLIT      CTL supports pingpong split
  * @DPU_CTL_MAX
  */
 enum {
 	DPU_CTL_SPLIT_DISPLAY = 0x1,
-	DPU_CTL_PINGPONG_SPLIT,
 	DPU_CTL_MAX
 };
 

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +0 -33

index 60e4bef..8f7f932 100644
@@ -80,11 +80,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 				lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
 			else
 				lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
-
-			/* free run */
-			if (cfg->pp_split_slave != INTF_MAX)
-				lower_pipe = FLD_SMART_PANEL_FREE_RUN;
-
 			upper_pipe = lower_pipe;
 		} else {
 			if (cfg->intf == INTF_2) {

@@ -103,33 +98,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 	DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
 }
 
-static void dpu_hw_setup_pp_split(struct dpu_hw_mdp *mdp,
-		struct split_pipe_cfg *cfg)
-{
-	u32 ppb_config = 0x0;
-	u32 ppb_control = 0x0;
-
-	if (!mdp || !cfg)
-		return;
-
-	if (cfg->en && cfg->pp_split_slave != INTF_MAX) {
-		ppb_config |= (cfg->pp_split_slave - INTF_0 + 1) << 20;
-		ppb_config |= BIT(16); /* split enable */
-		ppb_control = BIT(5); /* horz split*/
-	}
-	if (cfg->pp_split_index) {
-		DPU_REG_WRITE(&mdp->hw, PPB0_CONFIG, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB0_CNTL, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CONFIG, ppb_config);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CNTL, ppb_control);
-	} else {
-		DPU_REG_WRITE(&mdp->hw, PPB0_CONFIG, ppb_config);
-		DPU_REG_WRITE(&mdp->hw, PPB0_CNTL, ppb_control);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CONFIG, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CNTL, 0x0);
-	}
-}
-
 static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp,
 		struct cdm_output_cfg *cfg)
 {

@@ -349,7 +317,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
 		unsigned long cap)
 {
 	ops->setup_split_pipe = dpu_hw_setup_split_pipe;
-	ops->setup_pp_split = dpu_hw_setup_pp_split;
 	ops->setup_cdm_output = dpu_hw_setup_cdm_output;
 	ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
 	ops->get_danger_status = dpu_hw_get_danger_status;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h +0 -11

index 1470d0f..5429cd5 100644
@@ -41,8 +41,6 @@ struct traffic_shaper_cfg {
  * @en        : Enable/disable dual pipe confguration
  * @mode      : Panel interface mode
  * @intf      : Interface id for main control path
- * @pp_split_slave: Slave interface for ping pong split, INTF_MAX to disable
- * @pp_split_idx:   Ping pong index for ping pong split
  * @split_flush_en: Allows both the paths to be flushed when master path is
  *              flushed
  */

@@ -50,8 +48,6 @@ struct split_pipe_cfg {
 	bool en;
 	enum dpu_intf_mode mode;
 	enum dpu_intf intf;
-	enum dpu_intf pp_split_slave;
-	u32 pp_split_index;
 	bool split_flush_en;
 };
 

@@ -109,13 +105,6 @@ struct dpu_hw_mdp_ops {
 	void (*setup_split_pipe)(struct dpu_hw_mdp *mdp,
 			struct split_pipe_cfg *p);
 
-	/** setup_pp_split() : Configure pp split related registers
-	 * @mdp  : mdp top context driver
-	 * @cfg  : upper and lower part of pipe configuration
-	 */
-	void (*setup_pp_split)(struct dpu_hw_mdp *mdp,
-			struct split_pipe_cfg *cfg);
-
 	/**
 	 * setup_cdm_output() : Setup selection control of the cdm data path
 	 * @mdp  : mdp top context driver

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h +0 -4

index b887082..5b2bc9b 100644
@@ -36,10 +36,6 @@
 #define DSPP_IGC_COLOR0_RAM_LUTN        0x300
 #define DSPP_IGC_COLOR1_RAM_LUTN        0x304
 #define DSPP_IGC_COLOR2_RAM_LUTN        0x308
-#define PPB0_CNTL                       0x330
-#define PPB0_CONFIG                     0x334
-#define PPB1_CNTL                       0x338
-#define PPB1_CONFIG                     0x33C
 #define HW_EVENTS_CTL                   0x37C
 #define CLK_CTRL3                       0x3A8
 #define CLK_STATUS3                     0x3AC

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +1 -36

index 13efbeb..c8c12d3 100644
@@ -50,7 +50,6 @@ struct dpu_rm_topology_def {
 	{   DPU_RM_TOPOLOGY_SINGLEPIPE,           1, 0, 1, 1, false },
 	{   DPU_RM_TOPOLOGY_DUALPIPE,             2, 0, 2, 2, true  },
 	{   DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,     2, 0, 1, 1, false },
-	{   DPU_RM_TOPOLOGY_PPSPLIT,              1, 0, 2, 1, true  },
 };
 
 /**

@@ -531,7 +530,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm_hw_blk *primary_lm)
 {
 	const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
-	const struct dpu_pingpong_cfg *pp_cfg;
 	struct dpu_rm_hw_iter iter;
 	bool is_valid_dspp, is_valid_ds, ret;
 

@@ -650,15 +648,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		return false;
 	}
 
-	pp_cfg = to_dpu_hw_pingpong((*pp)->hw)->caps;
-	if ((reqs->topology->top_name == DPU_RM_TOPOLOGY_PPSPLIT) &&
-			!(test_bit(DPU_PINGPONG_SPLIT, &pp_cfg->features))) {
-		DPU_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
-		*dspp = NULL;
-		*ds = NULL;
-		return false;
-	}
-
 	return true;
 }
 

@@ -742,26 +731,6 @@ static int _dpu_rm_reserve_lms(
 				ds[i] ? ds[i]->id : 0);
 	}
 
-	if (reqs->topology->top_name == DPU_RM_TOPOLOGY_PPSPLIT) {
-		/* reserve a free PINGPONG_SLAVE block */
-		rc = -ENAVAIL;
-		dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_PINGPONG);
-		while (_dpu_rm_get_hw_locked(rm, &iter_i)) {
-			const struct dpu_hw_pingpong *pp =
-					to_dpu_hw_pingpong(iter_i.blk->hw);
-			const struct dpu_pingpong_cfg *pp_cfg = pp->caps;
-
-			if (!(test_bit(DPU_PINGPONG_SLAVE, &pp_cfg->features)))
-				continue;
-			if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
-				continue;
-
-			iter_i.blk->rsvp_nxt = rsvp;
-			rc = 0;
-			break;
-		}
-	}
-
 	return rc;
 }
 

@@ -780,22 +749,18 @@ static int _dpu_rm_reserve_ctls(
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
 		unsigned long features = ctl->caps->features;
-		bool has_split_display, has_ppsplit;
+		bool has_split_display;
 
 		if (RESERVED_BY_OTHER(iter.blk, rsvp))
 			continue;
 
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
-		has_ppsplit = BIT(DPU_CTL_PINGPONG_SPLIT) & features;
 
 		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
 
 		if (top->needs_split_display != has_split_display)
 			continue;
 
-		if (top->top_name == DPU_RM_TOPOLOGY_PPSPLIT && !has_ppsplit)
-			continue;
-
 		ctls[i] = iter.blk;
 		DPU_DEBUG("ctl %d match\n", iter.blk->id);
 

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +0 -2

index 3db61b5..8a6cbcf 100644
@@ -26,14 +26,12 @@
  * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_PPSPLIT:              1 LM, 2 PPs, 2 INTF/WB
  */
 enum dpu_rm_topology_name {
 	DPU_RM_TOPOLOGY_NONE = 0,
 	DPU_RM_TOPOLOGY_SINGLEPIPE,
 	DPU_RM_TOPOLOGY_DUALPIPE,
 	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
-	DPU_RM_TOPOLOGY_PPSPLIT,
 	DPU_RM_TOPOLOGY_MAX,
 };
 

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Remove autorefresh support for smart panels in SDM845 for now. It needs more discussion to figure out the user space communication to set preference for the feature.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c      |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  37 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 298 +--------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c    |  41 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h    |  18 --
 6 files changed, 11 insertions(+), 410 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c +0 -7

index f7e9f76..dc0978d 100644
@@ -24,9 +24,6 @@
 
 #define BL_NODE_NAME_SIZE 32
 
-/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
-#define AUTOREFRESH_MAX_FRAME_CNT 6
-
 #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
 		(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
 

@@ -1126,10 +1123,6 @@ struct drm_connector *dpu_connector_init(struct drm_device *dev,
 		CONNECTOR_PROP_AD_BL_SCALE);
 #endif
 
-	msm_property_install_range(&c_conn->property_info, "autorefresh",
-			0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
-			CONNECTOR_PROP_AUTOREFRESH);
-
 	/* enum/bitmask properties */
 	msm_property_install_enum(&c_conn->property_info, "topology_name",
 			DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +6 -31

index 32375b1..3004569 100644
@@ -815,7 +815,6 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 		u32 sw_event)
 {
-	bool autorefresh_enabled = false;
 	unsigned int lp, idle_timeout;
 	struct dpu_encoder_virt *dpu_enc;
 	struct msm_drm_private *priv;

@@ -922,13 +921,6 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 			return 0;
 		}
 
-		/* schedule delayed off work if autorefresh is disabled */
-		if (dpu_enc->cur_master &&
-			dpu_enc->cur_master->ops.is_autorefresh_enabled)
-			autorefresh_enabled =
-				dpu_enc->cur_master->ops.is_autorefresh_enabled(
-							dpu_enc->cur_master);
-
 		/* set idle timeout based on master connector's lp value */
 		if (dpu_enc->cur_master)
 			lp = dpu_connector_get_lp(

@@ -941,13 +933,12 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 		else
 			idle_timeout = dpu_enc->idle_timeout;
 
-		if (!autorefresh_enabled)
-			kthread_queue_delayed_work(
-				&disp_thread->worker,
-				&dpu_enc->delayed_off_work,
-				msecs_to_jiffies(idle_timeout));
+		kthread_queue_delayed_work(
+			&disp_thread->worker,
+			&dpu_enc->delayed_off_work,
+			msecs_to_jiffies(idle_timeout));
+
 		DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
-				autorefresh_enabled,
 				idle_timeout, DPU_EVTLOG_FUNC_CASE2);
 		DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
 				sw_event);

@@ -1990,7 +1981,6 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t)
 	struct drm_encoder *drm_enc = &dpu_enc->base;
 	struct msm_drm_private *priv;
 	struct msm_drm_thread *event_thread;
-	bool autorefresh_enabled = false;
 
 	if (!drm_enc->dev || !drm_enc->dev->dev_private ||
 			!drm_enc->crtc) {

@@ -2011,22 +2001,7 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t)
 		return;
 	}
 
-	if (dpu_enc->cur_master &&
-		dpu_enc->cur_master->ops.is_autorefresh_enabled)
-		autorefresh_enabled =
-			dpu_enc->cur_master->ops.is_autorefresh_enabled(
-						dpu_enc->cur_master);
-
-	/*
-	 * Queue work to update the vsync event timer
-	 * if autorefresh is enabled.
-	 */
-	DPU_EVT32_VERBOSE(autorefresh_enabled);
-	if (autorefresh_enabled)
-		kthread_queue_work(&event_thread->worker,
-				&dpu_enc->vsync_event_work);
-	else
-		del_timer(&dpu_enc->vsync_event_timer);
+	del_timer(&dpu_enc->vsync_event_timer);
 }
 
 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +0 -20

index 69ec2b6..d3bfc99 100644
@@ -124,8 +124,6 @@ struct dpu_encoder_virt_ops {
  * @prepare_idle_pc:		phys encoder can update the vsync_enable status
  *                              on idle power collapse prepare
  * @restore:			Restore all the encoder configs.
- * @is_autorefresh_enabled:	provides the autorefresh current
- *                              enable/disable state.
  * @get_line_count:		Obtain current vertical line count
  */
 

@@ -166,7 +164,6 @@ struct dpu_encoder_phys_ops {
 	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
 	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
 	void (*restore)(struct dpu_encoder_phys *phys);
-	bool (*is_autorefresh_enabled)(struct dpu_encoder_phys *phys);
 	int (*get_line_count)(struct dpu_encoder_phys *phys);
 };
 

@@ -176,8 +173,6 @@ struct dpu_encoder_phys_ops {
  * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel
  * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel
  * @INTR_IDX_RDPTR:    Readpointer done unterrupt for cmd mode panel
- * @INTR_IDX_AUTOREFRESH_DONE:  Autorefresh done for cmd mode panel meaning
- *                              autorefresh has triggered a double buffer flip
  */
 enum dpu_intr_idx {
 	INTR_IDX_VSYNC,

@@ -185,7 +180,6 @@ enum dpu_intr_idx {
 	INTR_IDX_UNDERRUN,
 	INTR_IDX_CTL_START,
 	INTR_IDX_RDPTR,
-	INTR_IDX_AUTOREFRESH_DONE,
 	INTR_IDX_MAX,
 };
 

@@ -287,18 +281,6 @@ struct dpu_encoder_phys_vid {
 };
 
 /**
- * struct dpu_encoder_phys_cmd_autorefresh - autorefresh state tracking
- * @cfg: current active autorefresh configuration
- * @kickoff_cnt: atomic count tracking autorefresh done irq kickoffs pending
- * @kickoff_wq:	wait queue for waiting on autorefresh done irq
- */
-struct dpu_encoder_phys_cmd_autorefresh {
-	struct dpu_hw_autorefresh cfg;
-	atomic_t kickoff_cnt;
-	wait_queue_head_t kickoff_wq;
-};
-
-/**
  * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
  *	mode specific operations
  * @base:	Baseclass physical encoder structure

@@ -307,7 +289,6 @@ struct dpu_encoder_phys_cmd_autorefresh {
  * @serialize_wait4pp:	serialize wait4pp feature waits for pp_done interrupt
  *			after ctl_start instead of before next frame kickoff
  * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
- * @autorefresh: autorefresh feature state
  * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
  * @pending_vblank_wq: Wait queue for blocking until VBLANK received
  */

@@ -316,7 +297,6 @@ struct dpu_encoder_phys_cmd {
 	int stream_sel;
 	bool serialize_wait4pp;
 	int pp_timeout_report_cnt;
-	struct dpu_encoder_phys_cmd_autorefresh autorefresh;
 	atomic_t pending_vblank_cnt;
 	wait_queue_head_t pending_vblank_wq;
 };

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +5 -293

index 3436788..072939c 100644
@@ -47,9 +47,7 @@
 static inline int _dpu_encoder_phys_cmd_get_idle_timeout(
 		struct dpu_encoder_phys_cmd *cmd_enc)
 {
-	return cmd_enc->autorefresh.cfg.frame_count ?
-			cmd_enc->autorefresh.cfg.frame_count *
-			KICKOFF_TIMEOUT_MS : KICKOFF_TIMEOUT_MS;
+	return KICKOFF_TIMEOUT_MS;
 }
 
 static inline bool dpu_encoder_phys_cmd_is_master(

@@ -68,52 +66,6 @@ static bool dpu_encoder_phys_cmd_mode_fixup(
 	return true;
 }
 
-static uint64_t _dpu_encoder_phys_cmd_get_autorefresh_property(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct drm_connector *conn = phys_enc->connector;
-
-	if (!conn || !conn->state)
-		return 0;
-
-	return dpu_connector_get_property(conn->state,
-				CONNECTOR_PROP_AUTOREFRESH);
-}
-
-static void _dpu_encoder_phys_cmd_config_autorefresh(
-		struct dpu_encoder_phys *phys_enc,
-		u32 new_frame_count)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc =
-			to_dpu_encoder_phys_cmd(phys_enc);
-	struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
-	struct drm_connector *conn = phys_enc->connector;
-	struct dpu_hw_autorefresh *cfg_cur, cfg_nxt;
-
-	if (!conn || !conn->state || !hw_pp)
-		return;
-
-	cfg_cur = &cmd_enc->autorefresh.cfg;
-
-	/* autorefresh property value should be validated already */
-	memset(&cfg_nxt, 0, sizeof(cfg_nxt));
-	cfg_nxt.frame_count = new_frame_count;
-	cfg_nxt.enable = (cfg_nxt.frame_count != 0);
-
-	DPU_DEBUG_CMDENC(cmd_enc, "autorefresh state %d->%d framecount %d\n",
-			cfg_cur->enable, cfg_nxt.enable, cfg_nxt.frame_count);
-	DPU_EVT32(DRMID(phys_enc->parent), hw_pp->idx, cfg_cur->enable,
-			cfg_nxt.enable, cfg_nxt.frame_count);
-
-	/* only proceed on state changes */
-	if (cfg_nxt.enable == cfg_cur->enable)
-		return;
-
-	memcpy(cfg_cur, &cfg_nxt, sizeof(*cfg_cur));
-	if (hw_pp->ops.setup_autorefresh)
-		hw_pp->ops.setup_autorefresh(hw_pp, cfg_cur);
-}
-
 static void _dpu_encoder_phys_cmd_update_intf_cfg(
 		struct dpu_encoder_phys *phys_enc)
 {

@@ -164,29 +116,6 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
 	DPU_ATRACE_END("pp_done_irq");
 }
 
-static void dpu_encoder_phys_cmd_autorefresh_done_irq(void *arg, int irq_idx)
-{
-	struct dpu_encoder_phys *phys_enc = arg;
-	struct dpu_encoder_phys_cmd *cmd_enc =
-			to_dpu_encoder_phys_cmd(phys_enc);
-	unsigned long lock_flags;
-	int new_cnt;
-
-	if (!cmd_enc)
-		return;
-
-	phys_enc = &cmd_enc->base;
-	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
-	new_cnt = atomic_add_unless(&cmd_enc->autorefresh.kickoff_cnt, -1, 0);
-	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
-
-	DPU_EVT32_IRQ(DRMID(phys_enc->parent),
-			phys_enc->hw_pp->idx - PINGPONG_0, new_cnt);
-
-	/* Signal any waiting atomic commit thread */
-	wake_up_all(&cmd_enc->autorefresh.kickoff_wq);
-}
-
 static void dpu_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx)
 {
 	struct dpu_encoder_phys *phys_enc = arg;

@@ -257,10 +186,6 @@ static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
 	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
 	irq->hw_idx = phys_enc->intf_idx;
 	irq->irq_idx = -EINVAL;
-
-	irq = &phys_enc->irq[INTR_IDX_AUTOREFRESH_DONE];
-	irq->hw_idx = phys_enc->hw_pp->idx;
-	irq->irq_idx = -EINVAL;
 }
 
 static void dpu_encoder_phys_cmd_mode_set(

@@ -352,73 +277,6 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
 	return -ETIMEDOUT;
 }
 
-static int _dpu_encoder_phys_cmd_poll_write_pointer_started(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc =
-			to_dpu_encoder_phys_cmd(phys_enc);
-	struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
-	struct dpu_hw_pp_vsync_info info;
-	u32 timeout_us = DPU_ENC_WR_PTR_START_TIMEOUT_US;
-	int ret;
-
-	if (!hw_pp || !hw_pp->ops.get_vsync_info ||
-			!hw_pp->ops.poll_timeout_wr_ptr)
-		return 0;
-
-	ret = hw_pp->ops.get_vsync_info(hw_pp, &info);
-	if (ret)
-		return ret;
-
-	DPU_DEBUG_CMDENC(cmd_enc,
-			"pp:%d rd_ptr %d wr_ptr %d\n",
-			phys_enc->hw_pp->idx - PINGPONG_0,
-			info.rd_ptr_line_count,
-			info.wr_ptr_line_count);
-	DPU_EVT32_VERBOSE(DRMID(phys_enc->parent),
-			phys_enc->hw_pp->idx - PINGPONG_0,
-			info.wr_ptr_line_count);
-
-	ret = hw_pp->ops.poll_timeout_wr_ptr(hw_pp, timeout_us);
-	if (ret) {
-		DPU_EVT32(DRMID(phys_enc->parent),
-				phys_enc->hw_pp->idx - PINGPONG_0,
-				timeout_us,
-				ret);
-		DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
-	}
-
-	return ret;
-}
-
-static bool _dpu_encoder_phys_cmd_is_ongoing_pptx(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_hw_pingpong *hw_pp;
-	struct dpu_hw_pp_vsync_info info;
-
-	if (!phys_enc)
-		return false;
-
-	hw_pp = phys_enc->hw_pp;
-	if (!hw_pp || !hw_pp->ops.get_vsync_info)
-		return false;
-
-	hw_pp->ops.get_vsync_info(hw_pp, &info);
-
-	DPU_EVT32(DRMID(phys_enc->parent),
-			phys_enc->hw_pp->idx - PINGPONG_0,
-			atomic_read(&phys_enc->pending_kickoff_cnt),
-			info.wr_ptr_line_count,
-			phys_enc->cached_mode.vdisplay);
-
-	if (info.wr_ptr_line_count > 0 && info.wr_ptr_line_count <
-			phys_enc->cached_mode.vdisplay)
-		return true;
-
-	return false;
-}
-
 static int _dpu_encoder_phys_cmd_wait_for_idle(
 		struct dpu_encoder_phys *phys_enc)
 {

@@ -446,42 +304,6 @@ static int _dpu_encoder_phys_cmd_wait_for_idle(
 	return ret;
 }
 
-static int _dpu_encoder_phys_cmd_wait_for_autorefresh_done(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc =
-			to_dpu_encoder_phys_cmd(phys_enc);
-	struct dpu_encoder_wait_info wait_info;
-	int ret = 0;
-
-	if (!phys_enc) {
-		DPU_ERROR("invalid encoder\n");
-		return -EINVAL;
-	}
-
-	/* only master deals with autorefresh */
-	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
-		return 0;
-
-	wait_info.wq = &cmd_enc->autorefresh.kickoff_wq;
-	wait_info.atomic_cnt = &cmd_enc->autorefresh.kickoff_cnt;
-	wait_info.timeout_ms = _dpu_encoder_phys_cmd_get_idle_timeout(cmd_enc);
-
-	/* wait for autorefresh kickoff to start */
-	ret = dpu_encoder_helper_wait_for_irq(phys_enc,
-			INTR_IDX_AUTOREFRESH_DONE, &wait_info);
-
-	/* double check that kickoff has started by reading write ptr reg */
-	if (!ret)
-		ret = _dpu_encoder_phys_cmd_poll_write_pointer_started(
-			phys_enc);
-	else
-		dpu_encoder_helper_report_irq_timeout(phys_enc,
-				INTR_IDX_AUTOREFRESH_DONE);
-
-	return ret;
-}
-
 static int dpu_encoder_phys_cmd_control_vblank_irq(
 		struct dpu_encoder_phys *phys_enc,
 		bool enable)

@@ -550,20 +372,13 @@ void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
 		dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
 		dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
 
-		if (dpu_encoder_phys_cmd_is_master(phys_enc)) {
+		if (dpu_encoder_phys_cmd_is_master(phys_enc))
 			dpu_encoder_helper_register_irq(phys_enc,
 					INTR_IDX_CTL_START);
-			dpu_encoder_helper_register_irq(phys_enc,
-					INTR_IDX_AUTOREFRESH_DONE);
-		}
-
 	} else {
-		if (dpu_encoder_phys_cmd_is_master(phys_enc)) {
+		if (dpu_encoder_phys_cmd_is_master(phys_enc))
 			dpu_encoder_helper_unregister_irq(phys_enc,
 					INTR_IDX_CTL_START);
-			dpu_encoder_helper_unregister_irq(phys_enc,
-					INTR_IDX_AUTOREFRESH_DONE);
-		}
 
 		dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN);
 		dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);

@@ -736,30 +551,6 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc)
 	phys_enc->enable_state = DPU_ENC_ENABLED;
 }
 
-static bool dpu_encoder_phys_cmd_is_autorefresh_enabled(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_hw_pingpong *hw_pp;
-	struct dpu_hw_autorefresh cfg;
-	int ret;
-
-	if (!phys_enc || !phys_enc->hw_pp)
-		return 0;
-
-	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
-		return 0;
-
-	hw_pp = phys_enc->hw_pp;
-	if (!hw_pp->ops.get_autorefresh)
-		return 0;
-
-	ret = hw_pp->ops.get_autorefresh(hw_pp, &cfg);
-	if (ret)
-		return 0;
-
-	return cfg.enable;
-}
-
 static void _dpu_encoder_phys_cmd_connect_te(
 		struct dpu_encoder_phys *phys_enc, bool enable)
 {

@@ -869,8 +660,7 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff(
 	DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 
 	DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
-			atomic_read(&phys_enc->pending_kickoff_cnt),
-			atomic_read(&cmd_enc->autorefresh.kickoff_cnt));
+			atomic_read(&phys_enc->pending_kickoff_cnt));
 
 	/*
 	 * Mark kickoff request as outstanding. If there are more than one,

@@ -954,10 +744,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done(
 	if (dpu_encoder_phys_cmd_is_master(phys_enc))
 		rc = _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
 
-	if (!rc && dpu_encoder_phys_cmd_is_master(phys_enc) &&
-			cmd_enc->autorefresh.cfg.enable)
-		rc = _dpu_encoder_phys_cmd_wait_for_autorefresh_done(phys_enc);
-
 	/* required for both controllers */
 	if (!rc && cmd_enc->serialize_wait4pp)
 		dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc, NULL);

@@ -993,58 +779,6 @@ static int dpu_encoder_phys_cmd_wait_for_vblank(
 	return rc;
 }
 
-static void dpu_encoder_phys_cmd_prepare_commit(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc =
-		to_dpu_encoder_phys_cmd(phys_enc);
-	unsigned long lock_flags;
-
-	if (!phys_enc)
-		return;
-
-	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
-		return;
-
-	DPU_EVT32(DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
-			cmd_enc->autorefresh.cfg.enable);
-
-	if (!dpu_encoder_phys_cmd_is_autorefresh_enabled(phys_enc))
-		return;
-
-	/**
-	 * Autorefresh must be disabled carefully:
-	 *  - Autorefresh must be disabled between pp_done and te
-	 *    signal prior to sdm845 targets. All targets after sdm845
-	 *    supports autorefresh disable without turning off the
-	 *    hardware TE and pp_done wait.
-	 *
-	 *  - Wait for TX to Complete
-	 *    Wait for PPDone confirms the last frame transfer is complete.
-	 *
-	 *  - Leave Autorefresh Disabled
-	 *    - Assume disable of Autorefresh since it is now safe
-	 *    - Can now safely Disable Encoder, do debug printing, etc.
-	 *     without worrying that Autorefresh will kickoff
-	 */
-
-	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
-
-	_dpu_encoder_phys_cmd_config_autorefresh(phys_enc, 0);
-
-	/* check for outstanding TX */
-	if (_dpu_encoder_phys_cmd_is_ongoing_pptx(phys_enc))
-		atomic_add_unless(&phys_enc->pending_kickoff_cnt, 1, 1);
-	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
-
-	/* wait for ppdone if necessary due to catching ongoing TX */
-	if (_dpu_encoder_phys_cmd_wait_for_idle(phys_enc))
-		DPU_ERROR_CMDENC(cmd_enc, "pp:%d kickoff timed out\n",
-				phys_enc->hw_pp->idx - PINGPONG_0);
-
-	DPU_DEBUG_CMDENC(cmd_enc, "disabled autorefresh\n");
-}
-
 static void dpu_encoder_phys_cmd_handle_post_kickoff(
 		struct dpu_encoder_phys *phys_enc)
 {

@@ -1061,27 +795,15 @@ static void dpu_encoder_phys_cmd_handle_post_kickoff(
 static void dpu_encoder_phys_cmd_trigger_start(
 		struct dpu_encoder_phys *phys_enc)
 {
-	struct dpu_encoder_phys_cmd *cmd_enc =
-			to_dpu_encoder_phys_cmd(phys_enc);
-	u32 frame_cnt;
-
 	if (!phys_enc)
 		return;
 
-	/* we don't issue CTL_START when using autorefresh */
-	frame_cnt = _dpu_encoder_phys_cmd_get_autorefresh_property(phys_enc);
-	if (frame_cnt) {
-		_dpu_encoder_phys_cmd_config_autorefresh(phys_enc, frame_cnt);
-		atomic_inc(&cmd_enc->autorefresh.kickoff_cnt);
-	} else {
-		dpu_encoder_helper_trigger_start(phys_enc);
-	}
+	dpu_encoder_helper_trigger_start(phys_enc);
 }
 
 static void dpu_encoder_phys_cmd_init_ops(
 		struct dpu_encoder_phys_ops *ops)
 {
-	ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit;
 	ops->is_master = dpu_encoder_phys_cmd_is_master;
 	ops->mode_set = dpu_encoder_phys_cmd_mode_set;
 	ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup;

@@ -1100,8 +822,6 @@ static void dpu_encoder_phys_cmd_init_ops(
 	ops->irq_control = dpu_encoder_phys_cmd_irq_control;
 	ops->restore = dpu_encoder_phys_cmd_enable_helper;
 	ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
-	ops->is_autorefresh_enabled =
-			dpu_encoder_phys_cmd_is_autorefresh_enabled;
 	ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff;
 	ops->get_line_count = dpu_encoder_phys_cmd_get_line_count;
 }

@@ -1175,20 +895,12 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 	irq->intr_idx = INTR_IDX_UNDERRUN;
 	irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
 
-	irq = &phys_enc->irq[INTR_IDX_AUTOREFRESH_DONE];
-	irq->name = "autorefresh_done";
-	irq->intr_type = DPU_IRQ_TYPE_PING_PONG_AUTO_REF;
-	irq->intr_idx = INTR_IDX_AUTOREFRESH_DONE;
-	irq->cb.func = dpu_encoder_phys_cmd_autorefresh_done_irq;
-
 	atomic_set(&phys_enc->vblank_refcount, 0);
 	atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 	atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
 	atomic_set(&cmd_enc->pending_vblank_cnt, 0);
 	init_waitqueue_head(&phys_enc->pending_kickoff_wq);
 	init_waitqueue_head(&cmd_enc->pending_vblank_wq);
-	atomic_set(&cmd_enc->autorefresh.kickoff_cnt, 0);
-	init_waitqueue_head(&cmd_enc->autorefresh.kickoff_wq);
 
 	DPU_DEBUG_CMDENC(cmd_enc, "created\n");
 

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +0 -41

index 9308f5c..0bfb511 100644
@@ -31,7 +31,6 @@
 #define PP_WR_PTR_IRQ                   0x024
 #define PP_OUT_LINE_COUNT               0x028
 #define PP_LINE_COUNT                   0x02C
-#define PP_AUTOREFRESH_CONFIG           0x030
 
 #define PP_FBC_MODE                     0x034
 #define PP_FBC_BUDGET_CTL               0x038

@@ -93,44 +92,6 @@ static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp,
 	return 0;
 }
 
-static int dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp,
-		struct dpu_hw_autorefresh *cfg)
-{
-	struct dpu_hw_blk_reg_map *c;
-	u32 refresh_cfg;
-
-	if (!pp || !cfg)
-		return -EINVAL;
-	c = &pp->hw;
-
-	if (cfg->enable)
-		refresh_cfg = BIT(31) | cfg->frame_count;
-	else
-		refresh_cfg = 0;
-
-	DPU_REG_WRITE(c, PP_AUTOREFRESH_CONFIG, refresh_cfg);
-	DPU_EVT32(pp->idx - PINGPONG_0, refresh_cfg);
-
-	return 0;
-}
-
-static int dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp,
-		struct dpu_hw_autorefresh *cfg)
-{
-	struct dpu_hw_blk_reg_map *c;
-	u32 val;
-
-	if (!pp || !cfg)
-		return -EINVAL;
-
-	c = &pp->hw;
-	val = DPU_REG_READ(c, PP_AUTOREFRESH_CONFIG);
-	cfg->enable = (val & BIT(31)) >> 31;
-	cfg->frame_count = val & 0xffff;
-
-	return 0;
-}
-
 static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
 		u32 timeout_us)
 {

@@ -293,8 +254,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops,
 	ops->enable_tearcheck = dpu_hw_pp_enable_te;
 	ops->connect_external_te = dpu_hw_pp_connect_external_te;
 	ops->get_vsync_info = dpu_hw_pp_get_vsync_info;
-	ops->setup_autorefresh = dpu_hw_pp_setup_autorefresh_config;
-	ops->get_autorefresh = dpu_hw_pp_get_autorefresh_config;
 	ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
 	ops->get_line_count = dpu_hw_pp_get_line_count;
 

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +0 -18

index 93d03cce..7dbfcae 100644
@@ -36,11 +36,6 @@ struct dpu_hw_tear_check {
 	u8 hw_vsync_mode;
 };
 
-struct dpu_hw_autorefresh {
-	bool  enable;
-	u32 frame_count;
-};
-
 struct dpu_hw_pp_vsync_info {
 	u32 rd_ptr_init_val;	/* value of rd pointer at vsync edge */
 	u32 rd_ptr_frame_count;	/* num frames sent since enabling interface */

@@ -55,7 +50,6 @@ struct dpu_hw_pp_vsync_info {
  *  @setup_tearcheck : program tear check values
  *  @enable_tearcheck : enables tear check
  *  @get_vsync_info : retries timing info of the panel
- *  @setup_autorefresh : program auto refresh
  *  @setup_dither : function to program the dither hw block
  *  @get_line_count: obtain current vertical line counter
  */

@@ -88,18 +82,6 @@ struct dpu_hw_pingpong_ops {
 			struct dpu_hw_pp_vsync_info  *info);
 
 	/**
-	 * configure and enable the autorefresh config
-	 */
-	int (*setup_autorefresh)(struct dpu_hw_pingpong *pp,
-			struct dpu_hw_autorefresh *cfg);
-
-	/**
-	 * retrieve autorefresh config from hardware
-	 */
-	int (*get_autorefresh)(struct dpu_hw_pingpong *pp,
-			struct dpu_hw_autorefresh *cfg);
-
-	/**
 	 * poll until write pointer transmission starts
 	 * @Return: 0 on success, -ETIMEDOUT on timeout
 	 */

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Remove custom ioctl support in SDM845 which allows user space to register/unregister for hw events.

Signed-off-by Jeykumar Sankaran <[email protected]>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 218 +------------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  31 -----
 drivers/gpu/drm/msm/msm_drv.c            | 201 ----------------------------
 drivers/gpu/drm/msm/msm_kms.h            |   2 -
 5 files changed, 1 insertion(+), 452 deletions(-)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +1 -217

index 8e464fa..387919a 100644
@@ -39,31 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
-struct dpu_crtc_irq_info {
-	struct dpu_irq_callback irq;
-	u32 event;
-	int (*func)(struct drm_crtc *crtc, bool en,
-			struct dpu_irq_callback *irq);
-	struct list_head list;
-};
-
-struct dpu_crtc_custom_events {
-	u32 event;
-	int (*func)(struct drm_crtc *crtc, bool en,
-			struct dpu_irq_callback *irq);
-};
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *ad_irq);
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *idle_irq);
-
-static struct dpu_crtc_custom_events custom_events[] = {
-	{DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
-	{DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
-	{DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
-};
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1

@@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 	struct drm_encoder *encoder;
 	struct dpu_crtc_mixer *m;
 	u32 i, misr_status;
-	unsigned long flags;
-	struct dpu_crtc_irq_info *node = NULL;
-	int ret = 0;
 
 	if (!crtc) {
 		DPU_ERROR("invalid crtc\n");

@@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 			dpu_encoder_virt_restore(encoder);
 		}
 
-		spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-		list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-			ret = 0;
-			if (node->func)
-				ret = node->func(crtc, true, &node->irq);
-			if (ret)
-				DPU_ERROR("%s failed to enable event %x\n",
-						dpu_crtc->name, node->event);
-		}
-		spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 		dpu_cp_crtc_post_ipc(crtc);
 
 		for (i = 0; i < dpu_crtc->num_mixers; ++i) {

@@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 							dpu_crtc->misr_data[i];
 		}
 
-		spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-		node = NULL;
-		list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-			ret = 0;
-			if (node->func)
-				ret = node->func(crtc, false, &node->irq);
-			if (ret)
-				DPU_ERROR("%s failed to disable event %x\n",
-						dpu_crtc->name, node->event);
-		}
-		spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 		dpu_cp_crtc_pre_ipc(crtc);
 		break;
 	case DPU_POWER_EVENT_POST_DISABLE:

@@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 	struct drm_display_mode *mode;
 	struct drm_encoder *encoder;
 	struct msm_drm_private *priv;
-	unsigned long flags;
-	struct dpu_crtc_irq_info *node = NULL;
 	struct drm_event event;
 	u32 power_on;
 	int ret;

@@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 		atomic_set(&dpu_crtc->frame_pending, 0);
 	}
 
-	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-	list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-		ret = 0;
-		if (node->func)
-			ret = node->func(crtc, false, &node->irq);
-		if (ret)
-			DPU_ERROR("%s failed to disable event %x\n",
-					dpu_crtc->name, node->event);
-	}
-	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 	dpu_core_perf_crtc_update(crtc, 0, true);
 
 	drm_for_each_encoder(encoder, crtc->dev) {

@@ -2656,8 +2592,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
 	struct dpu_crtc *dpu_crtc;
 	struct drm_encoder *encoder;
 	struct msm_drm_private *priv;
-	unsigned long flags;
-	struct dpu_crtc_irq_info *node = NULL;
 	struct drm_event event;
 	u32 power_on;
 	int ret;

@@ -2709,17 +2643,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
 
 	mutex_unlock(&dpu_crtc->crtc_lock);
 
-	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-	list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-		ret = 0;
-		if (node->func)
-			ret = node->func(crtc, true, &node->irq);
-		if (ret)
-			DPU_ERROR("%s failed to enable event %x\n",
-				dpu_crtc->name, node->event);
-	}
-	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 	dpu_crtc->power_event = dpu_power_handle_register_event(
 		&priv->phandle,
 		DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE |

@@ -3995,7 +3918,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
 	init_completion(&dpu_crtc->frame_done_comp);
 
 	INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
-	INIT_LIST_HEAD(&dpu_crtc->user_event_list);
+
 	for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
 		INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
 		list_add(&dpu_crtc->frame_events[i].list,

@@ -4039,142 +3962,3 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
 	DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
 	return crtc;
 }
-
-static int _dpu_crtc_event_enable(struct dpu_kms *kms,
-		struct drm_crtc *crtc_drm, u32 event)
-{
-	struct dpu_crtc *crtc = NULL;
-	struct dpu_crtc_irq_info *node;
-	struct msm_drm_private *priv;
-	unsigned long flags;
-	bool found = false;
-	int ret, i = 0;
-
-	crtc = to_dpu_crtc(crtc_drm);
-	spin_lock_irqsave(&crtc->spin_lock, flags);
-	list_for_each_entry(node, &crtc->user_event_list, list) {
-		if (node->event == event) {
-			found = true;
-			break;
-		}
-	}
-	spin_unlock_irqrestore(&crtc->spin_lock, flags);
-
-	/* event already enabled */
-	if (found)
-		return 0;
-
-	node = NULL;
-	for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
-		if (custom_events[i].event == event &&
-			custom_events[i].func) {
-			node = kzalloc(sizeof(*node), GFP_KERNEL);
-			if (!node)
-				return -ENOMEM;
-			node->event = event;
-			INIT_LIST_HEAD(&node->list);
-			node->func = custom_events[i].func;
-			node->event = event;
-			break;
-		}
-	}
-
-	if (!node) {
-		DPU_ERROR("unsupported event %x\n", event);
-		return -EINVAL;
-	}
-
-	priv = kms->dev->dev_private;
-	ret = 0;
-	if (crtc_drm->enabled) {
-		dpu_power_resource_enable(&priv->phandle, kms->core_client,
-				true);
-		INIT_LIST_HEAD(&node->irq.list);
-		ret = node->func(crtc_drm, true, &node->irq);
-		dpu_power_resource_enable(&priv->phandle, kms->core_client,
-				false);
-	}
-
-	if (!ret) {
-		spin_lock_irqsave(&crtc->spin_lock, flags);
-		list_add_tail(&node->list, &crtc->user_event_list);
-		spin_unlock_irqrestore(&crtc->spin_lock, flags);
-	} else {
-		kfree(node);
-	}
-
-	return ret;
-}
-
-static int _dpu_crtc_event_disable(struct dpu_kms *kms,
-		struct drm_crtc *crtc_drm, u32 event)
-{
-	struct dpu_crtc *crtc = NULL;
-	struct dpu_crtc_irq_info *node = NULL;
-	struct msm_drm_private *priv;
-	unsigned long flags;
-	bool found = false;
-	int ret;
-
-	crtc = to_dpu_crtc(crtc_drm);
-	spin_lock_irqsave(&crtc->spin_lock, flags);
-	list_for_each_entry(node, &crtc->user_event_list, list) {
-		if (node->event == event) {
-			list_del(&node->list);
-			found = true;
-			break;
-		}
-	}
-	spin_unlock_irqrestore(&crtc->spin_lock, flags);
-
-	/* event already disabled */
-	if (!found)
-		return 0;
-
-	/**
-	 * crtc is disabled interrupts are cleared remove from the list,
-	 * no need to disable/de-register.
-	 */
-	if (!crtc_drm->enabled) {
-		kfree(node);
-		return 0;
-	}
-	priv = kms->dev->dev_private;
-	dpu_power_resource_enable(&priv->phandle, kms->core_client, true);
-	ret = node->func(crtc_drm, false, &node->irq);
-	dpu_power_resource_enable(&priv->phandle, kms->core_client, false);
-	return ret;
-}
-
-int dpu_crtc_register_custom_event(struct dpu_kms *kms,
-		struct drm_crtc *crtc_drm, u32 event, bool en)
-{
-	struct dpu_crtc *crtc = NULL;
-	int ret;
-
-	crtc = to_dpu_crtc(crtc_drm);
-	if (!crtc || !kms || !kms->dev) {
-		DRM_ERROR("invalid dpu_crtc %pK kms %pK dev %pK\n", crtc,
-			kms, ((kms) ? (kms->dev) : NULL));
-		return -EINVAL;
-	}
-
-	if (en)
-		ret = _dpu_crtc_event_enable(kms, crtc_drm, event);
-	else
-		ret = _dpu_crtc_event_disable(kms, crtc_drm, event);
-
-	return ret;
-}
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *irq)
-{
-	return 0;
-}
-
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *irq)
-{
-	return 0;
-}

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +0 -1

index fade658..bc08416 100644
@@ -223,7 +223,6 @@ struct dpu_crtc {
 	struct list_head dirty_list;
 	struct list_head ad_dirty;
 	struct list_head ad_active;
-	struct list_head user_event_list;
 
 	struct mutex crtc_lock;
 

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +0 -31

index 2c187e9..5b07f77 100644
@@ -90,8 +90,6 @@
 
 static int dpu_kms_hw_init(struct msm_kms *kms);
 static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
-static int _dpu_kms_register_events(struct msm_kms *kms,
-		struct drm_mode_object *obj, u32 event, bool en);
 bool dpu_is_custom_client(void)
 {
 	return dpucustom;

@@ -1745,7 +1743,6 @@ static int dpu_kms_pm_resume(struct device *dev)
 	.pm_suspend      = dpu_kms_pm_suspend,
 	.pm_resume       = dpu_kms_pm_resume,
 	.destroy         = dpu_kms_destroy,
-	.register_events = _dpu_kms_register_events,
 	.get_address_space = _dpu_kms_get_address_space,
 	.postopen = _dpu_kms_post_open,
 };

@@ -2159,31 +2156,3 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev)
 	return &dpu_kms->base;
 }
 
-static int _dpu_kms_register_events(struct msm_kms *kms,
-		struct drm_mode_object *obj, u32 event, bool en)
-{
-	int ret = 0;
-	struct drm_crtc *crtc = NULL;
-	struct drm_connector *conn = NULL;
-	struct dpu_kms *dpu_kms = NULL;
-
-	if (!kms || !obj) {
-		DPU_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
-		return -EINVAL;
-	}
-
-	dpu_kms = to_dpu_kms(kms);
-	switch (obj->type) {
-	case DRM_MODE_OBJECT_CRTC:
-		crtc = obj_to_crtc(obj);
-		ret = dpu_crtc_register_custom_event(dpu_kms, crtc, event, en);
-		break;
-	case DRM_MODE_OBJECT_CONNECTOR:
-		conn = obj_to_connector(obj);
-		ret = dpu_connector_register_custom_event(dpu_kms, conn, event,
-				en);
-		break;
-	}
-
-	return ret;
-}

drivers/gpu/drm/msm/msm_drv.c +0 -201

index 5b12e87..a710b63 100644
@@ -1226,180 +1226,6 @@ static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
 	return msm_submitqueue_remove(file->driver_priv, id);
 }
 
-static int msm_drm_object_supports_event(struct drm_device *dev,
-		struct drm_msm_event_req *req, struct drm_file *file)
-{
-	int ret = -EINVAL;
-	struct drm_mode_object *arg_obj;
-
-	arg_obj = drm_mode_object_find(dev, file, req->object_id, req->object_type);
-	if (!arg_obj)
-		return -ENOENT;
-
-	switch (arg_obj->type) {
-	case DRM_MODE_OBJECT_CRTC:
-	case DRM_MODE_OBJECT_CONNECTOR:
-		ret = 0;
-		break;
-	default:
-		ret = -EOPNOTSUPP;
-		break;
-	}
-
-	return ret;
-}
-
-static int msm_register_event(struct drm_device *dev,
-	struct drm_msm_event_req *req, struct drm_file *file, bool en)
-{
-	int ret = -EINVAL;
-	struct msm_drm_private *priv = dev->dev_private;
-	struct msm_kms *kms = priv->kms;
-	struct drm_mode_object *arg_obj;
-
-	arg_obj = drm_mode_object_find(dev, file, req->object_id, req->object_type);
-	if (!arg_obj)
-		return -ENOENT;
-
-	ret = kms->funcs->register_events(kms, arg_obj, req->event, en);
-	return ret;
-}
-
-static int msm_event_client_count(struct drm_device *dev,
-		struct drm_msm_event_req *req_event, bool locked)
-{
-	struct msm_drm_private *priv = dev->dev_private;
-	unsigned long flag = 0;
-	struct msm_drm_event *node;
-	int count = 0;
-
-	if (!locked)
-		spin_lock_irqsave(&dev->event_lock, flag);
-	list_for_each_entry(node, &priv->client_event_list, base.link) {
-		if (node->event.type == req_event->event &&
-			node->info.object_id == req_event->object_id)
-			count++;
-	}
-	if (!locked)
-		spin_unlock_irqrestore(&dev->event_lock, flag);
-
-	return count;
-}
-
-static int msm_ioctl_register_event(struct drm_device *dev, void *data,
-				    struct drm_file *file)
-{
-	struct msm_drm_private *priv = dev->dev_private;
-	struct drm_msm_event_req *req_event = data;
-	struct msm_drm_event *client, *node;
-	unsigned long flag = 0;
-	bool dup_request = false;
-	int ret = 0, count = 0;
-
-	ret = msm_drm_object_supports_event(dev, req_event, file);
-	if (ret) {
-		DRM_ERROR("unsupported event %x object %x object id %d\n",
-			req_event->event, req_event->object_type,
-			req_event->object_id);
-		return ret;
-	}
-
-	spin_lock_irqsave(&dev->event_lock, flag);
-	list_for_each_entry(node, &priv->client_event_list, base.link) {
-		if (node->base.file_priv != file)
-			continue;
-		if (node->event.type == req_event->event &&
-			node->info.object_id == req_event->object_id) {
-			DRM_DEBUG("duplicate request for event %x obj id %d\n",
-				node->event.type, node->info.object_id);
-			dup_request = true;
-			break;
-		}
-	}
-	spin_unlock_irqrestore(&dev->event_lock, flag);
-
-	if (dup_request)
-		return -EALREADY;
-
-	client = kzalloc(sizeof(*client), GFP_KERNEL);
-	if (!client)
-		return -ENOMEM;
-
-	client->base.file_priv = file;
-	client->base.event = &client->event;
-	client->event.type = req_event->event;
-	memcpy(&client->info, req_event, sizeof(client->info));
-
-	/* Get the count of clients that have registered for event.
-	 * Event should be enabled for first client, for subsequent enable
-	 * calls add to client list and return.
-	 */
-	count = msm_event_client_count(dev, req_event, false);
-	/* Add current client to list */
-	spin_lock_irqsave(&dev->event_lock, flag);
-	list_add_tail(&client->base.link, &priv->client_event_list);
-	spin_unlock_irqrestore(&dev->event_lock, flag);
-
-	if (count)
-		return 0;
-
-	ret = msm_register_event(dev, req_event, file, true);
-	if (ret) {
-		DRM_ERROR("failed to enable event %x object %x object id %d\n",
-			req_event->event, req_event->object_type,
-			req_event->object_id);
-		spin_lock_irqsave(&dev->event_lock, flag);
-		list_del(&client->base.link);
-		spin_unlock_irqrestore(&dev->event_lock, flag);
-		kfree(client);
-	}
-	return ret;
-}
-
-static int msm_ioctl_deregister_event(struct drm_device *dev, void *data,
-				      struct drm_file *file)
-{
-	struct msm_drm_private *priv = dev->dev_private;
-	struct drm_msm_event_req *req_event = data;
-	struct msm_drm_event *client = NULL, *node, *temp;
-	unsigned long flag = 0;
-	int count = 0;
-	bool found = false;
-	int ret = 0;
-
-	ret = msm_drm_object_supports_event(dev, req_event, file);
-	if (ret) {
-		DRM_ERROR("unsupported event %x object %x object id %d\n",
-			req_event->event, req_event->object_type,
-			req_event->object_id);
-		return ret;
-	}
-
-	spin_lock_irqsave(&dev->event_lock, flag);
-	list_for_each_entry_safe(node, temp, &priv->client_event_list,
-			base.link) {
-		if (node->event.type == req_event->event &&
-		    node->info.object_id == req_event->object_id &&
-		    node->base.file_priv == file) {
-			client = node;
-			list_del(&client->base.link);
-			found = true;
-			kfree(client);
-			break;
-		}
-	}
-	spin_unlock_irqrestore(&dev->event_lock, flag);
-
-	if (!found)
-		return -ENOENT;
-
-	count = msm_event_client_count(dev, req_event, false);
-	if (!count)
-		ret = msm_register_event(dev, req_event, file, false);
-
-	return ret;
-}
-
 void msm_mode_object_event_notify(struct drm_mode_object *obj,
 		struct drm_device *dev, struct drm_event *event, u8 *payload)
 {

@@ -1452,29 +1278,6 @@ void msm_mode_object_event_notify(struct drm_mode_object *obj,
 
 static int msm_release(struct inode *inode, struct file *filp)
 {
-	struct drm_file *file_priv = filp->private_data;
-	struct drm_minor *minor = file_priv->minor;
-	struct drm_device *dev = minor->dev;
-	struct msm_drm_private *priv = dev->dev_private;
-	struct msm_drm_event *node, *temp;
-	u32 count;
-	unsigned long flags;
-
-	spin_lock_irqsave(&dev->event_lock, flags);
-	list_for_each_entry_safe(node, temp, &priv->client_event_list,
-			base.link) {
-		if (node->base.file_priv != file_priv)
-			continue;
-		list_del(&node->base.link);
-		spin_unlock_irqrestore(&dev->event_lock, flags);
-		count = msm_event_client_count(dev, &node->info, true);
-		if (!count)
-			msm_register_event(dev, &node->info, file_priv, false);
-		kfree(node);
-		spin_lock_irqsave(&dev->event_lock, flags);
-	}
-	spin_unlock_irqrestore(&dev->event_lock, flags);
-
 	return drm_release(inode, filp);
 }
 

@@ -1595,10 +1398,6 @@ int msm_ioctl_rmfb2(struct drm_device *dev, void *data,
 #ifdef CONFIG_DRM_MSM_WRITEBACK
 	DRM_IOCTL_DEF_DRV(DPU_WB_CONFIG, dpu_wb_config, DRM_UNLOCKED|DRM_AUTH),
 #endif
-	DRM_IOCTL_DEF_DRV(MSM_REGISTER_EVENT,  msm_ioctl_register_event,
-			  DRM_UNLOCKED|DRM_CONTROL_ALLOW),
-	DRM_IOCTL_DEF_DRV(MSM_DEREGISTER_EVENT,  msm_ioctl_deregister_event,
-			  DRM_UNLOCKED|DRM_CONTROL_ALLOW),
 	DRM_IOCTL_DEF_DRV(MSM_RMFB2, msm_ioctl_rmfb2,
 			  DRM_CONTROL_ALLOW|DRM_UNLOCKED),
 };

drivers/gpu/drm/msm/msm_kms.h +0 -2

index 25800c0..0ae1deb 100644
@@ -94,8 +94,6 @@ struct msm_kms_funcs {
 	void (*preclose)(struct msm_kms *kms, struct drm_file *file);
 	void (*postclose)(struct msm_kms *kms, struct drm_file *file);
 	void (*lastclose)(struct msm_kms *kms);
-	int (*register_events)(struct msm_kms *kms,
-			struct drm_mode_object *obj, u32 event, bool en);
 	void (*set_encoder_mode)(struct msm_kms *kms,
 				 struct drm_encoder *encoder,
 				 bool cmd_mode);

Signature · 7 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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