Switch DPU to use upstream DSI driver for SDM845

index 36607e3..1237efc 100644
@@ -39,12 +39,8 @@
 static const struct drm_prop_enum_list e_topology_name[] = {
 	{DPU_RM_TOPOLOGY_NONE,	"dpu_none"},
 	{DPU_RM_TOPOLOGY_SINGLEPIPE,	"dpu_singlepipe"},
-	{DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,	"dpu_singlepipe_dsc"},
 	{DPU_RM_TOPOLOGY_DUALPIPE,	"dpu_dualpipe"},
-	{DPU_RM_TOPOLOGY_DUALPIPE_DSC,	"dpu_dualpipe_dsc"},
 	{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,	"dpu_dualpipemerge"},
-	{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,	"dpu_dualpipemerge_dsc"},
-	{DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE,	"dpu_dualpipe_dscmerge"},
 	{DPU_RM_TOPOLOGY_PPSPLIT,	"dpu_ppsplit"},
 };
 static const struct drm_prop_enum_list e_topology_control[] = {

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index e85e5a4..b25619d 100644
@@ -145,20 +145,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder,
 void dpu_encoder_virt_restore(struct drm_encoder *encoder);
 
 /**
- * dpu_encoder_is_dsc_enabled - check if encoder is in DSC mode
- * @drm_enc: Pointer to drm encoder object
- * @Return: true if encoder is in DSC mode
- */
-bool dpu_encoder_is_dsc_enabled(struct drm_encoder *drm_enc);
-
-/**
- * dpu_encoder_is_dsc_merge - check if encoder is in DSC merge mode
- * @drm_enc: Pointer to drm encoder object
- * @Return: true if encoder is in DSC merge mode
- */
-bool dpu_encoder_is_dsc_merge(struct drm_encoder *drm_enc);
-
-/**
  * dpu_encoder_check_mode - check if given mode is supported or not
  * @drm_enc: Pointer to drm encoder object
  * @mode: Mode to be checked

index 9bbf339b..b57f619 100644
@@ -232,7 +232,6 @@ struct dpu_encoder_irq {
  * @split_role:		Role to play in a split-panel configuration
  * @intf_mode:		Interface mode
  * @intf_idx:		Interface index on dpu hardware
- * @comp_type:      Type of compression supported
  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
  * @enable_state:	Enable state tracking
  * @vblank_refcount:	Reference count of vblank request

@@ -262,7 +261,6 @@ struct dpu_encoder_phys {
 	enum dpu_enc_split_role split_role;
 	enum dpu_intf_mode intf_mode;
 	enum dpu_intf intf_idx;
-	enum msm_display_compression_type comp_type;
 	spinlock_t *enc_spinlock;
 	enum dpu_enc_enable_state enable_state;
 	atomic_t vblank_refcount;

@@ -384,7 +382,6 @@ struct dpu_encoder_phys_wb {
  * @split_role:		Role to play in a split-panel configuration
  * @intf_idx:		Interface index this phys_enc will control
  * @wb_idx:		Writeback index this phys_enc will control
- * @comp_type:      Type of compression supported
  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
  */
 struct dpu_enc_phys_init_params {

@@ -394,7 +391,6 @@ struct dpu_enc_phys_init_params {
 	enum dpu_enc_split_role split_role;
 	enum dpu_intf intf_idx;
 	enum dpu_wb wb_idx;
-	enum msm_display_compression_type comp_type;
 	spinlock_t *enc_spinlock;
 };
 

@@ -479,8 +475,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
 
 	topology = dpu_connector_get_topology_name(phys_enc->connector);
 	if (phys_enc->split_role == ENC_ROLE_SOLO &&
-			(topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE ||
-			 topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
+	    topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
 		return BLEND_3D_H_ROW_INT;
 
 	return BLEND_3D_NONE;

index 6ccf378..71e2e5a 100644
@@ -1237,7 +1237,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 	phys_enc->enc_spinlock = p->enc_spinlock;
 	cmd_enc->stream_sel = 0;
 	phys_enc->enable_state = DPU_ENC_DISABLED;
-	phys_enc->comp_type = p->comp_type;
 	for (i = 0; i < INTR_IDX_MAX; i++) {
 		irq = &phys_enc->irq[i];
 		INIT_LIST_HEAD(&irq->cb.list);

index 27ea2b1..d6b72a3 100644
@@ -77,9 +77,6 @@ static void drm_mode_to_intf_timing_params(
 	 * <---------------------------- [hv]total ------------->
 	 */
 	timing->width = mode->hdisplay;	/* active width */
-	if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC)
-		timing->width = DIV_ROUND_UP(timing->width, 3);
-
 	timing->height = mode->vdisplay;	/* active height */
 	timing->xres = timing->width;
 	timing->yres = timing->height;

@@ -379,8 +376,7 @@ static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 		return false;
 
 	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if ((topology == DPU_RM_TOPOLOGY_DUALPIPE_DSC) ||
-		(topology == DPU_RM_TOPOLOGY_DUALPIPE))
+	if (topology == DPU_RM_TOPOLOGY_DUALPIPE)
 		return true;
 
 	return false;

@@ -915,7 +911,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 	phys_enc->split_role = p->split_role;
 	phys_enc->intf_mode = INTF_MODE_VIDEO;
 	phys_enc->enc_spinlock = p->enc_spinlock;
-	phys_enc->comp_type = p->comp_type;
 	for (i = 0; i < INTR_IDX_MAX; i++) {
 		irq = &phys_enc->irq[i];
 		INIT_LIST_HEAD(&irq->cb.list);

index df73148..14e66ca 100644
@@ -380,29 +380,6 @@
 };
 
 /*************************************************************
- * DSC sub blocks config
- *************************************************************/
-
-static struct dpu_dsc_cfg sdm845_dsc[] = {
-	{
-	.name = "dsc_0", .id = DSC_0,
-	.base = 0x81000, .len = 0x140
-	},
-	{
-	.name = "dsc_1", .id = DSC_1,
-	.base = 0x81400, .len = 0x140
-	},
-	{
-	.name = "dsc_2", .id = DSC_2,
-	.base = 0x81800, .len = 0x140
-	},
-	{
-	.name = "dsc_3", .id = DSC_3,
-	.base = 0x81c00, .len = 0x140
-	},
-};
-
-/*************************************************************
  * INTF sub blocks config
  *************************************************************/
 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \

@@ -591,8 +568,6 @@ void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.ds = sdm845_ds,
 		.pingpong_count = ARRAY_SIZE(sdm845_pp),
 		.pingpong = sdm845_pp,
-		.dsc_count = ARRAY_SIZE(sdm845_dsc),
-		.dsc = sdm845_dsc,
 		.cdm_count = ARRAY_SIZE(sdm845_cdm),
 		.cdm = sdm845_cdm,
 		.intf_count = ARRAY_SIZE(sdm845_intf),

index 40d90c3..ceff3b7 100644
@@ -199,7 +199,6 @@ enum {
  * @DPU_PINGPONG_TE2        Additional tear check block for split pipes
  * @DPU_PINGPONG_SPLIT      PP block supports split fifo
  * @DPU_PINGPONG_SLAVE      PP block is a suitable slave for split fifo
- * @DPU_PINGPONG_DSC,       Display stream compression blocks
  * @DPU_PINGPONG_DITHER,    Dither blocks
  * @DPU_PINGPONG_MAX
  */

@@ -208,7 +207,6 @@ enum {
 	DPU_PINGPONG_TE2,
 	DPU_PINGPONG_SPLIT,
 	DPU_PINGPONG_SLAVE,
-	DPU_PINGPONG_DSC,
 	DPU_PINGPONG_DITHER,
 	DPU_PINGPONG_MAX
 };

@@ -489,7 +487,6 @@ struct dpu_dspp_sub_blks {
 struct dpu_pingpong_sub_blks {
 	struct dpu_pp_blk te;
 	struct dpu_pp_blk te2;
-	struct dpu_pp_blk dsc;
 	struct dpu_pp_blk dither;
 };
 

@@ -671,16 +668,6 @@ struct dpu_pingpong_cfg  {
 };
 
 /**
- * struct dpu_dsc_cfg - information of DSC blocks
- * @id                 enum identifying this block
- * @base               register offset of this block
- * @features           bit mask identifying sub-blocks/features
- */
-struct dpu_dsc_cfg {
-	DPU_HW_BLK_INFO;
-};
-
-/**
  * struct dpu_cdm_cfg - information of chroma down blocks
  * @id                 enum identifying this block
  * @base               register offset of this block

@@ -916,9 +903,6 @@ struct dpu_mdss_cfg {
 	u32 pingpong_count;
 	struct dpu_pingpong_cfg *pingpong;
 
-	u32 dsc_count;
-	struct dpu_dsc_cfg *dsc;
-
 	u32 cdm_count;
 	struct dpu_cdm_cfg *cdm;
 

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index 5ede2b5..70d57c9 100644
@@ -106,7 +106,6 @@ enum dpu_hw_blk_type {
 	DPU_HW_BLK_PINGPONG,
 	DPU_HW_BLK_INTF,
 	DPU_HW_BLK_WB,
-	DPU_HW_BLK_DSC,
 	DPU_HW_BLK_MAX,
 };
 

@@ -208,17 +207,6 @@ enum dpu_pingpong {
 	PINGPONG_MAX
 };
 
-enum dpu_dsc {
-	DSC_NONE = 0,
-	DSC_0,
-	DSC_1,
-	DSC_2,
-	DSC_3,
-	DSC_4,
-	DSC_5,
-	DSC_MAX
-};
-
 enum dpu_intf {
 	INTF_0 = 1,
 	INTF_1,

@@ -482,9 +470,8 @@ struct dpu_mdss_color {
 #define DPU_DBG_MASK_WB       (1 << 8)
 #define DPU_DBG_MASK_TOP      (1 << 9)
 #define DPU_DBG_MASK_VBIF     (1 << 10)
-#define DPU_DBG_MASK_DSC      (1 << 11)
-#define DPU_DBG_MASK_ROT      (1 << 12)
-#define DPU_DBG_MASK_DS       (1 << 13)
+#define DPU_DBG_MASK_ROT      (1 << 11)
+#define DPU_DBG_MASK_DS       (1 << 12)
 
 /**
  * struct dpu_hw_cp_cfg: hardware dspp/lm feature payload.

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index 7987ee6..93d03cce 100644
@@ -48,10 +48,6 @@ struct dpu_hw_pp_vsync_info {
 	u32 wr_ptr_line_count;	/* current line within pp fifo (wr ptr) */
 };
 
-struct dpu_hw_dsc_cfg {
-	u8 enable;
-};
-
 /**
  *
  * struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions

@@ -60,9 +56,6 @@ struct dpu_hw_dsc_cfg {
  *  @enable_tearcheck : enables tear check
  *  @get_vsync_info : retries timing info of the panel
  *  @setup_autorefresh : program auto refresh
- *  @setup_dsc : program DSC block with encoding details
- *  @enable_dsc : enables DSC encoder
- *  @disable_dsc : disables DSC encoder
  *  @setup_dither : function to program the dither hw block
  *  @get_line_count: obtain current vertical line counter
  */

@@ -113,21 +106,6 @@ struct dpu_hw_pingpong_ops {
 	int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us);
 
 	/**
-	 * Program the dsc compression block
-	 */
-	int (*setup_dsc)(struct dpu_hw_pingpong *pp);
-
-	/**
-	 * Enables DSC encoder
-	 */
-	void (*enable_dsc)(struct dpu_hw_pingpong *pp);
-
-	/**
-	 * Disables DSC encoder
-	 */
-	void (*disable_dsc)(struct dpu_hw_pingpong *pp);
-
-	/**
 	 * Program the dither hw block
 	 */
 	int (*setup_dither)(struct dpu_hw_pingpong *pp, void *cfg, size_t len);

index 68163a1..60e4bef 100644
@@ -317,18 +317,6 @@ static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
 	status->wb[WB_3] = 0;
 }
 
-static void dpu_hw_setup_dce(struct dpu_hw_mdp *mdp, u32 dce_sel)
-{
-	struct dpu_hw_blk_reg_map *c;
-
-	if (!mdp)
-		return;
-
-	c = &mdp->hw;
-
-	DPU_REG_WRITE(c, DCE_SEL, dce_sel);
-}
-
 void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
 {
 	struct dpu_hw_blk_reg_map c;

@@ -367,7 +355,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
 	ops->get_danger_status = dpu_hw_get_danger_status;
 	ops->setup_vsync_source = dpu_hw_setup_vsync_source;
 	ops->get_safe_status = dpu_hw_get_safe_status;
-	ops->setup_dce = dpu_hw_setup_dce;
 	ops->reset_ubwc = dpu_hw_reset_ubwc;
 	ops->intf_audio_select = dpu_hw_intf_audio_select;
 }

index 375cb7c..1470d0f 100644
@@ -143,13 +143,6 @@ struct dpu_hw_mdp_ops {
 			enum dpu_clk_ctrl_type clk_ctrl, bool enable);
 
 	/**
-	 * setup_dce - set DCE mux for DSC ctrl path
-	 * @mdp: mdp top context driver
-	 * @dce_sel: dce_mux value
-	 */
-	void (*setup_dce)(struct dpu_hw_mdp *mdp, u32 dce_sel);
-
-	/**
 	 * get_danger_status - get danger status
 	 * @mdp: mdp top context driver
 	 * @status: Pointer to danger safe status

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index 22a681c..3db61b5 100644
@@ -24,23 +24,15 @@
  * enum dpu_rm_topology_name - HW resource use case in use by connector
  * @DPU_RM_TOPOLOGY_NONE:                 No topology in use currently
  * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_SINGLEPIPE_DSC:       1 LM, 1 DSC, 1 PP, 1 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE_DSC:         2 LM, 2 DSC, 2 PP, 2 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC: 2 LM, 2 PP, 3DMux, 1 DSC, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE:    2 LM, 2 PP, 2 DSC Merge, 1 INTF/WB
  * @DPU_RM_TOPOLOGY_PPSPLIT:              1 LM, 2 PPs, 2 INTF/WB
  */
 enum dpu_rm_topology_name {
 	DPU_RM_TOPOLOGY_NONE = 0,
 	DPU_RM_TOPOLOGY_SINGLEPIPE,
-	DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,
 	DPU_RM_TOPOLOGY_DUALPIPE,
-	DPU_RM_TOPOLOGY_DUALPIPE_DSC,
 	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
-	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,
-	DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE,
 	DPU_RM_TOPOLOGY_PPSPLIT,
 	DPU_RM_TOPOLOGY_MAX,
 };

index 0bb07ee..cc78786 100644
@@ -307,8 +307,6 @@ int dpu_wb_get_mode_info(const struct drm_display_mode *drm_mode,
 	topology->num_enc = no_enc;
 	topology->num_intf = single_intf;
 
-	mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
-
 	return 0;
 }
 

index 017f881..2e742a3 100644
@@ -322,13 +322,6 @@ int dsi_conn_get_mode_info(const struct drm_display_mode *drm_mode,
 	memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
 			sizeof(struct msm_display_topology));
 
-	mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
-	if (dsi_mode.priv_info->dsc_enabled) {
-		mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
-		memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
-			sizeof(dsi_mode.priv_info->dsc));
-	}
-
 	return 0;
 }
 

index 4ee40f8..f98c4ef 100644
@@ -319,20 +319,6 @@ struct msm_display_dsc_info {
 };
 
 /**
- * struct msm_compression_info - defined panel compression
- * @comp_type:        type of compression supported
- * @dsc_info:         dsc configuration if the compression
- *                    supported is DSC
- */
-struct msm_compression_info {
-	enum msm_display_compression_type comp_type;
-
-	union{
-		struct msm_display_dsc_info dsc_info;
-	};
-};
-
-/**
  * struct msm_display_topology - defines a display topology pipeline
  * @num_lm:       number of layer mixers used
  * @num_enc:      number of compression encoder blocks used

@@ -352,7 +338,6 @@ struct msm_display_topology {
  * @jitter_numer:	display panel jitter numerator configuration
  * @jitter_denom:	display panel jitter denominator configuration
  * @topology:        supported topology for the mode
- * @comp_info:       compression info supported
  */
 struct msm_mode_info {
 	uint32_t frame_rate;

@@ -361,7 +346,6 @@ struct msm_mode_info {
 	uint32_t jitter_numer;
 	uint32_t jitter_denom;
 	struct msm_display_topology topology;
-	struct msm_compression_info comp_info;
 };
 
 /**

index 1237efc..f7e9f76 100644
@@ -41,8 +41,8 @@
 	{DPU_RM_TOPOLOGY_SINGLEPIPE,	"dpu_singlepipe"},
 	{DPU_RM_TOPOLOGY_DUALPIPE,	"dpu_dualpipe"},
 	{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,	"dpu_dualpipemerge"},
-	{DPU_RM_TOPOLOGY_PPSPLIT,	"dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
 	{DPU_RM_TOPCTL_RESERVE_LOCK,	"reserve_lock"},
 	{DPU_RM_TOPCTL_RESERVE_CLEAR,	"reserve_clear"},

index 516458e..8e464fa 100644
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
 	mutex_unlock(&dpu_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-	int i;
-	struct dpu_crtc_state *cstate;
-
-	cstate = to_dpu_crtc_state(state);
-
-	cstate->is_ppsplit = false;
-	for (i = 0; i < cstate->num_connectors; i++) {
-		struct drm_connector *conn = cstate->connectors[i];
-
-		if (dpu_connector_get_topology_name(conn) ==
-				DPU_RM_TOPOLOGY_PPSPLIT)
-			cstate->is_ppsplit = true;
-	}
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {

@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
 	if (!dpu_crtc->num_mixers) {
 		_dpu_crtc_setup_mixers(crtc);
-		_dpu_crtc_setup_is_ppsplit(crtc->state);
 		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
 	}
 

@@ -2901,7 +2883,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 	mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-	_dpu_crtc_setup_is_ppsplit(state);
 	_dpu_crtc_setup_lm_bounds(crtc, state);
 
 	 /* get plane state for all drm planes associated with crtc state */

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index b57f619..911ac6d 100644
@@ -40,13 +40,11 @@
  * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
  * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
  * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
- * @ENC_ROLE_SKIP:	This encoder is not participating in kickoffs
  */
 enum dpu_enc_split_role {
 	ENC_ROLE_SOLO,
 	ENC_ROLE_MASTER,
 	ENC_ROLE_SLAVE,
-	ENC_ROLE_SKIP
 };
 
 /**

@@ -123,7 +121,6 @@ struct dpu_encoder_virt_ops {
  * @hw_reset:			Issue HW recovery such as CTL reset and clear
  *				DPU_ENC_ERR_NEEDS_HW_RESET state
  * @irq_control:		Handler to enable/disable all the encoder IRQs
- * @update_split_role:		Update the split role of the phys enc
  * @prepare_idle_pc:		phys encoder can update the vsync_enable status
  *                              on idle power collapse prepare
  * @restore:			Restore all the encoder configs.

@@ -167,8 +164,6 @@ struct dpu_encoder_phys_ops {
 	u32 (*collect_misr)(struct dpu_encoder_phys *phys_enc);
 	void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
 	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
-	void (*update_split_role)(struct dpu_encoder_phys *phys_enc,
-			enum dpu_enc_split_role role);
 	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
 	void (*restore)(struct dpu_encoder_phys *phys);
 	bool (*is_autorefresh_enabled)(struct dpu_encoder_phys *phys);

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index d6b72a3..b680718 100644
@@ -354,20 +354,6 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
 			phys_enc);
 }
 
-static bool _dpu_encoder_phys_is_ppsplit(struct dpu_encoder_phys *phys_enc)
-{
-	enum dpu_rm_topology_name topology;
-
-	if (!phys_enc)
-		return false;
-
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-		return true;
-
-	return false;
-}
-
 static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 {
 	enum dpu_rm_topology_name topology;

@@ -385,8 +371,7 @@ static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 static bool dpu_encoder_phys_vid_needs_single_flush(
 		struct dpu_encoder_phys *phys_enc)
 {
-	return phys_enc && (_dpu_encoder_phys_is_ppsplit(phys_enc) ||
-		_dpu_encoder_phys_is_dual_ctl(phys_enc));
+	return (phys_enc && _dpu_encoder_phys_is_dual_ctl(phys_enc));
 }
 
 static void _dpu_encoder_phys_vid_setup_irq_hw_idx(

@@ -609,9 +594,7 @@ static int _dpu_encoder_phys_vid_wait_for_vblank(
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 
 	if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
-		/* signal done for slave video encoder, unless it is pp-split */
-		if (!_dpu_encoder_phys_is_ppsplit(phys_enc) &&
-			notify && phys_enc->parent_ops.handle_frame_done)
+		if (notify && phys_enc->parent_ops.handle_frame_done)
 			phys_enc->parent_ops.handle_frame_done(
 					phys_enc->parent, phys_enc,
 					DPU_ENCODER_FRAME_EVENT_DONE);

index 14e66ca..8e779c0 100644
@@ -43,7 +43,7 @@
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
 #define PINGPONG_SDM845_SPLIT_MASK \
-	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_SPLIT) | BIT(DPU_PINGPONG_TE2))
+	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define WB2_SDM845_MASK \
 	(BIT(DPU_WB_LINE_MODE) | BIT(DPU_WB_TRAFFIC_SHAPER) | BIT(DPU_WB_CDP) |\

@@ -119,8 +119,7 @@
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x2000, .len = 0xE4,
-	.features = BIT(DPU_CTL_SPLIT_DISPLAY) |
-		BIT(DPU_CTL_PINGPONG_SPLIT)
+	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,

index ceff3b7..39bec0a 100644
@@ -214,12 +214,10 @@ enum {
 /**
  * CTL sub-blocks
  * @DPU_CTL_SPLIT_DISPLAY       CTL supports video mode split display
- * @DPU_CTL_PINGPONG_SPLIT      CTL supports pingpong split
  * @DPU_CTL_MAX
  */
 enum {
 	DPU_CTL_SPLIT_DISPLAY = 0x1,
-	DPU_CTL_PINGPONG_SPLIT,
 	DPU_CTL_MAX
 };
 

index 60e4bef..8f7f932 100644
@@ -80,11 +80,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 				lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
 			else
 				lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
-
-			/* free run */
-			if (cfg->pp_split_slave != INTF_MAX)
-				lower_pipe = FLD_SMART_PANEL_FREE_RUN;
-
 			upper_pipe = lower_pipe;
 		} else {
 			if (cfg->intf == INTF_2) {

@@ -103,33 +98,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 	DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
 }
 
-static void dpu_hw_setup_pp_split(struct dpu_hw_mdp *mdp,
-		struct split_pipe_cfg *cfg)
-{
-	u32 ppb_config = 0x0;
-	u32 ppb_control = 0x0;
-
-	if (!mdp || !cfg)
-		return;
-
-	if (cfg->en && cfg->pp_split_slave != INTF_MAX) {
-		ppb_config |= (cfg->pp_split_slave - INTF_0 + 1) << 20;
-		ppb_config |= BIT(16); /* split enable */
-		ppb_control = BIT(5); /* horz split*/
-	}
-	if (cfg->pp_split_index) {
-		DPU_REG_WRITE(&mdp->hw, PPB0_CONFIG, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB0_CNTL, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CONFIG, ppb_config);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CNTL, ppb_control);
-	} else {
-		DPU_REG_WRITE(&mdp->hw, PPB0_CONFIG, ppb_config);
-		DPU_REG_WRITE(&mdp->hw, PPB0_CNTL, ppb_control);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CONFIG, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CNTL, 0x0);
-	}
-}
-
 static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp,
 		struct cdm_output_cfg *cfg)
 {

@@ -349,7 +317,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
 		unsigned long cap)
 {
 	ops->setup_split_pipe = dpu_hw_setup_split_pipe;
-	ops->setup_pp_split = dpu_hw_setup_pp_split;
 	ops->setup_cdm_output = dpu_hw_setup_cdm_output;
 	ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
 	ops->get_danger_status = dpu_hw_get_danger_status;

index 1470d0f..5429cd5 100644
@@ -41,8 +41,6 @@ struct traffic_shaper_cfg {
  * @en        : Enable/disable dual pipe confguration
  * @mode      : Panel interface mode
  * @intf      : Interface id for main control path
- * @pp_split_slave: Slave interface for ping pong split, INTF_MAX to disable
- * @pp_split_idx:   Ping pong index for ping pong split
  * @split_flush_en: Allows both the paths to be flushed when master path is
  *              flushed
  */

@@ -50,8 +48,6 @@ struct split_pipe_cfg {
 	bool en;
 	enum dpu_intf_mode mode;
 	enum dpu_intf intf;
-	enum dpu_intf pp_split_slave;
-	u32 pp_split_index;
 	bool split_flush_en;
 };
 

@@ -109,13 +105,6 @@ struct dpu_hw_mdp_ops {
 	void (*setup_split_pipe)(struct dpu_hw_mdp *mdp,
 			struct split_pipe_cfg *p);
 
-	/** setup_pp_split() : Configure pp split related registers
-	 * @mdp  : mdp top context driver
-	 * @cfg  : upper and lower part of pipe configuration
-	 */
-	void (*setup_pp_split)(struct dpu_hw_mdp *mdp,
-			struct split_pipe_cfg *cfg);
-
 	/**
 	 * setup_cdm_output() : Setup selection control of the cdm data path
 	 * @mdp  : mdp top context driver

index b887082..5b2bc9b 100644
@@ -36,10 +36,6 @@
 #define DSPP_IGC_COLOR0_RAM_LUTN        0x300
 #define DSPP_IGC_COLOR1_RAM_LUTN        0x304
 #define DSPP_IGC_COLOR2_RAM_LUTN        0x308
-#define PPB0_CNTL                       0x330
-#define PPB0_CONFIG                     0x334
-#define PPB1_CNTL                       0x338
-#define PPB1_CONFIG                     0x33C
 #define HW_EVENTS_CTL                   0x37C
 #define CLK_CTRL3                       0x3A8
 #define CLK_STATUS3                     0x3AC

index 13efbeb..c8c12d3 100644
@@ -50,7 +50,6 @@ struct dpu_rm_topology_def {
 	{   DPU_RM_TOPOLOGY_SINGLEPIPE,           1, 0, 1, 1, false },
 	{   DPU_RM_TOPOLOGY_DUALPIPE,             2, 0, 2, 2, true  },
 	{   DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,     2, 0, 1, 1, false },
-	{   DPU_RM_TOPOLOGY_PPSPLIT,              1, 0, 2, 1, true  },
 };
 
 /**

@@ -531,7 +530,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm_hw_blk *primary_lm)
 {
 	const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
-	const struct dpu_pingpong_cfg *pp_cfg;
 	struct dpu_rm_hw_iter iter;
 	bool is_valid_dspp, is_valid_ds, ret;
 

@@ -650,15 +648,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		return false;
 	}
 
-	pp_cfg = to_dpu_hw_pingpong((*pp)->hw)->caps;
-	if ((reqs->topology->top_name == DPU_RM_TOPOLOGY_PPSPLIT) &&
-			!(test_bit(DPU_PINGPONG_SPLIT, &pp_cfg->features))) {
-		DPU_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
-		*dspp = NULL;
-		*ds = NULL;
-		return false;
-	}
-
 	return true;
 }
 

@@ -742,26 +731,6 @@ static int _dpu_rm_reserve_lms(
 				ds[i] ? ds[i]->id : 0);
 	}
 
-	if (reqs->topology->top_name == DPU_RM_TOPOLOGY_PPSPLIT) {
-		/* reserve a free PINGPONG_SLAVE block */
-		rc = -ENAVAIL;
-		dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_PINGPONG);
-		while (_dpu_rm_get_hw_locked(rm, &iter_i)) {
-			const struct dpu_hw_pingpong *pp =
-					to_dpu_hw_pingpong(iter_i.blk->hw);
-			const struct dpu_pingpong_cfg *pp_cfg = pp->caps;
-
-			if (!(test_bit(DPU_PINGPONG_SLAVE, &pp_cfg->features)))
-				continue;
-			if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
-				continue;
-
-			iter_i.blk->rsvp_nxt = rsvp;
-			rc = 0;
-			break;
-		}
-	}
-
 	return rc;
 }
 

@@ -780,22 +749,18 @@ static int _dpu_rm_reserve_ctls(
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
 		unsigned long features = ctl->caps->features;
-		bool has_split_display, has_ppsplit;
+		bool has_split_display;
 
 		if (RESERVED_BY_OTHER(iter.blk, rsvp))
 			continue;
 
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
-		has_ppsplit = BIT(DPU_CTL_PINGPONG_SPLIT) & features;
 
 		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
 
 		if (top->needs_split_display != has_split_display)
 			continue;
 
-		if (top->top_name == DPU_RM_TOPOLOGY_PPSPLIT && !has_ppsplit)
-			continue;
-
 		ctls[i] = iter.blk;
 		DPU_DEBUG("ctl %d match\n", iter.blk->id);
 

index 3db61b5..8a6cbcf 100644
@@ -26,14 +26,12 @@
  * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_PPSPLIT:              1 LM, 2 PPs, 2 INTF/WB
  */
 enum dpu_rm_topology_name {
 	DPU_RM_TOPOLOGY_NONE = 0,
 	DPU_RM_TOPOLOGY_SINGLEPIPE,
 	DPU_RM_TOPOLOGY_DUALPIPE,
 	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
-	DPU_RM_TOPOLOGY_PPSPLIT,
 	DPU_RM_TOPOLOGY_MAX,
 };
 

index f7e9f76..dc0978d 100644
@@ -24,9 +24,6 @@
 
 #define BL_NODE_NAME_SIZE 32
 
-/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
-#define AUTOREFRESH_MAX_FRAME_CNT 6
-
 #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
 		(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
 

@@ -1126,10 +1123,6 @@ struct drm_connector *dpu_connector_init(struct drm_device *dev,
 		CONNECTOR_PROP_AD_BL_SCALE);
 #endif
 
-	msm_property_install_range(&c_conn->property_info, "autorefresh",
-			0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
-			CONNECTOR_PROP_AUTOREFRESH);
-
 	/* enum/bitmask properties */
 	msm_property_install_enum(&c_conn->property_info, "topology_name",
 			DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,

index d04095b..3854410 100644
@@ -813,7 +813,6 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 		u32 sw_event)
 {
-	bool autorefresh_enabled = false;
 	unsigned int lp, idle_timeout;
 	struct dpu_encoder_virt *dpu_enc;
 	struct msm_drm_private *priv;

@@ -920,13 +919,6 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 			return 0;
 		}
 
-		/* schedule delayed off work if autorefresh is disabled */
-		if (dpu_enc->cur_master &&
-			dpu_enc->cur_master->ops.is_autorefresh_enabled)
-			autorefresh_enabled =
-				dpu_enc->cur_master->ops.is_autorefresh_enabled(
-							dpu_enc->cur_master);
-
 		/* set idle timeout based on master connector's lp value */
 		if (dpu_enc->cur_master)
 			lp = dpu_connector_get_lp(

@@ -939,13 +931,12 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 		else
 			idle_timeout = dpu_enc->idle_timeout;
 
-		if (!autorefresh_enabled)
-			kthread_queue_delayed_work(
-				&disp_thread->worker,
-				&dpu_enc->delayed_off_work,
-				msecs_to_jiffies(idle_timeout));
+		kthread_queue_delayed_work(
+			&disp_thread->worker,
+			&dpu_enc->delayed_off_work,
+			msecs_to_jiffies(idle_timeout));
+
 		DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
-				autorefresh_enabled,
 				idle_timeout, DPU_EVTLOG_FUNC_CASE2);
 		DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
 				sw_event);

@@ -1988,7 +1979,6 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t)
 	struct drm_encoder *drm_enc = &dpu_enc->base;
 	struct msm_drm_private *priv;
 	struct msm_drm_thread *event_thread;
-	bool autorefresh_enabled = false;
 
 	if (!drm_enc->dev || !drm_enc->dev->dev_private ||
 			!drm_enc->crtc) {

@@ -2009,22 +1999,7 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t)
 		return;
 	}
 
-	if (dpu_enc->cur_master &&
-		dpu_enc->cur_master->ops.is_autorefresh_enabled)
-		autorefresh_enabled =
-			dpu_enc->cur_master->ops.is_autorefresh_enabled(
-						dpu_enc->cur_master);
-
-	/*
-	 * Queue work to update the vsync event timer
-	 * if autorefresh is enabled.
-	 */
-	DPU_EVT32_VERBOSE(autorefresh_enabled);
-	if (autorefresh_enabled)
-		kthread_queue_work(&event_thread->worker,
-				&dpu_enc->vsync_event_work);
-	else
-		del_timer(&dpu_enc->vsync_event_timer);
+	del_timer(&dpu_enc->vsync_event_timer);
 }
 
 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)

index 911ac6d..576c475 100644
@@ -124,8 +124,6 @@ struct dpu_encoder_virt_ops {
  * @prepare_idle_pc:		phys encoder can update the vsync_enable status
  *                              on idle power collapse prepare
  * @restore:			Restore all the encoder configs.
- * @is_autorefresh_enabled:	provides the autorefresh current
- *                              enable/disable state.
  * @get_line_count:		Obtain current vertical line count
  */
 

@@ -166,7 +164,6 @@ struct dpu_encoder_phys_ops {
 	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
 	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
 	void (*restore)(struct dpu_encoder_phys *phys);
-	bool (*is_autorefresh_enabled)(struct dpu_encoder_phys *phys);
 	int (*get_line_count)(struct dpu_encoder_phys *phys);
 };
 

@@ -176,8 +173,6 @@ struct dpu_encoder_phys_ops {
  * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel
  * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel
  * @INTR_IDX_RDPTR:    Readpointer done unterrupt for cmd mode panel
- * @INTR_IDX_AUTOREFRESH_DONE:  Autorefresh done for cmd mode panel meaning
- *                              autorefresh has triggered a double buffer flip
  */
 enum dpu_intr_idx {
 	INTR_IDX_VSYNC,

@@ -185,7 +180,6 @@ enum dpu_intr_idx {
 	INTR_IDX_UNDERRUN,
 	INTR_IDX_CTL_START,
 	INTR_IDX_RDPTR,
-	INTR_IDX_AUTOREFRESH_DONE,
 	INTR_IDX_MAX,
 };
 

@@ -287,18 +281,6 @@ struct dpu_encoder_phys_vid {
 };
 
 /**
- * struct dpu_encoder_phys_cmd_autorefresh - autorefresh state tracking
- * @cfg: current active autorefresh configuration
- * @kickoff_cnt: atomic count tracking autorefresh done irq kickoffs pending
- * @kickoff_wq:	wait queue for waiting on autorefresh done irq
- */
-struct dpu_encoder_phys_cmd_autorefresh {
-	struct dpu_hw_autorefresh cfg;
-	atomic_t kickoff_cnt;
-	wait_queue_head_t kickoff_wq;
-};
-
-/**
  * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
  *	mode specific operations
  * @base:	Baseclass physical encoder structure

@@ -307,7 +289,6 @@ struct dpu_encoder_phys_cmd_autorefresh {
  * @serialize_wait4pp:	serialize wait4pp feature waits for pp_done interrupt
  *			after ctl_start instead of before next frame kickoff
  * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
- * @autorefresh: autorefresh feature state
  * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
  * @pending_vblank_wq: Wait queue for blocking until VBLANK received
  */

@@ -316,7 +297,6 @@ struct dpu_encoder_phys_cmd {
 	int stream_sel;
 	bool serialize_wait4pp;
 	int pp_timeout_report_cnt;
-	struct dpu_encoder_phys_cmd_autorefresh autorefresh;
 	atomic_t pending_vblank_cnt;
 	wait_queue_head_t pending_vblank_wq;
 };

401 lines not on this page · raw message

59 lines not on this page · raw message

index 93d03cce..7dbfcae 100644
@@ -36,11 +36,6 @@ struct dpu_hw_tear_check {
 	u8 hw_vsync_mode;
 };
 
-struct dpu_hw_autorefresh {
-	bool  enable;
-	u32 frame_count;
-};
-
 struct dpu_hw_pp_vsync_info {
 	u32 rd_ptr_init_val;	/* value of rd pointer at vsync edge */
 	u32 rd_ptr_frame_count;	/* num frames sent since enabling interface */

@@ -55,7 +50,6 @@ struct dpu_hw_pp_vsync_info {
  *  @setup_tearcheck : program tear check values
  *  @enable_tearcheck : enables tear check
  *  @get_vsync_info : retries timing info of the panel
- *  @setup_autorefresh : program auto refresh
  *  @setup_dither : function to program the dither hw block
  *  @get_line_count: obtain current vertical line counter
  */

@@ -88,18 +82,6 @@ struct dpu_hw_pingpong_ops {
 			struct dpu_hw_pp_vsync_info  *info);
 
 	/**
-	 * configure and enable the autorefresh config
-	 */
-	int (*setup_autorefresh)(struct dpu_hw_pingpong *pp,
-			struct dpu_hw_autorefresh *cfg);
-
-	/**
-	 * retrieve autorefresh config from hardware
-	 */
-	int (*get_autorefresh)(struct dpu_hw_pingpong *pp,
-			struct dpu_hw_autorefresh *cfg);
-
-	/**
 	 * poll until write pointer transmission starts
 	 * @Return: 0 on success, -ETIMEDOUT on timeout
 	 */

index 8e464fa..387919a 100644
@@ -39,31 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
-struct dpu_crtc_irq_info {
-	struct dpu_irq_callback irq;
-	u32 event;
-	int (*func)(struct drm_crtc *crtc, bool en,
-			struct dpu_irq_callback *irq);
-	struct list_head list;
-};
-
-struct dpu_crtc_custom_events {
-	u32 event;
-	int (*func)(struct drm_crtc *crtc, bool en,
-			struct dpu_irq_callback *irq);
-};
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *ad_irq);
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *idle_irq);
-
-static struct dpu_crtc_custom_events custom_events[] = {
-	{DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
-	{DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
-	{DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
-};
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1

@@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 	struct drm_encoder *encoder;
 	struct dpu_crtc_mixer *m;
 	u32 i, misr_status;
-	unsigned long flags;
-	struct dpu_crtc_irq_info *node = NULL;
-	int ret = 0;
 
 	if (!crtc) {
 		DPU_ERROR("invalid crtc\n");

@@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 			dpu_encoder_virt_restore(encoder);
 		}
 
-		spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-		list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-			ret = 0;
-			if (node->func)
-				ret = node->func(crtc, true, &node->irq);
-			if (ret)
-				DPU_ERROR("%s failed to enable event %x\n",
-						dpu_crtc->name, node->event);
-		}
-		spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 		dpu_cp_crtc_post_ipc(crtc);
 
 		for (i = 0; i < dpu_crtc->num_mixers; ++i) {

@@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 							dpu_crtc->misr_data[i];
 		}
 
-		spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-		node = NULL;
-		list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-			ret = 0;
-			if (node->func)
-				ret = node->func(crtc, false, &node->irq);
-			if (ret)
-				DPU_ERROR("%s failed to disable event %x\n",
-						dpu_crtc->name, node->event);
-		}
-		spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 		dpu_cp_crtc_pre_ipc(crtc);
 		break;
 	case DPU_POWER_EVENT_POST_DISABLE:

@@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 	struct drm_display_mode *mode;
 	struct drm_encoder *encoder;
 	struct msm_drm_private *priv;
-	unsigned long flags;
-	struct dpu_crtc_irq_info *node = NULL;
 	struct drm_event event;
 	u32 power_on;
 	int ret;

@@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 		atomic_set(&dpu_crtc->frame_pending, 0);
 	}
 
-	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-	list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-		ret = 0;
-		if (node->func)
-			ret = node->func(crtc, false, &node->irq);
-		if (ret)
-			DPU_ERROR("%s failed to disable event %x\n",
-					dpu_crtc->name, node->event);
-	}
-	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 	dpu_core_perf_crtc_update(crtc, 0, true);
 
 	drm_for_each_encoder(encoder, crtc->dev) {

@@ -2656,8 +2592,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
 	struct dpu_crtc *dpu_crtc;
 	struct drm_encoder *encoder;
 	struct msm_drm_private *priv;
-	unsigned long flags;
-	struct dpu_crtc_irq_info *node = NULL;
 	struct drm_event event;
 	u32 power_on;
 	int ret;

@@ -2709,17 +2643,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
 
 	mutex_unlock(&dpu_crtc->crtc_lock);
 
-	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
-	list_for_each_entry(node, &dpu_crtc->user_event_list, list) {
-		ret = 0;
-		if (node->func)
-			ret = node->func(crtc, true, &node->irq);
-		if (ret)
-			DPU_ERROR("%s failed to enable event %x\n",
-				dpu_crtc->name, node->event);
-	}
-	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
-
 	dpu_crtc->power_event = dpu_power_handle_register_event(
 		&priv->phandle,
 		DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE |

@@ -3995,7 +3918,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
 	init_completion(&dpu_crtc->frame_done_comp);
 
 	INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
-	INIT_LIST_HEAD(&dpu_crtc->user_event_list);
+
 	for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
 		INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
 		list_add(&dpu_crtc->frame_events[i].list,

@@ -4039,142 +3962,3 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
 	DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
 	return crtc;
 }
-
-static int _dpu_crtc_event_enable(struct dpu_kms *kms,
-		struct drm_crtc *crtc_drm, u32 event)
-{
-	struct dpu_crtc *crtc = NULL;
-	struct dpu_crtc_irq_info *node;
-	struct msm_drm_private *priv;
-	unsigned long flags;
-	bool found = false;
-	int ret, i = 0;
-
-	crtc = to_dpu_crtc(crtc_drm);
-	spin_lock_irqsave(&crtc->spin_lock, flags);
-	list_for_each_entry(node, &crtc->user_event_list, list) {
-		if (node->event == event) {
-			found = true;
-			break;
-		}
-	}
-	spin_unlock_irqrestore(&crtc->spin_lock, flags);
-
-	/* event already enabled */
-	if (found)
-		return 0;
-
-	node = NULL;
-	for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
-		if (custom_events[i].event == event &&
-			custom_events[i].func) {
-			node = kzalloc(sizeof(*node), GFP_KERNEL);
-			if (!node)
-				return -ENOMEM;
-			node->event = event;
-			INIT_LIST_HEAD(&node->list);
-			node->func = custom_events[i].func;
-			node->event = event;
-			break;
-		}
-	}
-
-	if (!node) {
-		DPU_ERROR("unsupported event %x\n", event);
-		return -EINVAL;
-	}
-
-	priv = kms->dev->dev_private;
-	ret = 0;
-	if (crtc_drm->enabled) {
-		dpu_power_resource_enable(&priv->phandle, kms->core_client,
-				true);
-		INIT_LIST_HEAD(&node->irq.list);
-		ret = node->func(crtc_drm, true, &node->irq);
-		dpu_power_resource_enable(&priv->phandle, kms->core_client,
-				false);
-	}
-
-	if (!ret) {
-		spin_lock_irqsave(&crtc->spin_lock, flags);
-		list_add_tail(&node->list, &crtc->user_event_list);
-		spin_unlock_irqrestore(&crtc->spin_lock, flags);
-	} else {
-		kfree(node);
-	}
-
-	return ret;
-}
-
-static int _dpu_crtc_event_disable(struct dpu_kms *kms,
-		struct drm_crtc *crtc_drm, u32 event)
-{
-	struct dpu_crtc *crtc = NULL;
-	struct dpu_crtc_irq_info *node = NULL;
-	struct msm_drm_private *priv;
-	unsigned long flags;
-	bool found = false;
-	int ret;
-
-	crtc = to_dpu_crtc(crtc_drm);
-	spin_lock_irqsave(&crtc->spin_lock, flags);
-	list_for_each_entry(node, &crtc->user_event_list, list) {
-		if (node->event == event) {
-			list_del(&node->list);
-			found = true;
-			break;
-		}
-	}
-	spin_unlock_irqrestore(&crtc->spin_lock, flags);
-
-	/* event already disabled */
-	if (!found)
-		return 0;
-
-	/**
-	 * crtc is disabled interrupts are cleared remove from the list,
-	 * no need to disable/de-register.
-	 */
-	if (!crtc_drm->enabled) {
-		kfree(node);
-		return 0;
-	}
-	priv = kms->dev->dev_private;
-	dpu_power_resource_enable(&priv->phandle, kms->core_client, true);
-	ret = node->func(crtc_drm, false, &node->irq);
-	dpu_power_resource_enable(&priv->phandle, kms->core_client, false);
-	return ret;
-}
-
-int dpu_crtc_register_custom_event(struct dpu_kms *kms,
-		struct drm_crtc *crtc_drm, u32 event, bool en)
-{
-	struct dpu_crtc *crtc = NULL;
-	int ret;
-
-	crtc = to_dpu_crtc(crtc_drm);
-	if (!crtc || !kms || !kms->dev) {
-		DRM_ERROR("invalid dpu_crtc %pK kms %pK dev %pK\n", crtc,
-			kms, ((kms) ? (kms->dev) : NULL));
-		return -EINVAL;
-	}
-
-	if (en)
-		ret = _dpu_crtc_event_enable(kms, crtc_drm, event);
-	else
-		ret = _dpu_crtc_event_disable(kms, crtc_drm, event);
-
-	return ret;
-}
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *irq)
-{
-	return 0;
-}
-
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-	bool en, struct dpu_irq_callback *irq)
-{
-	return 0;
-}

index 8756b2b..9304058 100644
@@ -223,7 +223,6 @@ struct dpu_crtc {
 	struct list_head dirty_list;
 	struct list_head ad_dirty;
 	struct list_head ad_active;
-	struct list_head user_event_list;
 
 	struct mutex crtc_lock;
 

index f6fea21..57d808d 100644
@@ -90,8 +90,6 @@
 
 static int dpu_kms_hw_init(struct msm_kms *kms);
 static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
-static int _dpu_kms_register_events(struct msm_kms *kms,
-		struct drm_mode_object *obj, u32 event, bool en);
 bool dpu_is_custom_client(void)
 {
 	return dpucustom;

@@ -1745,7 +1743,6 @@ static int dpu_kms_pm_resume(struct device *dev)
 	.pm_suspend      = dpu_kms_pm_suspend,
 	.pm_resume       = dpu_kms_pm_resume,
 	.destroy         = dpu_kms_destroy,
-	.register_events = _dpu_kms_register_events,
 	.get_address_space = _dpu_kms_get_address_space,
 	.postopen = _dpu_kms_post_open,
 };

@@ -2162,31 +2159,3 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev)
 	return &dpu_kms->base;
 }
 
-static int _dpu_kms_register_events(struct msm_kms *kms,
-		struct drm_mode_object *obj, u32 event, bool en)
-{
-	int ret = 0;
-	struct drm_crtc *crtc = NULL;
-	struct drm_connector *conn = NULL;
-	struct dpu_kms *dpu_kms = NULL;
-
-	if (!kms || !obj) {
-		DPU_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
-		return -EINVAL;
-	}
-
-	dpu_kms = to_dpu_kms(kms);
-	switch (obj->type) {
-	case DRM_MODE_OBJECT_CRTC:
-		crtc = obj_to_crtc(obj);
-		ret = dpu_crtc_register_custom_event(dpu_kms, crtc, event, en);
-		break;
-	case DRM_MODE_OBJECT_CONNECTOR:
-		conn = obj_to_connector(obj);
-		ret = dpu_connector_register_custom_event(dpu_kms, conn, event,
-				en);
-		break;
-	}
-
-	return ret;
-}

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index 25800c0..0ae1deb 100644
@@ -94,8 +94,6 @@ struct msm_kms_funcs {
 	void (*preclose)(struct msm_kms *kms, struct drm_file *file);
 	void (*postclose)(struct msm_kms *kms, struct drm_file *file);
 	void (*lastclose)(struct msm_kms *kms);
-	int (*register_events)(struct msm_kms *kms,
-			struct drm_mode_object *obj, u32 event, bool en);
 	void (*set_encoder_mode)(struct msm_kms *kms,
 				 struct drm_encoder *encoder,
 				 bool cmd_mode);

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index 387919a..ad195d5 100644
@@ -33,7 +33,6 @@
 #include "dpu_plane.h"
 #include "dpu_color_processing.h"
 #include "dpu_encoder.h"
-#include "dpu_connector.h"
 #include "dpu_vbif.h"
 #include "dpu_power_handle.h"
 #include "dpu_core_perf.h"

@@ -3359,7 +3358,6 @@ static int dpu_crtc_atomic_get_property(struct drm_crtc *crtc,
 	struct dpu_crtc_state *cstate;
 	struct drm_encoder *encoder;
 	int i, ret = -EINVAL;
-	bool conn_offset = 0;
 	bool is_cmd = true;
 
 	if (!crtc || !state) {

@@ -3368,13 +3366,6 @@ static int dpu_crtc_atomic_get_property(struct drm_crtc *crtc,
 		dpu_crtc = to_dpu_crtc(crtc);
 		cstate = to_dpu_crtc_state(state);
 
-		for (i = 0; i < cstate->num_connectors; ++i) {
-			conn_offset = dpu_connector_needs_offset(
-						cstate->connectors[i]);
-			if (conn_offset)
-				break;
-		}
-
 		/**
 		 * set the cmd flag only when all the encoders attached
 		 * to the crtc are in cmd mode. Consider all other cases

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index b25619d..d853ad9 100644
@@ -45,7 +45,6 @@ struct dpu_encoder_hw_resources {
 	enum dpu_intf_mode wbs[WB_MAX];
 	bool needs_cdm;
 	u32 display_num_of_h_tiles;
-	struct msm_display_topology topology;
 };
 
 /**

@@ -160,6 +159,15 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder,
  */
 struct drm_encoder *dpu_encoder_init(
 		struct drm_device *dev,
+		int drm_enc_mode);
+
+/**
+ * dpu_encoder_setup - setup dpu_encoder for the display probed
+ * @dev:		Pointer to drm device structure
+ * @enc:		Pointer to the drm_encoder
+ * @disp_info:	Pointer to the display info
+ */
+int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
 		struct msm_display_info *disp_info);
 
 /**

index 576c475..35beefa 100644
@@ -25,7 +25,6 @@
 #include "dpu_hw_wb.h"
 #include "dpu_hw_cdm.h"
 #include "dpu_encoder.h"
-#include "dpu_connector.h"
 
 #define DPU_ENCODER_NAME_MAX	16
 

@@ -221,6 +220,7 @@ struct dpu_encoder_irq {
  * @split_role:		Role to play in a split-panel configuration
  * @intf_mode:		Interface mode
  * @intf_idx:		Interface index on dpu hardware
+ * @topology_name:	topology selected for the display
  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
  * @enable_state:	Enable state tracking
  * @vblank_refcount:	Reference count of vblank request

@@ -250,6 +250,7 @@ struct dpu_encoder_phys {
 	enum dpu_enc_split_role split_role;
 	enum dpu_intf_mode intf_mode;
 	enum dpu_intf intf_idx;
+	enum dpu_rm_topology_name topology_name;
 	spinlock_t *enc_spinlock;
 	enum dpu_enc_enable_state enable_state;
 	atomic_t vblank_refcount;

@@ -443,14 +444,11 @@ int dpu_encoder_helper_wait_event_timeout(
 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
 		struct dpu_encoder_phys *phys_enc)
 {
-	enum dpu_rm_topology_name topology;
-
 	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
 		return BLEND_3D_NONE;
 
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
 	if (phys_enc->split_role == ENC_ROLE_SOLO &&
-	    topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
+	    phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
 		return BLEND_3D_H_ROW_INT;
 
 	return BLEND_3D_NONE;

index b680718..73e5938 100644
@@ -15,7 +15,6 @@
 #include "dpu_hw_interrupts.h"
 #include "dpu_core_irq.h"
 #include "dpu_formats.h"
-#include "dsi_display.h"
 #include "dpu_trace.h"
 
 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \

@@ -356,13 +355,10 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
 
 static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 {
-	enum dpu_rm_topology_name topology;
-
 	if (!phys_enc)
 		return false;
 
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_DUALPIPE)
+	if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
 		return true;
 
 	return false;

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index a14c26d..eb3521e 100644
@@ -200,12 +200,6 @@ struct dpu_kms {
 
 	struct dpu_hw_vbif *hw_vbif[VBIF_MAX];
 	struct dpu_hw_mdp *hw_mdp;
-	int dsi_display_count;
-	void **dsi_displays;
-	int wb_display_count;
-	void **wb_displays;
-	int dp_display_count;
-	void **dp_displays;
 
 	bool has_danger_ctrl;
 };

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index 8a6cbcf..4c77874 100644
@@ -128,6 +128,7 @@ int dpu_rm_init(struct dpu_rm *rm,
  * @drm_enc: DRM Encoder handle
  * @crtc_state: Proposed Atomic DRM CRTC State handle
  * @conn_state: Proposed Atomic DRM Connector State handle
+ * @topology: Pointer to topology info for the display
  * @test_only: Atomic-Test phase, discard results (unless property overrides)
  * @Return: 0 on Success otherwise -ERROR
  */

@@ -135,6 +136,7 @@ int dpu_rm_reserve(struct dpu_rm *rm,
 		struct drm_encoder *drm_enc,
 		struct drm_crtc_state *crtc_state,
 		struct drm_connector_state *conn_state,
+		struct msm_display_topology topology,
 		bool test_only);
 
 /**

@@ -187,4 +189,13 @@ void dpu_rm_init_hw_iter(
  */
 int dpu_rm_check_property_topctl(uint64_t val);
 
+/**
+ * dpu_rm_get_topology_name - returns the name of the the given topology
+ *                            definition
+ * @topology: topology definition
+ * @Return: name of the topology
+ */
+enum dpu_rm_topology_name
+dpu_rm_get_topology_name(struct msm_display_topology topology);
+
 #endif /* __DPU_RM_H__ */

index 341b596..5c62339 100644
@@ -2545,9 +2545,6 @@ static void _dpu_dump_array(struct dpu_dbg_reg_base *blk_arr[],
 	if (dump_dbgbus_vbif_rt)
 		_dpu_dbg_dump_vbif_dbg_bus(&dpu_dbg_base.dbgbus_vbif_rt);
 
-	if (dpu_dbg_base.dsi_dbg_bus || dump_all)
-		dsi_ctrl_debug_dump();
-
 	if (do_panic && dpu_dbg_base.panic_on_err)
 		panic(name);
 }

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