Add Intel Stratix 10 SoC support

Add the base address map for Statix10 SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38 ++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +26 -0

new file mode 100644
index 0000000..e18d2bf
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +1 -0

+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Quoted 48 lines · Ley Foon Tan

Add the base address map for Statix10 SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38
++++++++++++++++++++

 1 files changed, 38 insertions(+), 0 deletions(-)

 create mode 100644 arch/arm/mach-
socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +29 -0

new file mode 100644
index 0000000..e18d2bf
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200

arch/arm/mach-socfpga/include/mach/base_addr_s10.h line 36

Quoted 7 lines

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +7 -0

+#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
+#define SOCFPGA_FIREWALL_TCU			0xffd21400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+#define GICD_BASE				0xfffc1000
+#define GICC_BASE				0xfffc2000

How much of this can come from DT ?

Quoted 49 lines · Marek Vasut

Quoted 48 lines · Ley Foon Tan

Add the base address map for Statix10 SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38
++++++++++++++++++++

 1 files changed, 38 insertions(+), 0 deletions(-)

 create mode 100644 arch/arm/mach-
socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +29 -0

new file mode 100644
index 0000000..e18d2bf
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200

Quoted 9 lines

arch/arm/mach-socfpga/include/mach/base_addr_s10.h line 36

Quoted 7 lines

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +7 -0

+#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
+#define SOCFPGA_FIREWALL_TCU			0xffd21400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+#define GICD_BASE				0xfffc1000
+#define GICC_BASE				0xfffc2000

How much of this can come from DT ?

Just found out Dinh already upstreamed this patch. BTW, we will try to use DT when it is possible.

Add CONFIG_SYS_L2_PL310 conditional build.

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/misc.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

arch/arm/mach-socfpga/misc.c +4 -0

index 692466c..01f824c 100644
@@ -23,8 +23,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_L2_PL310
 static const struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
 
 struct bsel bsel_str[] = {
 	{ "rsvd", "Reserved", },

@@ -53,6 +55,7 @@ void enable_caches(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
 	/* Disable the L2 cache */

@@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
 	/* Disable the L2 cache */
 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 }
+#endif
 
 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)

Quoted 2 lines · Ley Foon Tan

Add CONFIG_SYS_L2_PL310 conditional build.

Why ?

Quoted 5 lines · Marek Vasut

Quoted 2 lines · Ley Foon Tan

Add CONFIG_SYS_L2_PL310 conditional build.

Why ?

In ARM64, L2 cache controller is accessed through processor registers. Hence we shall make this conditional in order this file can be shared across SOCFPGAs.

Quoted 7 lines · Chin Liang

Quoted 5 lines · Marek Vasut

Quoted 2 lines · Ley Foon Tan

Add CONFIG_SYS_L2_PL310 conditional build.

Why ?

Quoted 3 lines

In ARM64, L2 cache controller is accessed through processor registers. Hence we shall make this conditional in order this file can be shared across SOCFPGAs.

That should be in the patch description .
Do you ever add the PL310 register access on S10 later in the set?

--

Quoted 12 lines · Marek Vasut

Quoted 10 lines · Chin Liang

Quoted 5 lines · Marek Vasut

Quoted 2 lines · Ley Foon Tan

Add CONFIG_SYS_L2_PL310 conditional build.

Why ?

In ARM64, L2 cache controller is accessed through processor registers. Hence we shall make this conditional in order this file can be shared across SOCFPGAs.

Quoted 4 lines

That should be in the patch description .
Do you ever add the PL310 register access on S10 later in the set?

--

Okay, will update description.
No, S10 doesn't use PL310 registers.

Quoted 17 lines · Ley Foon Tan

Quoted 16 lines · Marek Vasut

Quoted 10 lines · Chin Liang

Quoted 5 lines · Marek Vasut

Quoted 2 lines · Ley Foon Tan

Add CONFIG_SYS_L2_PL310 conditional build.

Why ?

In ARM64, L2 cache controller is accessed through processor registers. Hence we shall make this conditional in order this file can be shared across SOCFPGAs.

That should be in the patch description .
Do you ever add the PL310 register access on S10 later in the set?

--

Quoted 2 lines

Okay, will update description.
No, S10 doesn't use PL310 registers.

If this PL310 is Gen5 specific, then keep it in some Gen5 file.

--
Best regards,
Marek Vasut.

Move eth reset to common misc driver so can used by other device families.

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

Quoted 4 lines · Ley Foon Tan

Move eth reset to common misc driver so can used by other device families.

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

Shouldn't this use the reset framework instead ?

Quoted 8 lines · Marek Vasut

Quoted 4 lines · Ley Foon Tan

Move eth reset to common misc driver so can used by other device families.

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

Shouldn't this use the reset framework instead ?

What reset framework you refer to? drivers/reset?

Quoted 7 lines · Ley Foon Tan

Quoted 6 lines · Marek Vasut

Quoted 4 lines · Ley Foon Tan

Move eth reset to common misc driver so can used by other device families.

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

Quoted 3 lines

Quoted 2 lines

Shouldn't this use the reset framework instead ?

What reset framework you refer to? drivers/reset?

I think so, there were patches from Dinh earlier this month
2ac718821a | Dinh Nguyen | reset: socfpga: add reset driver for
SoCFPGA platform

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/Makefile   |    1 +
 arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index 910eb6f..b253914 100644
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= misc_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o

arch/arm/mach-socfpga/misc_s10.c new file +21 -0

new file mode 100644
index 0000000..b1cc6ca
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+#include <linux/libfdt.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>

arch/arm/mach-socfpga/misc_s10.c new file +14 -0

+void dwmac_deassert_reset(const unsigned int of_reset_id,
+			  const u32 phymode)
+{
+	/* Put the emac we're using into reset.
+	 * This is required before configuring the PHY interface
+	 */
+	socfpga_emac_manage_reset(of_reset_id, 1);
+
+	clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
+			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+			phymode);
+
+	socfpga_emac_manage_reset(of_reset_id, 0);
+}

arch/arm/mach-socfpga/misc_s10.c new file +9 -0

+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	char qspi_string[13];
+

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;

arch/arm/mach-socfpga/misc_s10.c new file +13 -0

+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(bridge, 2, 1, do_bridge,
+	   "SoCFPGA HPS FPGA bridge control",
+	   "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   ""
+);

Quoted 53 lines · Ley Foon Tan

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/Makefile   |    1 +
 arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index 910eb6f..b253914 100644
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y        += clock_manager_s10.o
+obj-y        += misc_s10.o
 obj-y        += reset_manager_s10.o
 obj-y        += system_manager_s10.o
 obj-y        += wrap_pinmux_config_s10.o

arch/arm/mach-socfpga/misc_s10.c new file +25 -0

new file mode 100644
index 0000000..b1cc6ca
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+#include <linux/libfdt.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =

arch/arm/mach-socfpga/misc_s10.c line 31

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE

Use the reset framework ? Talk to Dinh if in doubt

Quoted 19 lines

arch/arm/mach-socfpga/misc_s10.c new file +18 -0

+void dwmac_deassert_reset(const unsigned int of_reset_id,
+                       const u32 phymode)
+{
+     /* Put the emac we're using into reset.
+      * This is required before configuring the PHY interface
+      */
+     socfpga_emac_manage_reset(of_reset_id, 1);
+
+     clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
+                     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+                     phymode);
+
+     socfpga_emac_manage_reset(of_reset_id, 0);
+}
+#endif
+
+/*
+ * Print CPU information

arch/arm/mach-socfpga/misc_s10.c line 55

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+     puts("CPU:   Intel FPGA SoCFPGA Platform\n");
+     puts("FPGA:  Intel FPGA Stratix 10\n");

This can well come from DT.

Quoted 14 lines

arch/arm/mach-socfpga/misc_s10.c new file +13 -0

+     return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+     char qspi_string[13];
+
+     sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
+     env_set("qspi_clock", qspi_string);
+
+     return socfpga_eth_reset();

arch/arm/mach-socfpga/misc_s10.c line 74

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+}
+#endif
+
+int arch_early_init_r(void)
+{
+     return 0;

Needed ?

Quoted 11 lines

arch/arm/mach-socfpga/misc_s10.c new file +10 -0

+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+     if (argc != 2)
+             return CMD_RET_USAGE;
+
+     argv++;
+
+     switch (*argv[0]) {

arch/arm/mach-socfpga/misc_s10.c line 90

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+     case 'e':       /* Enable */
+             socfpga_bridges_reset(1);
+             break;
+     case 'd':       /* Disable */
+             socfpga_bridges_reset(0);
+             break;

Do you really need to duplicate this command ?

Quoted 5 lines

arch/arm/mach-socfpga/misc_s10.c new file +3 -0

+     default:
+             return CMD_RET_USAGE;
+     }

arch/arm/mach-socfpga/misc_s10.c line 103

Quoted 10 lines

arch/arm/mach-socfpga/misc_s10.c new file +10 -0

+
+     return 0;
+}
+
+U_BOOT_CMD(bridge, 2, 1, do_bridge,
+        "SoCFPGA HPS FPGA bridge control",
+        "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+        "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+        ""
+);

Quoted 54 lines · Marek Vasut

Quoted 53 lines · Ley Foon Tan

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/Makefile   |    1 +
 arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index 910eb6f..b253914 100644
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y        += clock_manager_s10.o
+obj-y        += misc_s10.o
 obj-y        += reset_manager_s10.o
 obj-y        += system_manager_s10.o
 obj-y        += wrap_pinmux_config_s10.o

arch/arm/mach-socfpga/misc_s10.c new file +25 -0

new file mode 100644
index 0000000..b1cc6ca
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+#include <linux/libfdt.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =

Quoted 8 lines

arch/arm/mach-socfpga/misc_s10.c line 31

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE

Use the reset framework ? Talk to Dinh if in doubt

Yes, will convert this to reset framework. Will send out separate patches to convert device drivers to use reset framework.

Quoted 18 lines

Quoted 18 lines

arch/arm/mach-socfpga/misc_s10.c new file +18 -0

+void dwmac_deassert_reset(const unsigned int of_reset_id,
+                       const u32 phymode)
+{
+     /* Put the emac we're using into reset.
+      * This is required before configuring the PHY interface
+      */
+     socfpga_emac_manage_reset(of_reset_id, 1);
+
+     clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
+                     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+                     phymode);
+
+     socfpga_emac_manage_reset(of_reset_id, 0);
+}
+#endif
+
+/*
+ * Print CPU information

Quoted 8 lines

arch/arm/mach-socfpga/misc_s10.c line 55

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+     puts("CPU:   Intel FPGA SoCFPGA Platform\n");
+     puts("FPGA:  Intel FPGA Stratix 10\n");

This can well come from DT.

DT only contains the "model" and this is already display in common/board_info.c:show_board_info().
So, will use simple puts here for the CPU info, unless we want add new DT property.

Below is example output from console, model is retrieved from DT.

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK

Quoted 13 lines

Quoted 13 lines

arch/arm/mach-socfpga/misc_s10.c new file +13 -0

+     return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+     char qspi_string[13];
+
+     sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
+     env_set("qspi_clock", qspi_string);
+
+     return socfpga_eth_reset();

Quoted 8 lines

arch/arm/mach-socfpga/misc_s10.c line 74

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+}
+#endif
+
+int arch_early_init_r(void)
+{
+     return 0;

Needed ?

Will remove.

Quoted 11 lines

Quoted 11 lines

arch/arm/mach-socfpga/misc_s10.c new file +10 -0

+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+     if (argc != 2)
+             return CMD_RET_USAGE;
+
+     argv++;
+
+     switch (*argv[0]) {

Quoted 8 lines

arch/arm/mach-socfpga/misc_s10.c line 90

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+     case 'e':       /* Enable */
+             socfpga_bridges_reset(1);
+             break;
+     case 'd':       /* Disable */
+             socfpga_bridges_reset(0);
+             break;

Do you really need to duplicate this command ?

Will rework this part and merge with Gen5.

Quoted 15 lines

Quoted 5 lines

arch/arm/mach-socfpga/misc_s10.c new file +3 -0

+     default:
+             return CMD_RET_USAGE;
+     }

arch/arm/mach-socfpga/misc_s10.c line 103

Quoted 10 lines

arch/arm/mach-socfpga/misc_s10.c new file +10 -0

+
+     return 0;
+}
+
+U_BOOT_CMD(bridge, 2, 1, do_bridge,
+        "SoCFPGA HPS FPGA bridge control",
+        "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+        "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+        ""
+);

Thanks.

Regards
Ley Foon

Quoted 63 lines · Ley Foon Tan

Quoted 62 lines · Marek Vasut

Quoted 49 lines · Ley Foon Tan

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/Makefile   |    1 +
 arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index 910eb6f..b253914 100644
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y        += clock_manager_s10.o
+obj-y        += misc_s10.o
 obj-y        += reset_manager_s10.o
 obj-y        += system_manager_s10.o
 obj-y        += wrap_pinmux_config_s10.o

arch/arm/mach-socfpga/misc_s10.c new file +21 -0

new file mode 100644
index 0000000..b1cc6ca
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+#include <linux/libfdt.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>

arch/arm/mach-socfpga/misc_s10.c line 31

Quoted 10 lines

arch/arm/mach-socfpga/misc_s10.c new file +10 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE

Use the reset framework ? Talk to Dinh if in doubt

Quoted 2 lines

Yes, will convert this to reset framework. Will send out separate patches to convert device drivers to use reset framework.

Thanks, this really helps even for the A10.

http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10

Quoted 67 lines · Marek Vasut

Quoted 65 lines · Ley Foon Tan

Quoted 54 lines · Marek Vasut

Quoted 53 lines · Ley Foon Tan

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/Makefile   |    1 +
 arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index 910eb6f..b253914 100644
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y        += clock_manager_s10.o
+obj-y        += misc_s10.o
 obj-y        += reset_manager_s10.o
 obj-y        += system_manager_s10.o
 obj-y        += wrap_pinmux_config_s10.o

arch/arm/mach-socfpga/misc_s10.c new file +25 -0

new file mode 100644
index 0000000..b1cc6ca
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+#include <linux/libfdt.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =

Quoted 8 lines

arch/arm/mach-socfpga/misc_s10.c line 31

Quoted 6 lines

arch/arm/mach-socfpga/misc_s10.c new file +6 -0

+     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE

Use the reset framework ? Talk to Dinh if in doubt

Yes, will convert this to reset framework. Will send out separate patches to convert device drivers to use reset framework.

Quoted 3 lines

Thanks, this really helps even for the A10.

http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10

I saw you have new patches on this git repo, should I rebase my patchset on top of this git repo or using main u-boot.git?

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                   |    1 +
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |  155 +++++++++
 arch/arm/mach-socfpga/mailbox_s10.c              |  378 ++++++++++++++++++++++
 3 files changed, 534 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index b253914..43e18d2 100644
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o

arch/arm/mach-socfpga/include/mach/mailbox_s10.h new file +81 -0

new file mode 100644
index 0000000..85e7f84
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _MAILBOX_S10_H_
+#define _MAILBOX_S10_H_
+
+/* user define Uboot ID */
+#define MBOX_CLIENT_ID_UBOOT	0xB
+#define MBOX_ID_UBOOT		0x1
+
+#define MBOX_CMD_DIRECT	0
+#define MBOX_CMD_INDIRECT	1
+
+#define MBOX_MAX_CMD_INDEX	2047
+#define MBOX_CMD_BUFFER_SIZE	32
+#define MBOX_RESP_BUFFER_SIZE	16
+
+#define MBOX_HDR_CMD_LSB	0
+#define MBOX_HDR_CMD_MSK	(BIT(11) - 1)
+#define MBOX_HDR_I_LSB		11
+#define MBOX_HDR_I_MSK		BIT(11)
+#define MBOX_HDR_LEN_LSB	12
+#define MBOX_HDR_LEN_MSK	0x007FF000
+#define MBOX_HDR_ID_LSB		24
+#define MBOX_HDR_ID_MSK		0x0F000000
+#define MBOX_HDR_CLIENT_LSB	28
+#define MBOX_HDR_CLIENT_MSK	0xF0000000
+
+/* Interrupt flags */
+#define MBOX_FLAGS_INT_COE	BIT(0)	/* COUT update interrupt enable */
+#define MBOX_FLAGS_INT_RIE	BIT(1)	/* RIN update interrupt enable */
+#define MBOX_FLAGS_INT_UAE	BIT(8)	/* Urgent ACK interrupt enable */
+#define MBOX_ALL_INTRS		(MBOX_FLAGS_INT_COE | \
+				 MBOX_FLAGS_INT_RIE | \
+				 MBOX_FLAGS_INT_UAE)
+
+/* Status */
+#define MBOX_STATUS_UA_MSK	BIT(8)
+
+#define MBOX_CMD_HEADER(client, id, len, indirect, cmd)     \
+	((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
+	(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
+	(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK)  | \
+	(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)     | \
+	(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
+
+#define MBOX_RESP_ERR_GET(resp)				\
+	(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
+#define MBOX_RESP_LEN_GET(resp)			\
+	(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
+#define MBOX_RESP_ID_GET(resp)				\
+	(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
+#define MBOX_RESP_CLIENT_GET(resp)			\
+	(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
+
+/* Response error list */
+enum ALT_SDM_MBOX_RESP_CODE {
+	/* CMD completed successfully, but check resp ARGS for any errors */
+	MBOX_RESP_STATOK = 0,
+	/* CMD is incorrectly formatted in some way */
+	MBOX_RESP_INVALID_COMMAND = 1,
+	/* BootROM Command code not undesrtood */
+	MBOX_RESP_UNKNOWN_BR = 2,
+	/* CMD code not recognized by firmware */
+	MBOX_RESP_UNKNOWN = 3,
+	/* Indicates that the device is not configured */
+	MBOX_RESP_NOT_CONFIGURED = 256,
+	/* Indicates that the device is busy */
+	MBOX_RESP_DEVICE_BUSY = 0x1FF,
+	/* Indicates that there is no valid response available */
+	MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
+	/* General Error */
+	MBOX_RESP_ERROR = 0x3FF,
+};
+
+/* Mailbox command list */
+#define MBOX_RESTART		2
+#define MBOX_CONFIG_STATUS	4

arch/arm/mach-socfpga/include/mach/mailbox_s10.h new file +64 -0

+	u32 cin;		/* command valid offset */
+	u32 rout;		/* response output offset */
+	u32 urg;		/* urgent command */
+	u32 flags;		/* interrupt enables */
+	u32 pad_0x10_0x1f[4];	/* 0x10 - 0x1F reserved */
+	u32 cout;		/* command free offset */
+	u32 rin;		/* respond valid offset */
+	u32 pad_0x28;		/* 0x28 reserved */
+	u32 status;		/* mailbox status */
+	u32 pad_0x30_0x3f[4];	/* 0x30 - 0x3F reserved */
+	u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];	/* 0x40 - 0xBC circular command
+						 * buffer to SDM
+						 */
+	u32 resp_buf[MBOX_RESP_BUFFER_SIZE];	/* 0xC0 - 0xFF circular
+						 * response buffer
+						 */
+};
+
+/* Use define other than put into struct socfpga_mailbox to save spaces */
+#define MBOX_DOORBELL_TO_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x400)
+#define MBOX_DOORBELL_FROM_SDM_REG	(SOCFPGA_MAILBOX_ADDRESS + 0x480)
+
+/******** Status and bit information returned by RECONFIG_STATUS ********/
+#define RECONFIG_STATUS_RESPONSE_LEN			6
+#define RECONFIG_STATUS_STATE				0
+#define RECONFIG_STATUS_PIN_STATUS			2
+#define RECONFIG_STATUS_SOFTFUNC_STATUS			3
+
+#define MBOX_CFGSTAT_STATE_IDLE				0x00000000
+#define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
+#define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
+#define MBOX_CFGSTAT_STATE_ERROR_INVALID		0xf0000001
+#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT		0xf0000002
+#define MBOX_CFGSTAT_STATE_ERROR_AUTH			0xf0000003
+#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO		0xf0000004
+#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE		0xf0000005
+#define MBOX_CFGSTAT_STATE_ERROR_FAKE			0xf0000006
+#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO		0xf0000007
+#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR		0xf0000008
+
+#define RCF_SOFTFUNC_STATUS_CONF_DONE			BIT(0)
+#define RCF_SOFTFUNC_STATUS_INIT_DONE			BIT(1)
+#define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
+#define RCF_PIN_STATUS_NSTATUS				BIT(31)
+/************************************************************************/
+
+int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
+		  u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
+		       u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_init(void);
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void);
+int mbox_qspi_open(void);
+#endif
+
+int mbox_reset_cold(void);
+
+#endif /* _MAILBOX_S10_H_ */

arch/arm/mach-socfpga/mailbox_s10.c new file +16 -0

new file mode 100644
index 0000000..ed713a9
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/system_manager.h>
+#include <asm/secure.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __always_inline int mbox_polling_resp(u32 rout)

arch/arm/mach-socfpga/mailbox_s10.c new file +74 -0

+		i--;
+	}
+
+	return -ETIMEDOUT;
+}
+
+/* Check for available slot and write to circular buffer.
+ * It also update command valid offset (cin) register.
+ */
+static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
+						       u32 *arg)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+	u32 cin;
+	u32 cout;
+	u32 i;
+
+	cin = readl(&mbox_base->cin) % MBOX_CMD_BUFFER_SIZE;
+	cout = readl(&mbox_base->cout) % MBOX_CMD_BUFFER_SIZE;
+
+	/* if command buffer is full or not enough free space
+	 * to fit the data
+	 */
+	if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
+	    ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
+	     MBOX_CMD_BUFFER_SIZE) < len)
+		return -ENOMEM;
+
+	/* write header to circular buffer */
+	writel(header, &mbox_base->cmd_buf[cin++]);
+	/* wrapping around when it reach the buffer size */
+	cin %= MBOX_CMD_BUFFER_SIZE;
+
+	/* write arguments */
+	for (i = 0; i < len; i++) {
+		writel(arg[i], &mbox_base->cmd_buf[cin++]);
+		/* wrapping around when it reach the buffer size */
+		cin %= MBOX_CMD_BUFFER_SIZE;
+	}
+
+	/* write command valid offset */
+	writel(cin, &mbox_base->cin);
+
+	return 0;
+}
+
+/* Check the command and fill it into circular buffer */
+static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
+						 u8 is_indirect, u32 len,
+						 u32 *arg)
+{
+	u32 header;
+	int ret;
+
+	/* Total length is command + argument length */
+	if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
+		return -EINVAL;
+
+	if (cmd > MBOX_MAX_CMD_INDEX)
+		return -EINVAL;
+
+	header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
+				 (is_indirect) ? 1 : 0, cmd);
+
+	ret = mbox_fill_cmd_circular_buff(header, len, arg);
+
+	return ret;
+}
+
+/* Send command only without waiting for responses from SDM */
+static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
+						u8 is_indirect, u32 len,
+						u32 *arg)

arch/arm/mach-socfpga/mailbox_s10.c new file +59 -0

+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+	u32 rin;
+	u32 rout;
+	u32 resp_len = 0;
+
+	/* clear doorbell from SDM if it was SET */
+	if (readl((const u32 *)MBOX_DOORBELL_FROM_SDM_REG) & 1)
+		writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+	/* read current response offset */
+	rout = readl(&mbox_base->rout);
+	/* read response valid offset */
+	rin = readl(&mbox_base->rin);
+
+	while (rin != rout && (resp_len < resp_buf_max_len)) {
+		/* Response received */
+		if (resp_buf)
+			resp_buf[resp_len++] =
+				readl(&mbox_base->resp_buf[rout]);
+		rout++;
+		/* wrapping around when it reach the buffer size */
+		rout %= MBOX_RESP_BUFFER_SIZE;
+		/* update next ROUT */
+		writel(rout, &mbox_base->rout);
+	}
+
+	return resp_len;
+}
+
+/* Support one command and up to 31 words argument length only */
+static __always_inline int __mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect,
+					   u32 len, u32 *arg, u8 urgent,
+					   u32 *resp_buf_len, u32 *resp_buf)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+
+	u32 rin;
+	u32 resp;
+	u32 rout;
+	u32 status;
+	u32 resp_len;
+	u32 buf_len;
+	int ret;
+
+	ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+	if (ret)
+		return ret;
+
+	if (urgent) {
+		/* Read status because it is toggled */
+		status = readl(&mbox_base->status) & MBOX_STATUS_UA_MSK;
+		/* Send command as urgent command */
+		writel(1, &mbox_base->urg);
+	}
+
+	/* write doorbell */

arch/arm/mach-socfpga/mailbox_s10.c new file +127 -0

+		/* clear interrupt */
+		writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+		if (urgent) {
+			u32 new_status = readl(&mbox_base->status);
+			/* urgent command doesn't have response */
+			writel(0, &mbox_base->urg);
+			/* Urgent ACK is toggled */
+			if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
+				return 0;
+
+			return -ECOMM;
+		}
+
+		/* read current response offset */
+		rout = readl(&mbox_base->rout);
+
+		/* read response valid offset */
+		rin = readl(&mbox_base->rin);
+
+		if (rout != rin) {
+			/* Response received */
+			resp = readl(&mbox_base->resp_buf[rout]);
+			rout++;
+			/* wrapping around when it reach the buffer size */
+			rout %= MBOX_RESP_BUFFER_SIZE;
+			/* update next ROUT */
+			writel(rout, &mbox_base->rout);
+
+			/* check client ID and ID */
+			if ((MBOX_RESP_CLIENT_GET(resp) == MBOX_CLIENT_ID_UBOOT) &&
+			    (MBOX_RESP_ID_GET(resp) == id)) {
+				ret = MBOX_RESP_ERR_GET(resp);
+				if (ret)
+					return ret;
+
+				if (resp_buf_len) {
+					buf_len = *resp_buf_len;
+					*resp_buf_len = 0;
+				} else {
+					buf_len = 0;
+				}
+
+				resp_len = MBOX_RESP_LEN_GET(resp);
+				while (resp_len) {
+					ret = mbox_polling_resp(rout);
+					if (ret)
+						return ret;
+					/* we need to process response buffer
+					 * even caller doesn't need it
+					 */
+					resp = readl(&mbox_base->resp_buf[rout]);
+					rout++;
+					resp_len--;
+					rout %= MBOX_RESP_BUFFER_SIZE;
+					writel(rout, &mbox_base->rout);
+					if (buf_len) {
+						/* copy response to buffer */
+						resp_buf[*resp_buf_len] = resp;
+						(*resp_buf_len)++;
+						buf_len--;
+					}
+				}
+				return ret;
+			}
+		}
+	};
+
+	return -EIO;
+}
+
+int mbox_init(void)
+{
+	static const struct socfpga_mailbox *mbox_base =
+					(void *)SOCFPGA_MAILBOX_ADDRESS;
+	int ret;
+
+	/* enable mailbox interrupts */
+	writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+	/* Ensure urgent request is cleared */
+	writel(0, &mbox_base->urg);
+
+	/* Ensure the Doorbell Interrupt is cleared */
+	writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
+			    NULL, 1, 0, NULL);
+	if (ret)
+		return ret;
+
+	/* Renable mailbox interrupts after MBOX_RESTART */
+	writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+	return 0;
+}
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void)
+{
+	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
+			     0, NULL, 0, 0, NULL);
+}
+
+int mbox_qspi_open(void)
+{
+	static const struct socfpga_system_manager *sysmgr_regs =
+		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+	int ret;
+	u32 resp_buf[1];
+	u32 resp_buf_len;
+
+	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
+			    0, NULL, 0, 0, NULL);
+	if (ret) {
+		/* retry again by closing and reopen the QSPI again */
+		ret = mbox_qspi_close();
+		if (ret)
+			return ret;
+
+		ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
+				    MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
+		if (ret)
+			return ret;
+	}
+

arch/arm/mach-socfpga/mailbox_s10.c new file +11 -0

+	writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
+
+	return 0;
+
+error:
+	mbox_qspi_close();
+
+	return ret;
+}
+#endif /* CONFIG_CADENCE_QSPI */
+

Quoted 116 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                   |    1 +
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h |  155 +++++++++
 arch/arm/mach-socfpga/mailbox_s10.c              |  378 ++++++++++++++++++++++
 3 files changed, 534 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h
 create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index b253914..43e18d2 100644
@@ -32,6 +32,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y        += clock_manager_s10.o
+obj-y        += mailbox_s10.o
 obj-y        += misc_s10.o
 obj-y        += reset_manager_s10.o
 obj-y        += system_manager_s10.o

arch/arm/mach-socfpga/include/mach/mailbox_s10.h new file +86 -0

new file mode 100644
index 0000000..85e7f84
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _MAILBOX_S10_H_
+#define _MAILBOX_S10_H_
+
+/* user define Uboot ID */
+#define MBOX_CLIENT_ID_UBOOT 0xB
+#define MBOX_ID_UBOOT                0x1
+
+#define MBOX_CMD_DIRECT      0
+#define MBOX_CMD_INDIRECT    1
+
+#define MBOX_MAX_CMD_INDEX   2047
+#define MBOX_CMD_BUFFER_SIZE 32
+#define MBOX_RESP_BUFFER_SIZE        16
+
+#define MBOX_HDR_CMD_LSB     0
+#define MBOX_HDR_CMD_MSK     (BIT(11) - 1)
+#define MBOX_HDR_I_LSB               11
+#define MBOX_HDR_I_MSK               BIT(11)
+#define MBOX_HDR_LEN_LSB     12
+#define MBOX_HDR_LEN_MSK     0x007FF000
+#define MBOX_HDR_ID_LSB              24
+#define MBOX_HDR_ID_MSK              0x0F000000
+#define MBOX_HDR_CLIENT_LSB  28
+#define MBOX_HDR_CLIENT_MSK  0xF0000000
+
+/* Interrupt flags */
+#define MBOX_FLAGS_INT_COE   BIT(0)  /* COUT update interrupt enable */
+#define MBOX_FLAGS_INT_RIE   BIT(1)  /* RIN update interrupt enable */
+#define MBOX_FLAGS_INT_UAE   BIT(8)  /* Urgent ACK interrupt enable */
+#define MBOX_ALL_INTRS               (MBOX_FLAGS_INT_COE | \
+                              MBOX_FLAGS_INT_RIE | \
+                              MBOX_FLAGS_INT_UAE)
+
+/* Status */
+#define MBOX_STATUS_UA_MSK   BIT(8)
+
+#define MBOX_CMD_HEADER(client, id, len, indirect, cmd)     \
+     ((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
+     (((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
+     (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK)  | \
+     (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK)     | \
+     (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
+
+#define MBOX_RESP_ERR_GET(resp)                              \
+     (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
+#define MBOX_RESP_LEN_GET(resp)                      \
+     (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
+#define MBOX_RESP_ID_GET(resp)                               \
+     (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
+#define MBOX_RESP_CLIENT_GET(resp)                   \
+     (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
+
+/* Response error list */
+enum ALT_SDM_MBOX_RESP_CODE {
+     /* CMD completed successfully, but check resp ARGS for any errors */
+     MBOX_RESP_STATOK = 0,
+     /* CMD is incorrectly formatted in some way */
+     MBOX_RESP_INVALID_COMMAND = 1,
+     /* BootROM Command code not undesrtood */
+     MBOX_RESP_UNKNOWN_BR = 2,
+     /* CMD code not recognized by firmware */
+     MBOX_RESP_UNKNOWN = 3,
+     /* Indicates that the device is not configured */
+     MBOX_RESP_NOT_CONFIGURED = 256,
+     /* Indicates that the device is busy */
+     MBOX_RESP_DEVICE_BUSY = 0x1FF,
+     /* Indicates that there is no valid response available */
+     MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
+     /* General Error */
+     MBOX_RESP_ERROR = 0x3FF,
+};
+
+/* Mailbox command list */
+#define MBOX_RESTART         2
+#define MBOX_CONFIG_STATUS   4
+#define MBOX_RECONFIG                6
+#define MBOX_RECONFIG_MSEL   7
+#define MBOX_RECONFIG_DATA   8
+#define MBOX_RECONFIG_STATUS 9
+#define MBOX_QSPI_OPEN               50

arch/arm/mach-socfpga/include/mach/mailbox_s10.h line 91

Quoted 5 lines

arch/arm/mach-socfpga/include/mach/mailbox_s10.h new file +5 -0

+#define MBOX_QSPI_CLOSE              51
+#define MBOX_QSPI_DIRECT     59
+#define MBOX_REBOOT_HPS              71
+
+struct socfpga_mailbox {

We should probably just use register offset macros in new code, this struct {} stuff often doesn't work too well and the limitations are showing.

Quoted 91 lines

arch/arm/mach-socfpga/include/mach/mailbox_s10.h new file +64 -0

+     u32 cin;                /* command valid offset */
+     u32 rout;               /* response output offset */
+     u32 urg;                /* urgent command */
+     u32 flags;              /* interrupt enables */
+     u32 pad_0x10_0x1f[4];   /* 0x10 - 0x1F reserved */
+     u32 cout;               /* command free offset */
+     u32 rin;                /* respond valid offset */
+     u32 pad_0x28;           /* 0x28 reserved */
+     u32 status;             /* mailbox status */
+     u32 pad_0x30_0x3f[4];   /* 0x30 - 0x3F reserved */
+     u32 cmd_buf[MBOX_CMD_BUFFER_SIZE];      /* 0x40 - 0xBC circular command
+                                              * buffer to SDM
+                                              */
+     u32 resp_buf[MBOX_RESP_BUFFER_SIZE];    /* 0xC0 - 0xFF circular
+                                              * response buffer
+                                              */
+};
+
+/* Use define other than put into struct socfpga_mailbox to save spaces */
+#define MBOX_DOORBELL_TO_SDM_REG     (SOCFPGA_MAILBOX_ADDRESS + 0x400)
+#define MBOX_DOORBELL_FROM_SDM_REG   (SOCFPGA_MAILBOX_ADDRESS + 0x480)
+
+/******** Status and bit information returned by RECONFIG_STATUS ********/
+#define RECONFIG_STATUS_RESPONSE_LEN                 6
+#define RECONFIG_STATUS_STATE                                0
+#define RECONFIG_STATUS_PIN_STATUS                   2
+#define RECONFIG_STATUS_SOFTFUNC_STATUS                      3
+
+#define MBOX_CFGSTAT_STATE_IDLE                              0x00000000
+#define MBOX_CFGSTAT_STATE_CONFIG                    0x10000000
+#define MBOX_CFGSTAT_STATE_FAILACK                   0x08000000
+#define MBOX_CFGSTAT_STATE_ERROR_INVALID             0xf0000001
+#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT             0xf0000002
+#define MBOX_CFGSTAT_STATE_ERROR_AUTH                        0xf0000003
+#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO             0xf0000004
+#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE            0xf0000005
+#define MBOX_CFGSTAT_STATE_ERROR_FAKE                        0xf0000006
+#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO           0xf0000007
+#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR          0xf0000008
+
+#define RCF_SOFTFUNC_STATUS_CONF_DONE                        BIT(0)
+#define RCF_SOFTFUNC_STATUS_INIT_DONE                        BIT(1)
+#define RCF_SOFTFUNC_STATUS_SEU_ERROR                        BIT(3)
+#define RCF_PIN_STATUS_NSTATUS                               BIT(31)
+/************************************************************************/
+
+int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
+               u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
+                    u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
+int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
+int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
+int mbox_init(void);
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void);
+int mbox_qspi_open(void);
+#endif
+
+int mbox_reset_cold(void);
+
+#endif /* _MAILBOX_S10_H_ */

arch/arm/mach-socfpga/mailbox_s10.c new file +20 -0

new file mode 100644
index 0000000..ed713a9
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/system_manager.h>
+#include <asm/secure.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;

arch/arm/mach-socfpga/mailbox_s10.c line 26

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

Quoted 79 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +78 -0

+             i--;
+     }
+
+     return -ETIMEDOUT;
+}
+
+/* Check for available slot and write to circular buffer.
+ * It also update command valid offset (cin) register.
+ */
+static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
+                                                    u32 *arg)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 cin;
+     u32 cout;
+     u32 i;
+
+     cin = readl(&mbox_base->cin) % MBOX_CMD_BUFFER_SIZE;
+     cout = readl(&mbox_base->cout) % MBOX_CMD_BUFFER_SIZE;
+
+     /* if command buffer is full or not enough free space
+      * to fit the data
+      */
+     if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
+         ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
+          MBOX_CMD_BUFFER_SIZE) < len)
+             return -ENOMEM;
+
+     /* write header to circular buffer */
+     writel(header, &mbox_base->cmd_buf[cin++]);
+     /* wrapping around when it reach the buffer size */
+     cin %= MBOX_CMD_BUFFER_SIZE;
+
+     /* write arguments */
+     for (i = 0; i < len; i++) {
+             writel(arg[i], &mbox_base->cmd_buf[cin++]);
+             /* wrapping around when it reach the buffer size */
+             cin %= MBOX_CMD_BUFFER_SIZE;
+     }
+
+     /* write command valid offset */
+     writel(cin, &mbox_base->cin);
+
+     return 0;
+}
+
+/* Check the command and fill it into circular buffer */
+static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
+                                              u8 is_indirect, u32 len,
+                                              u32 *arg)
+{
+     u32 header;
+     int ret;
+
+     /* Total length is command + argument length */
+     if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
+             return -EINVAL;
+
+     if (cmd > MBOX_MAX_CMD_INDEX)
+             return -EINVAL;
+
+     header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
+                              (is_indirect) ? 1 : 0, cmd);
+
+     ret = mbox_fill_cmd_circular_buff(header, len, arg);
+
+     return ret;
+}
+
+/* Send command only without waiting for responses from SDM */
+static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
+                                             u8 is_indirect, u32 len,
+                                             u32 *arg)
+{
+     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+     /* write doorbell */
+     writel(1, MBOX_DOORBELL_TO_SDM_REG);

arch/arm/mach-socfpga/mailbox_s10.c line 111

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+
+     return ret;
+}
+
+/* Return number of responses received in buffer */
+static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)

__always_inline is nonsense, drop it. Let the compiler do it's thing.

Quoted 64 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +63 -0

+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;
+     u32 rout;
+     u32 resp_len = 0;
+
+     /* clear doorbell from SDM if it was SET */
+     if (readl((const u32 *)MBOX_DOORBELL_FROM_SDM_REG) & 1)
+             writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+     /* read current response offset */
+     rout = readl(&mbox_base->rout);
+     /* read response valid offset */
+     rin = readl(&mbox_base->rin);
+
+     while (rin != rout && (resp_len < resp_buf_max_len)) {
+             /* Response received */
+             if (resp_buf)
+                     resp_buf[resp_len++] =
+                             readl(&mbox_base->resp_buf[rout]);
+             rout++;
+             /* wrapping around when it reach the buffer size */
+             rout %= MBOX_RESP_BUFFER_SIZE;
+             /* update next ROUT */
+             writel(rout, &mbox_base->rout);
+     }
+
+     return resp_len;
+}
+
+/* Support one command and up to 31 words argument length only */
+static __always_inline int __mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect,
+                                        u32 len, u32 *arg, u8 urgent,
+                                        u32 *resp_buf_len, u32 *resp_buf)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+
+     u32 rin;
+     u32 resp;
+     u32 rout;
+     u32 status;
+     u32 resp_len;
+     u32 buf_len;
+     int ret;
+
+     ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+     if (ret)
+             return ret;
+
+     if (urgent) {
+             /* Read status because it is toggled */
+             status = readl(&mbox_base->status) & MBOX_STATUS_UA_MSK;
+             /* Send command as urgent command */
+             writel(1, &mbox_base->urg);
+     }
+
+     /* write doorbell */
+     writel(1, MBOX_DOORBELL_TO_SDM_REG);
+
+     while (1) {
+             ret = ~0;

arch/arm/mach-socfpga/mailbox_s10.c line 180

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+
+             /* Wait for doorbell from SDM */
+             while (!readl(MBOX_DOORBELL_FROM_SDM_REG) && ret--)
+                     ;
+             if (!ret)
+                     return -ETIMEDOUT;

wait_for_bit...

Quoted 132 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +131 -0

+             /* clear interrupt */
+             writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+             if (urgent) {
+                     u32 new_status = readl(&mbox_base->status);
+                     /* urgent command doesn't have response */
+                     writel(0, &mbox_base->urg);
+                     /* Urgent ACK is toggled */
+                     if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
+                             return 0;
+
+                     return -ECOMM;
+             }
+
+             /* read current response offset */
+             rout = readl(&mbox_base->rout);
+
+             /* read response valid offset */
+             rin = readl(&mbox_base->rin);
+
+             if (rout != rin) {
+                     /* Response received */
+                     resp = readl(&mbox_base->resp_buf[rout]);
+                     rout++;
+                     /* wrapping around when it reach the buffer size */
+                     rout %= MBOX_RESP_BUFFER_SIZE;
+                     /* update next ROUT */
+                     writel(rout, &mbox_base->rout);
+
+                     /* check client ID and ID */
+                     if ((MBOX_RESP_CLIENT_GET(resp) == MBOX_CLIENT_ID_UBOOT) &&
+                         (MBOX_RESP_ID_GET(resp) == id)) {
+                             ret = MBOX_RESP_ERR_GET(resp);
+                             if (ret)
+                                     return ret;
+
+                             if (resp_buf_len) {
+                                     buf_len = *resp_buf_len;
+                                     *resp_buf_len = 0;
+                             } else {
+                                     buf_len = 0;
+                             }
+
+                             resp_len = MBOX_RESP_LEN_GET(resp);
+                             while (resp_len) {
+                                     ret = mbox_polling_resp(rout);
+                                     if (ret)
+                                             return ret;
+                                     /* we need to process response buffer
+                                      * even caller doesn't need it
+                                      */
+                                     resp = readl(&mbox_base->resp_buf[rout]);
+                                     rout++;
+                                     resp_len--;
+                                     rout %= MBOX_RESP_BUFFER_SIZE;
+                                     writel(rout, &mbox_base->rout);
+                                     if (buf_len) {
+                                             /* copy response to buffer */
+                                             resp_buf[*resp_buf_len] = resp;
+                                             (*resp_buf_len)++;
+                                             buf_len--;
+                                     }
+                             }
+                             return ret;
+                     }
+             }
+     };
+
+     return -EIO;
+}
+
+int mbox_init(void)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     int ret;
+
+     /* enable mailbox interrupts */
+     writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+     /* Ensure urgent request is cleared */
+     writel(0, &mbox_base->urg);
+
+     /* Ensure the Doorbell Interrupt is cleared */
+     writel(0, MBOX_DOORBELL_FROM_SDM_REG);
+
+     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
+                         NULL, 1, 0, NULL);
+     if (ret)
+             return ret;
+
+     /* Renable mailbox interrupts after MBOX_RESTART */
+     writel(MBOX_ALL_INTRS, &mbox_base->flags);
+
+     return 0;
+}
+
+#ifdef CONFIG_CADENCE_QSPI
+int mbox_qspi_close(void)
+{
+     return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
+                          0, NULL, 0, 0, NULL);
+}
+
+int mbox_qspi_open(void)
+{
+     static const struct socfpga_system_manager *sysmgr_regs =
+             (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+     int ret;
+     u32 resp_buf[1];
+     u32 resp_buf_len;
+
+     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
+                         0, NULL, 0, 0, NULL);
+     if (ret) {
+             /* retry again by closing and reopen the QSPI again */
+             ret = mbox_qspi_close();
+             if (ret)
+                     return ret;
+
+             ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
+                                 MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
+             if (ret)
+                     return ret;
+     }
+
+     /* HPS will directly control the QSPI controller, no longer mailbox */
+     resp_buf_len = 1;
+     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
+                         0, NULL, 0, (u32 *)&resp_buf_len,

arch/arm/mach-socfpga/mailbox_s10.c line 318

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+                         (u32 *)&resp_buf);
+     if (ret)
+             goto error;
+
+     /* We are getting QSPI ref clock and set into sysmgr boot register */
+     printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);

Certainly something I can get out of clock or clk command, drop the print.

Quoted 16 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +15 -0

+     writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
+
+     return 0;
+
+error:
+     mbox_qspi_close();
+
+     return ret;
+}
+#endif /* CONFIG_CADENCE_QSPI */
+
+int mbox_reset_cold(void)
+{
+     int ret;
+

arch/arm/mach-socfpga/mailbox_s10.c line 339

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+     ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
+                         0, NULL, 0, 0, NULL);
+     if (ret) {
+             /* mailbox sent failure, wait for watchdog to kick in */
+             while (1)
+                     ;

Is this supposed to be hang() ?

arch/arm/mach-socfpga/mailbox_s10.c line 349

Quoted 11 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +10 -0

+     }
+     return 0;
+}
+
+int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
+               u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
+{
+     return __mbox_send_cmd(id, cmd, is_indirect, len, arg, urgent,
+                            resp_buf_len, resp_buf);
+}

__anything is reserved for compiler, drop the leading underscores

Quoted 1 line

--
Best regards,
Marek Vasut

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +5 -0

+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;

Quoted 8 lines

arch/arm/mach-socfpga/mailbox_s10.c line 26

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

The reason we use this method instead of using wait_bit because this function will use in Secure Monitor Call (SMC) call as well. When run in secure section, timer is not available. So, we can't use wait_for_bit.

Quoted 8 lines

Quoted 8 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +8 -0

+/* Send command only without waiting for responses from SDM */
+static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
+                                             u8 is_indirect, u32 len,
+                                             u32 *arg)
+{
+     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+     /* write doorbell */
+     writel(1, MBOX_DOORBELL_TO_SDM_REG);

Quoted 8 lines

arch/arm/mach-socfpga/mailbox_s10.c line 111

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+
+     return ret;
+}
+
+/* Return number of responses received in buffer */
+static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)

__always_inline is nonsense, drop it. Let the compiler do it's thing.

This function used in SMC call as well, so it needs to be inline when in secure section.

Quoted 7 lines · Ley Foon Tan

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---

[...]

Quoted 13 lines

Quoted 13 lines

arch/arm/mach-socfpga/mailbox_s10.c line 26

Quoted 11 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +11 -0

+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;
+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

Quoted 4 lines

The reason we use this method instead of using wait_bit because this function will use in Secure Monitor Call (SMC) call as well. When run in secure section, timer is not available. So, we can't use wait_for_bit.

Can't you just do timer_init() then ?

Quoted 17 lines

Quoted 17 lines

Quoted 5 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +4 -0

+/* Send command only without waiting for responses from SDM */
+static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
+                                             u8 is_indirect, u32 len,
+                                             u32 *arg)

arch/arm/mach-socfpga/mailbox_s10.c line 111

Quoted 10 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +10 -0

+{
+     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+     /* write doorbell */
+     writel(1, MBOX_DOORBELL_TO_SDM_REG);
+
+     return ret;
+}
+
+/* Return number of responses received in buffer */
+static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)

__always_inline is nonsense, drop it. Let the compiler do it's thing.

Quoted 2 lines

This function used in SMC call as well, so it needs to be inline when in secure section.

Why ?

Quoted 29 lines · Marek Vasut

Quoted 7 lines · Ley Foon Tan

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---

[...]

Quoted 17 lines

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +5 -0

+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;

Quoted 8 lines

arch/arm/mach-socfpga/mailbox_s10.c line 26

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

The reason we use this method instead of using wait_bit because this function will use in Secure Monitor Call (SMC) call as well. When run in secure section, timer is not available. So, we can't use wait_for_bit.

Quoted 1 line

Can't you just do timer_init() then ?

We can't use timer in secure region. This SMC code is resident in onchip memory (secure region) while Linux is running. So, timer might be used by Linux.

Quoted 16 lines

Quoted 16 lines

Quoted 16 lines

Quoted 4 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +4 -0

+/* Send command only without waiting for responses from SDM */
+static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
+                                             u8 is_indirect, u32 len,
+                                             u32 *arg)

arch/arm/mach-socfpga/mailbox_s10.c line 111

Quoted 10 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +10 -0

+{
+     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+     /* write doorbell */
+     writel(1, MBOX_DOORBELL_TO_SDM_REG);
+
+     return ret;
+}
+
+/* Return number of responses received in buffer */
+static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)

__always_inline is nonsense, drop it. Let the compiler do it's thing.

Quoted 4 lines

Quoted 2 lines

This function used in SMC call as well, so it needs to be inline when in secure section.

Why ?

These functions needed for normal U-boot and SMC (secure section in OCM) and we need to copy the whole function to secure section, not just the API call.
This also avoid code duplication for U-boot and SMC.

Quoted 30 lines · Ley Foon Tan

Quoted 29 lines · Marek Vasut

Quoted 7 lines · Ley Foon Tan

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---

[...]

Quoted 17 lines

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +5 -0

+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;

Quoted 8 lines

arch/arm/mach-socfpga/mailbox_s10.c line 26

Quoted 6 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +6 -0

+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

The reason we use this method instead of using wait_bit because this function will use in Secure Monitor Call (SMC) call as well. When run in secure section, timer is not available. So, we can't use wait_for_bit.

Quoted 4 lines

Quoted 1 line

Can't you just do timer_init() then ?

We can't use timer in secure region. This SMC code is resident in onchip memory (secure region) while Linux is running. So, timer might be used by Linux.

So pieces of U-Boot remain in memory and get called by Linux, right ?

I am CCing a few more people , since this might need further discussion.

btw does this work when Linux is compiled in AArch32 mode while U-Boot is AArch64 ? I think it might not.

Quoted 21 lines

Quoted 21 lines

Quoted 17 lines

Quoted 17 lines

Quoted 5 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +4 -0

+/* Send command only without waiting for responses from SDM */
+static __always_inline int __mbox_send_cmd_only(u8 id, u32 cmd,
+                                             u8 is_indirect, u32 len,
+                                             u32 *arg)

arch/arm/mach-socfpga/mailbox_s10.c line 111

Quoted 10 lines

arch/arm/mach-socfpga/mailbox_s10.c new file +10 -0

+{
+     int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
+     /* write doorbell */
+     writel(1, MBOX_DOORBELL_TO_SDM_REG);
+
+     return ret;
+}
+
+/* Return number of responses received in buffer */
+static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)

__always_inline is nonsense, drop it. Let the compiler do it's thing.

Quoted 2 lines

This function used in SMC call as well, so it needs to be inline when in secure section.

Why ?

Quoted 4 lines

These functions needed for normal U-boot and SMC (secure section in OCM) and we need to copy the whole function to secure section, not just the API call.
This also avoid code duplication for U-boot and SMC.

Thanks for the explanation!

--

Quoted 36 lines · Marek Vasut

Quoted 34 lines · Ley Foon Tan

Quoted 24 lines · Marek Vasut

Quoted 7 lines · Ley Foon Tan

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---

[...]

Quoted 13 lines

Quoted 13 lines

Review

Quoted 11 lines

(quoted diff) +11 -0

+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;
+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

Quoted 6 lines

Quoted 4 lines

The reason we use this method instead of using wait_bit because this function will use in Secure Monitor Call (SMC) call as well. When run in secure section, timer is not available. So, we can't use wait_for_bit.

Can't you just do timer_init() then ?

We can't use timer in secure region. This SMC code is resident in onchip memory (secure region) while Linux is running. So, timer might be used by Linux.

Quoted 1 line

So pieces of U-Boot remain in memory and get called by Linux, right ?

Normal U-boot (in DDR) is destroyed after Linux is running, only SMC code Onchip memory will remain.
The existing U-boot have support this SMC feature, platform just need to configure the CONFIG_ARMV8_SECURE_BASE for the secure section. Of course, we need to enable CONFIG_ARMV8_PSCI too.

Quoted 4 lines

I am CCing a few more people , since this might need further discussion.

btw does this work when Linux is compiled in AArch32 mode while U-Boot is AArch64 ? I think it might not.

It should work. PSCI handle checks ESR_EL3.EC field to know whether it is SMC32 or SMC64.
See code in handle_sync near line 230 in
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/psci.S

Quoted 38 lines · Ley Foon Tan

Quoted 37 lines · Marek Vasut

Quoted 30 lines · Ley Foon Tan

Quoted 29 lines · Marek Vasut

Quoted 7 lines · Ley Foon Tan

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---

[...]

Quoted 17 lines

Quoted 5 lines

Quoted 5 lines

(quoted diff) +5 -0

+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;

Quoted 8 lines

Review

Quoted 6 lines

(quoted diff) +6 -0

+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

The reason we use this method instead of using wait_bit because this function will use in Secure Monitor Call (SMC) call as well. When run in secure section, timer is not available. So, we can't use wait_for_bit.

Quoted 4 lines

Quoted 1 line

Can't you just do timer_init() then ?

We can't use timer in secure region. This SMC code is resident in onchip memory (secure region) while Linux is running. So, timer might be used by Linux.

So pieces of U-Boot remain in memory and get called by Linux, right ?

Quoted 5 lines

Normal U-boot (in DDR) is destroyed after Linux is running, only SMC code Onchip memory will remain.
The existing U-boot have support this SMC feature, platform just need to configure the CONFIG_ARMV8_SECURE_BASE for the secure section. Of course, we need to enable CONFIG_ARMV8_PSCI too.

So piece of U-Boot then becomes the part which handles PSCI calls from Linux, do I understand it correctly ?

Quoted 5 lines

Quoted 5 lines

I am CCing a few more people , since this might need further discussion.

btw does this work when Linux is compiled in AArch32 mode while U-Boot is AArch64 ? I think it might not.

Quoted 4 lines

It should work. PSCI handle checks ESR_EL3.EC field to know whether it is SMC32 or SMC64.
See code in handle_sync near line 230 in
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/psci.S

Will do, thanks!

--

Quoted 45 lines · Marek Vasut

Quoted 43 lines · Ley Foon Tan

Quoted 31 lines · Marek Vasut

Quoted 30 lines · Ley Foon Tan

Quoted 29 lines · Marek Vasut

Quoted 7 lines · Ley Foon Tan

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Ley Foon Tan

Add mailbox support for Stratix SoC

Signed-off-by Ley Foon Tan <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

---

[...]

Quoted 17 lines

Quoted 5 lines

Quoted 5 lines

(quoted diff) +5 -0

+static __always_inline int mbox_polling_resp(u32 rout)
+{
+     static const struct socfpga_mailbox *mbox_base =
+                                     (void *)SOCFPGA_MAILBOX_ADDRESS;
+     u32 rin;

Quoted 8 lines

Review

Quoted 6 lines

(quoted diff) +6 -0

+     unsigned long i = ~0;
+
+     while (i) {
+             rin = readl(&mbox_base->rin);
+             if (rout != rin)
+                     return 0;

This looks like include/wait_bit.h reimplementation

The reason we use this method instead of using wait_bit because this function will use in Secure Monitor Call (SMC) call as well. When run in secure section, timer is not available. So, we can't use wait_for_bit.

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

Can't you just do timer_init() then ?

We can't use timer in secure region. This SMC code is resident in onchip memory (secure region) while Linux is running. So, timer might be used by Linux.

So pieces of U-Boot remain in memory and get called by Linux, right ?

Normal U-boot (in DDR) is destroyed after Linux is running, only SMC code Onchip memory will remain.
The existing U-boot have support this SMC feature, platform just need to configure the CONFIG_ARMV8_SECURE_BASE for the secure section. Of course, we need to enable CONFIG_ARMV8_PSCI too.

Quoted 2 lines

So piece of U-Boot then becomes the part which handles PSCI calls from Linux, do I understand it correctly ?

Yes, and we put this piece of code in onchip memory in our platform so it doesn't corrupted by Linux.

You can see detail in
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv8/u-boot.lds
All code related to PSCI/SMC will put in secure section.

Add MMU support for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/Makefile        |    1 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c |   71 +++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c

arch/arm/mach-socfpga/Makefile +1 -0

index 43e18d2..098e5e9 100644
@@ -34,6 +34,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
 obj-y	+= mailbox_s10.o
 obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o

arch/arm/mach-socfpga/mmu-arm64_s10.c new file +71 -0

new file mode 100644
index 0000000..670ceb9
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+	{
+		/* MEM 2GB*/
+		.virt	= 0x0UL,
+		.phys	= 0x0UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* FPGA 1.5GB */
+		.virt	= 0x80000000UL,
+		.phys	= 0x80000000UL,
+		.size	= 0x60000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* DEVICE 142MB */
+		.virt	= 0xF7000000UL,
+		.phys	= 0xF7000000UL,
+		.size	= 0x08E00000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* OCRAM 1MB but available 256KB */
+		.virt	= 0xFFE00000UL,
+		.phys	= 0xFFE00000UL,
+		.size	= 0x00100000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 32KB */
+		.virt	= 0xFFFC0000UL,
+		.phys	= 0xFFFC0000UL,
+		.size	= 0x00008000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* MEM 124GB */
+		.virt	= 0x0100000000UL,
+		.phys	= 0x0100000000UL,
+		.size	= 0x1F00000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* DEVICE 4GB */
+		.virt	= 0x2000000000UL,
+		.phys	= 0x2000000000UL,
+		.size	= 0x0100000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		/* List terminator */
+	},
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;