FAILED: patch "[PATCH] drm/i915: Correctly handle limited range YCbCr data on" failed to apply to 4.9-stable tree
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[email protected]
maintainerThe patch below does not apply to the 4.9-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
Quoted 1 line
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5deae9191130db6b617c94fb261804597cf9b508Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <[email protected]>
Date: Wed, 14 Feb 2018 21:23:23 +0200
Subject: [PATCH] drm/i915: Correctly handle limited range YCbCr data on
VLV/CHV
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Turns out the VLV/CHV fixed function sprite CSC expects full range data as input. We've been feeding it limited range data to it all along. To expand the data out to full range we'll use the color correction registers (brightness, contrast, and saturation).
On CHV pipe B we were actually doing the right thing already because we progammed the custom CSC matrix to do expect limited range input. Now that well pre-expand the data out with the color correction unit, we need to change the CSC matrix to operate with full range input instead.
This should make the sprite output of the other pipes match the sprite output of pipe B reasonably well. Looking at the resulting pipe CRCs, there can be a slight difference in the output, but as I don't know the formula used by the fixed function CSC of the other pipes, I don't think it's worth the effort to try to match the output exactly. It might not even be possible due to difference in internal precision etc.
One slight caveat here is that the color correction registers are single bufferred, so we should really be updating them during vblank, but we still don't have a mechanism for that, so just toss in another FIXME.
v2: Rebase
v3: s/bri/brightness/ s/con/contrast/ (Shashank)
v4: Clarify the constants and math (Shashank)
drivers/gpu/drm/i915/i915_reg.h +10 -0
@@ -6278,6 +6278,12 @@ enum {#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)#define SP_CONST_ALPHA_ENABLE (1<<31) +#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) +#define SP_CONTRAST (x) ((x) << 18)/* u3.6 */ +#define SP_BRIGHTNESS (x) ((x) & 0xff)/* s8 */ +#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) +#define SP_SH_SIN (x) (((x) & 0x7ff) << 16)/* s4.7 */ +#define SP_SH_COS (x) (x)/* u3.7 */ #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
@@ -6291,6 +6297,8 @@ enum {#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) +#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) +#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)#define _MMIO_VLV_SPR (pipe, plane_id, reg_a, reg_b) \
@@ -6307,6 +6315,8 @@ enum {#define SPKEYMAXVAL (pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)#define SPTILEOFF (pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)#define SPCONSTALPHA (pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) +#define SPCLRC0 (pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) +#define SPCLRC1 (pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)#define SPGAMC (pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)/*
drivers/gpu/drm/i915/intel_sprite.c +63 -18
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