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sunxi: R40: add gigabit ethernet clocks

PATCH Superseded Lothar Felten 2 participants 11 messages Apr 17, 2018 – Apr 23, 2018

Subsystems (3)
Network drivers Arm (32-bit) Arm/Allwinner sunXi SoC support

v2 of 6 Superseded Latest is v6 →

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Lothar Felten

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#0 lore raw

PATCH v2 1/5 sunxi: R40: add gigabit ethernet clocks

Add clock control entries for the gigabit interface of the Allwinner R40/V40 CPU

Signed-off-by Lothar Felten <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +9 -1
index d35aa479f7..3ea473c302 100644
@@ -61,7 +61,11 @@ struct sunxi_ccm_reg {
 	u32 reserved11;
 	u32 sata_clk_cfg;	/* 0xc8 SATA clock control (R40 only) */
 	u32 usb_clk_cfg;	/* 0xcc USB clock control */
-	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 cir0_clk_cfg;	/* 0xd0 CIR0 clock control (R40 only) */
+#else
+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control (not for R40) */
+#endif
 	u32 reserved12[7];
 	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
 	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */

@@ -104,7 +108,11 @@ struct sunxi_ccm_reg {
 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 gmac_clk_cfg;	/* 0x164 GMAC clock control (R40 only) */
+#else
 	u32 reserved16;
+#endif
 	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
 	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
 	u32 reserved17[4];
Signature · 1 line
2.14.1
author
#1 lore raw

PATCH v2 2/5 sunxi: R40: add gigabit ethernet reset

Add reset control for the gigabit interface of the Allwinner R40/V40 CPU

Signed-off-by Lothar Felten <[email protected]>
---
 board/sunxi/gmac.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
board/sunxi/gmac.c +4 -1
index 826650c89b..b2ede37dc3 100644
@@ -13,7 +13,10 @@ void eth_init_board(void)
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
 	/* Set up clock gating */
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#if defined(CONFIG_MACH_SUN8I_R40)
+	setbits_le32(&ccm->ahb_reset1_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
+	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+#elif defined(CONFIG_SUNXI_GEN_SUN6I)
 	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
 #else
Signature · 1 line
2.14.1
#2 lore raw

PATCH v2 2/5 sunxi: R40: add gigabit ethernet reset

Quoted 3 lines · Lothar Felten

Add reset control for the gigabit interface of the Allwinner R40/V40 CPU

Signed-off-by Lothar Felten <[email protected]>
Acked-by Maxime Ripard <[email protected]>

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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author
#3 lore raw

PATCH v2 3/5 sunxi: R40: add gigabit ethernet gpio pinmux

In reply to Lothar Felten

Add gpio mux settings for the Allwinner R40/V40 CPU.
The gigabit ethernet interface can only be routed to a fixed set of pins.

Signed-off-by Lothar Felten <[email protected]>
---
 arch/arm/dts/sun8i-r40.dtsi | 9 +++++++++
 drivers/net/sun8i_emac.c    | 2 ++
 2 files changed, 11 insertions(+)
arch/arm/dts/sun8i-r40.dtsi +9 -0
index 48ec2e855a..ee22f6eb3a 100644
@@ -126,6 +126,15 @@
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
+			gmac_pins_rgmii: gmac_rgmii {
+				pins =	"PA0", "PA1", "PA2",
+					"PA3", "PA4", "PA5", "PA6",
+					"PA7", "PA8", "PA10",
+					"PA11", "PA12", "PA13",
+					"PA15", "PA16";
+				function = "gmac";
+			};
+
 			i2c0_pins: i2c0_pins {
 				pins = "PB0", "PB1";
 				function = "i2c0";
drivers/net/sun8i_emac.c +2 -0
index b6e5dafe83..0cb1a697f3 100644
@@ -68,6 +68,8 @@
 
 #if defined(CONFIG_MACH_SUNXI_H3_H5)
 #define SUN8I_GPD8_GMAC		2
+#elif defined(CONFIG_MACH_SUN8I_R40)
+#define SUN8I_GPD8_GMAC		5
 #else
 #define SUN8I_GPD8_GMAC		4
 #endif
Signature · 1 line
2.14.1
#4 lore raw

PATCH v2 3/5 sunxi: R40: add gigabit ethernet gpio pinmux

Quoted 4 lines · Lothar Felten

Add gpio mux settings for the Allwinner R40/V40 CPU.
The gigabit ethernet interface can only be routed to a fixed set of pins.

Signed-off-by Lothar Felten <[email protected]>
Acked-by Maxime Ripard <[email protected]>

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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author
#5 lore raw

PATCH v2 4/5 sunxi: R40: add gigabit ethernet devicetree node

In reply to Lothar Felten

Add a device tree node for the Allwinner R40/V40 CPU. The syscon node is required by the gmac driver.

Signed-off-by Lothar Felten <[email protected]>
---
 arch/arm/dts/sun8i-r40.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
arch/arm/dts/sun8i-r40.dtsi +28 -0
index ee22f6eb3a..93bf811014 100644
@@ -114,6 +114,12 @@
 		#size-cells = <1>;
 		ranges;
 
+		syscon: syscon at 1c00000 {
+			compatible = "allwinner,sun8i-r40-system-controller",
+				"syscon";
+			reg = <0x01c00000 0x1000>;
+		};
+
 		pio: pinctrl at 1c20800 {
 			compatible = "allwinner,sun8i-r40-pinctrl";
 			reg = <0x01c20800 0x400>;

@@ -168,6 +174,28 @@
 			#size-cells = <0>;
 		};
 
+		gmac: ethernet at 01c50000 {
+			compatible = "allwinner,sun8i-h3-emac";
+			syscon = <&syscon>;
+			reg = <0x01c50000 0x2000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks = <&osc24M>, <&osc24M>;
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_rgmii>;
+			phy-mode = "rgmii";
+			status = "disabled";
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+			};
+		};
+
 		gic: interrupt-controller at 1c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,
Signature · 1 line
2.14.1
#6 lore raw

PATCH v2 4/5 sunxi: R40: add gigabit ethernet devicetree node

Quoted 13 lines · Lothar Felten

Add a device tree node for the Allwinner R40/V40 CPU. The syscon node is required by the gmac driver.

Signed-off-by Lothar Felten <[email protected]>
---
 arch/arm/dts/sun8i-r40.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
arch/arm/dts/sun8i-r40.dtsi +0 -0
index ee22f6eb3a..93bf811014 100644

arch/arm/dts/sun8i-r40.dtsi line 121

Quoted 8 lines
arch/arm/dts/sun8i-r40.dtsi +5 -0
@@ -114,6 +114,12 @@
 		#size-cells = <1>;
 		ranges;
 
+		syscon: syscon at 1c00000 {
+			compatible = "allwinner,sun8i-r40-system-controller",
+				"syscon";
+			reg = <0x01c00000 0x1000>;
+		};

As far as I understood it, the GMAC configuration register is not in the system controller on the R40, but in the clock controller.

Quoted 20 lines
arch/arm/dts/sun8i-r40.dtsi +13 -0
+
 		pio: pinctrl at 1c20800 {
 			compatible = "allwinner,sun8i-r40-pinctrl";
 			reg = <0x01c20800 0x400>;

@@ -168,6 +174,28 @@
 			#size-cells = <0>;
 		};
 
+		gmac: ethernet at 01c50000 {
+			compatible = "allwinner,sun8i-h3-emac";
+			syscon = <&syscon>;
+			reg = <0x01c50000 0x2000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks = <&osc24M>, <&osc24M>;
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_rgmii>;

arch/arm/dts/sun8i-r40.dtsi line 198

Quoted 10 lines
arch/arm/dts/sun8i-r40.dtsi +10 -0
+			phy-mode = "rgmii";
+			status = "disabled";
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,dwmac-mdio";
+			};
+		};
+

And I guess this is just some temporary binding while waiting for "real" ones to land in Linux?

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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author
#7 lore raw

PATCH v2 5/5 configs: Bananapi_M2_Ultra: enable gigabit on the Bananapi M2U

In reply to Lothar Felten

Enable the gigabit ethernet for the Bananapi M2 Ultra board. Tested on BananaPi M2 Berry (R40), custom board (V40).

Signed-off-by Lothar Felten <[email protected]>
---
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
 configs/Bananapi_M2_Ultra_defconfig          |  4 ++++
 2 files changed, 18 insertions(+)
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +14 -0
index ab471ab0bf..25f2112fbf 100644
@@ -67,3 +67,17 @@
 	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_pins_rgmii>;
+	status = "okay";
+	phy-handle = <&rgmii_phy>;
+};
+
+&mdio {
+	rgmii_phy: ethernet-phy at 1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
configs/Bananapi_M2_Ultra_defconfig +4 -0
index 37cc2df5dc..e4e943dc49 100644
@@ -17,3 +17,7 @@ CONFIG_AXP_DLDO4_VOLT=2500
 CONFIG_AXP_ELDO3_VOLT=1200
 CONFIG_SCSI=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_MACPWR="PA17"
Signature · 1 line
2.14.1
#8 lore raw

PATCH v2 5/5 configs: Bananapi_M2_Ultra: enable gigabit on the Bananapi M2U

Quoted 36 lines · Lothar Felten

Enable the gigabit ethernet for the Bananapi M2 Ultra board. Tested on BananaPi M2 Berry (R40), custom board (V40).

Signed-off-by Lothar Felten <[email protected]>
---
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
 configs/Bananapi_M2_Ultra_defconfig          |  4 ++++
 2 files changed, 18 insertions(+)
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +14 -0
index ab471ab0bf..25f2112fbf 100644
@@ -67,3 +67,17 @@
 	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_pins_rgmii>;
+	status = "okay";
+	phy-handle = <&rgmii_phy>;
+};
+
+&mdio {
+	rgmii_phy: ethernet-phy at 1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
configs/Bananapi_M2_Ultra_defconfig +0 -0
index 37cc2df5dc..e4e943dc49 100644

configs/Bananapi_M2_Ultra_defconfig CONFIG_AXP_DLDO4_VOLT=2500 · line 22

Quoted 6 lines
configs/Bananapi_M2_Ultra_defconfig +3 -0
@@ -17,3 +17,7 @@ CONFIG_AXP_DLDO4_VOLT=2500
 CONFIG_AXP_ELDO3_VOLT=1200
 CONFIG_SCSI=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y

I'm not sure why you'd need both?

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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author
#9 lore raw

PATCH v2 5/5 configs: Bananapi_M2_Ultra: enable gigabit on the Bananapi M2U

Quoted 39 lines · Maxime Ripard
Quoted 38 lines · Lothar Felten

Enable the gigabit ethernet for the Bananapi M2 Ultra board. Tested on BananaPi M2 Berry (R40), custom board (V40).

Signed-off-by Lothar Felten <[email protected]>
---
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 14 ++++++++++++++
 configs/Bananapi_M2_Ultra_defconfig          |  4 ++++
 2 files changed, 18 insertions(+)
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +14 -0
index ab471ab0bf..25f2112fbf 100644
@@ -67,3 +67,17 @@
 	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_pins_rgmii>;
+	status = "okay";
+	phy-handle = <&rgmii_phy>;
+};
+
+&mdio {
+	rgmii_phy: ethernet-phy at 1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
configs/Bananapi_M2_Ultra_defconfig +0 -0
index 37cc2df5dc..e4e943dc49 100644
@@ -17,3 +17,7 @@ CONFIG_AXP_DLDO4_VOLT=2500
Quoted 8 lines

configs/Bananapi_M2_Ultra_defconfig CONFIG_AXP_DLDO4_VOLT=2500 · line 22

Quoted 6 lines
configs/Bananapi_M2_Ultra_defconfig +3 -0
 CONFIG_AXP_ELDO3_VOLT=1200
 CONFIG_SCSI=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y

I'm not sure why you'd need both?

I used the SUN8I driver and SUN7I GMAC config approach.
In the new patch v3 I cleaned this up: the config is now in the driver, and sysconf optional for R40 SoCs.

Lothar

Quoted 3 lines

Maxime

#10 lore raw

PATCH v2 1/5 sunxi: R40: add gigabit ethernet clocks

In reply to Lothar Felten
Quoted 4 lines · Lothar Felten

Add clock control entries for the gigabit interface of the Allwinner R40/V40 CPU

Signed-off-by Lothar Felten <[email protected]>
Acked-by Maxime Ripard <[email protected]>

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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