clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
Martin Blumenstingl
reviewerPATCH 1/1 clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
meson8b_cpu_clk has two parent clocks:
- meson8b_xtal
- meson8b_cpu_scale_out_sel
The name of the "xtal" clock parent is specified correctly. However, there is a typo in the name of the second parent clock. The meson8b_cpu_scale_out_sel definition uses the name "cpu_scale_out_sel" (which matches the name from the datasheet). However, the mux parent definition uses the name "cpu_out_sel" which does not match any existing clock.
--- drivers/clk/meson/meson8b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/meson/meson8b.c +2 -1
@@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = { .hw.init = &(struct clk_init_data){ .name ="cpu_clk" , .ops = &clk_regmap_mux_ro_ops, - .parent_names = (const char *[]){"xtal" ,"cpu_out_sel" }, + .parent_names = (const char *[]){"xtal" , +"cpu_scale_out_sel" }, .num_parents =2 , .flags = (CLK_SET_RATE_PARENT |CLK_SET_RATE_NO_REPARENT ),
Signature · 1 line
2.17.0
Jerome Brunet
maintainerPATCH 1/1 clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
Quoted 11 lines · Martin Blumenstingl
meson8b_cpu_clkhas two parent clocks:
-meson8b_xtal
-meson8b_cpu_scale_out_selThe name of the "xtal" clock parent is specified correctly. However, there is a typo in the name of the second parent clock. The
meson8b_cpu_scale_out_seldefinition uses the name "cpu_scale_out_sel" (which matches the name from the datasheet). However, the mux parent definition uses the name "cpu_out_sel" which does not match any existing clock.
Quoted 2 lines
Fixes 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock")Signed-off-by Martin Blumenstingl <[email protected]>
Roohhh ... Sorry about that :(
I'll take it along with the other typo fix. Thx Martin !
Quoted 18 lines
--- drivers/clk/meson/meson8b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/clk/meson/meson8b.c +2
-1@@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = { .hw.init = &(struct clk_init_data){ .name ="cpu_clk" , .ops = &clk_regmap_mux_ro_ops, - .parent_names = (const char *[]){"xtal" ,"cpu_out_sel" }, + .parent_names = (const char *[]){"xtal" , +"cpu_scale_out_sel" }, .num_parents =2 , .flags = (CLK_SET_RATE_PARENT |CLK_SET_RATE_NO_REPARENT ),