rtlwifi: halmac: Add new module halmac

index d27e33960e77..c8542b87cc2b 100644
@@ -2305,6 +2305,13 @@ struct rtl_hal_ops {
 	u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
 	void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
 				    u8 *val);
+	/* ops for halmac cb */
+	bool (*halmac_cb_init_mac_register)(struct rtl_priv *rtlpriv);
+	bool (*halmac_cb_init_bb_rf_register)(struct rtl_priv *rtlpriv);
+	bool (*halmac_cb_write_data_rsvd_page)(struct rtl_priv *rtlpriv,
+					       u8 *buf, u32 size);
+	bool (*halmac_cb_write_data_h2c)(struct rtl_priv *rtlpriv, u8 *buf,
+					 u32 size);
 };
 
 struct rtl_intf_ops {

@@ -2687,6 +2694,54 @@ struct rtl_btc_ops {
 	bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
 };
 
+struct rtl_halmac_ops {
+	int (*halmac_init_adapter)(struct rtl_priv *rtlpriv);
+	int (*halmac_deinit_adapter)(struct rtl_priv *rtlpriv);
+	int (*halmac_init_hal)(struct rtl_priv *rtlpriv);
+	int (*halmac_deinit_hal)(struct rtl_priv *rtlpriv);
+	int (*halmac_poweron)(struct rtl_priv *rtlpriv);
+	int (*halmac_poweroff)(struct rtl_priv *rtlpriv);
+
+	int (*halmac_phy_power_switch)(struct rtl_priv *rtlpriv, u8 enable);
+	int (*halmac_set_mac_address)(struct rtl_priv *rtlpriv, u8 hwport,
+				      u8 *addr);
+	int (*halmac_set_bssid)(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
+
+	int (*halmac_get_physical_efuse_size)(struct rtl_priv *rtlpriv,
+					      u32 *size);
+	int (*halmac_read_physical_efuse_map)(struct rtl_priv *rtlpriv,
+					      u8 *map, u32 size);
+	int (*halmac_get_logical_efuse_size)(struct rtl_priv *rtlpriv,
+					     u32 *size);
+	int (*halmac_read_logical_efuse_map)(struct rtl_priv *rtlpriv, u8 *map,
+					     u32 size);
+
+	int (*halmac_set_bandwidth)(struct rtl_priv *rtlpriv, u8 channel,
+				    u8 pri_ch_idx, u8 bw);
+
+	int (*halmac_c2h_handle)(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
+
+	int (*halmac_chk_txdesc)(struct rtl_priv *rtlpriv, u8 *txdesc,
+				 u32 size);
+	int (*halmac_iqk)(struct rtl_priv *rtlpriv, u8 clear, u8 segment);
+};
+
+struct rtl_halmac_indicator {
+	struct completion *comp;
+	u32 wait_ms;
+
+	u8 *buffer;
+	u32 buf_size;
+	u32 ret_size;
+	u32 status;
+};
+
+struct rtl_halmac {
+	const struct rtl_halmac_ops *ops;
+	void *internal;	/* internal context of halmac, i.e. PHALMAC_ADAPTER */
+	struct rtl_halmac_indicator *indicator;	/* size=10 */
+};
+
 struct proxim {
 	bool proxim_on;
 

@@ -2792,6 +2847,9 @@ struct rtl_priv {
 	/*for bt coexist use*/
 	struct bt_coexist_info btcoexist;
 
+	/* halmac for newer ICs */
+	struct rtl_halmac halmac;
+
 	/* separate 92ee from other ICs,
 	 * 92ee use new trx flow.
 	 */

index ad6834af618b..90c41c17d678 100644
@@ -106,6 +106,7 @@
 #define COMP_BT_COEXIST			BIT(30)
 #define COMP_IQK			BIT(31)
 #define COMP_TX_REPORT			BIT_ULL(32)
+#define COMP_HALMAC			BIT_ULL(33)
 
 /*--------------------------------------------------------------
 		Define the rt_print components

new file mode 100644
index 000000000000..5560cd1f98ed
@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __RTL_DMINFO_H__
+#define __RTL_DMINFO_H__
+
+enum bb_path {
+	BB_PATH_A = 0x00000001,
+	BB_PATH_B = 0x00000002,
+	BB_PATH_C = 0x00000004,
+	BB_PATH_D = 0x00000008,
+
+	BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
+	BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
+	BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
+	BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
+	BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
+	BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
+
+	BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
+	BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
+	BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
+	BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
+
+	BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
+};
+
+#endif

index c8542b87cc2b..c32985cfe48d 100644
@@ -35,6 +35,7 @@
 #include <linux/usb.h>
 #include <net/mac80211.h>
 #include <linux/completion.h>
+#include "dmdef.h"
 #include "debug.h"
 
 #define	MASKBYTE0				0xff

new file mode 100644
index 000000000000..d6cce79a460d
@@ -0,0 +1,157 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_STATE_MACHINE_H_
+#define _HALMAC_STATE_MACHINE_H_
+
+enum halmac_dlfw_state {
+	HALMAC_DLFW_NONE = 0,
+	HALMAC_DLFW_DONE = 1,
+	HALMAC_GEN_INFO_SENT = 2,
+
+	/* Data CPU firmware download framework */
+	HALMAC_DLFW_INIT = 0x11,
+	HALMAC_DLFW_START = 0x12,
+	HALMAC_DLFW_CONF_READY = 0x13,
+	HALMAC_DLFW_CPU_READY = 0x14,
+	HALMAC_DLFW_MEM_READY = 0x15,
+	HALMAC_DLFW_SW_READY = 0x16,
+	HALMAC_DLFW_OFLD_READY = 0x17,
+
+	HALMAC_DLFW_UNDEFINED = 0x7F,
+};
+
+enum halmac_gpio_cfg_state {
+	HALMAC_GPIO_CFG_STATE_IDLE = 0,
+	HALMAC_GPIO_CFG_STATE_BUSY = 1,
+	HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_rsvd_pg_state {
+	HALMAC_RSVD_PG_STATE_IDLE = 0,
+	HALMAC_RSVD_PG_STATE_BUSY = 1,
+	HALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_api_state {
+	HALMAC_API_STATE_INIT = 0,
+	HALMAC_API_STATE_HALT = 1,
+	HALMAC_API_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_construct_state {
+	HALMAC_CMD_CNSTR_IDLE = 0,
+	HALMAC_CMD_CNSTR_BUSY = 1,
+	HALMAC_CMD_CNSTR_H2C_SENT = 2,
+	HALMAC_CMD_CNSTR_CNSTR = 3,
+	HALMAC_CMD_CNSTR_BUF_CLR = 4,
+	HALMAC_CMD_CNSTR_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_process_status {
+	HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
+	HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
+	HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
+	HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
+	HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
+	HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
+};
+
+enum halmac_mac_power {
+	HALMAC_MAC_POWER_OFF = 0x0,
+	HALMAC_MAC_POWER_ON = 0x1,
+	HALMAC_MAC_POWER_UNDEFINE = 0x7F,
+};
+
+enum halmac_wlcpu_mode {
+	HALMAC_WLCPU_ACTIVE = 0x0,
+	HALMAC_WLCPU_ENTER_SLEEP = 0x1,
+	HALMAC_WLCPU_SLEEP = 0x2,
+	HALMAC_WLCPU_UNDEFINE = 0x7F,
+};
+
+struct halmac_efuse_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_cfg_param_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_scan_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_update_pkt_state {
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_iqk_state {
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_pwr_tracking_state {
+	enum halmac_cmd_process_status	proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_psd_state {
+	enum halmac_cmd_process_status proc_status;
+	u16 data_size;
+	u16 seg_size;
+	u8 *data;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_fw_snding_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_state {
+	struct halmac_efuse_state efuse_state;
+	struct halmac_cfg_param_state cfg_param_state;
+	struct halmac_scan_state scan_state;
+	struct halmac_update_pkt_state update_pkt_state;
+	struct halmac_iqk_state iqk_state;
+	struct halmac_pwr_tracking_state pwr_trk_state;
+	struct halmac_psd_state psd_state;
+	struct halmac_fw_snding_state fw_snding_state;
+	enum halmac_api_state api_state;
+	enum halmac_mac_power mac_pwr;
+	enum halmac_dlfw_state dlfw_state;
+	enum halmac_wlcpu_mode wlcpu_mode;
+	enum halmac_gpio_cfg_state gpio_cfg_state;
+	enum halmac_rsvd_pg_state rsvd_pg_state;
+};
+
+#endif

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new file mode 100644
index 000000000000..f6ed7b44549c
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_8822B_CFG_H_
+#define _HALMAC_8822B_CFG_H_
+
+#include "../halmac_88xx_cfg.h"
+
+#define TX_FIFO_SIZE_8822B	262144
+#define RX_FIFO_SIZE_8822B	24576
+#define TRX_SHARE_SIZE_8822B	65536
+
+#define RX_DESC_DUMMY_SIZE_8822B	72 /* 8 * 9 Bytes */
+#define RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B	80 /* 8 Byte alignment*/
+
+/* should be 8 Byte alignment*/
+#if (HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE <= \
+	RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B)
+#define RX_FIFO_EXPANDING_UNIT_8822B	(RX_DESC_SIZE_88XX + \
+	RX_DESC_DUMMY_SIZE_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE)
+#else
+#define RX_FIFO_EXPANDING_UNIT_8822B (RX_DESC_SIZE_88XX + \
+	RX_DESC_DUMMY_SIZE_8822B + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B)
+#endif
+
+#define TX_FIFO_SIZE_LA_8822B	(TX_FIFO_SIZE_8822B >>  1)
+#define TX_FIFO_SIZE_RX_EXPAND_1BLK_8822B	\
+		(TX_FIFO_SIZE_8822B - TRX_SHARE_SIZE_8822B)
+#define RX_FIFO_SIZE_RX_EXPAND_1BLK_8822B	\
+		((((RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) << 10)
+#define TX_FIFO_SIZE_RX_EXPAND_2BLK_8822B	\
+		(TX_FIFO_SIZE_8822B - (2 * TRX_SHARE_SIZE_8822B))
+#define RX_FIFO_SIZE_RX_EXPAND_2BLK_8822B	\
+		(RX_FIFO_SIZE_8822B +  (2 * TRX_SHARE_SIZE_8822B))
+#define TX_FIFO_SIZE_RX_EXPAND_3BLK_8822B	\
+		(TX_FIFO_SIZE_8822B - (3 * TRX_SHARE_SIZE_8822B))
+#define RX_FIFO_SIZE_RX_EXPAND_3BLK_8822B	\
+		(RX_FIFO_SIZE_8822B +  (3 * TRX_SHARE_SIZE_8822B))
+
+#define EFUSE_SIZE_8822B		1024
+#define EEPROM_SIZE_8822B		768
+#define BT_EFUSE_SIZE_8822B		128
+
+#define SEC_CAM_NUM_8822B		64
+
+#define OQT_ENTRY_AC_8822B		32
+#define OQT_ENTRY_NOAC_8822B		32
+#define MACID_MAX_8822B			128
+
+#define WLAN_FW_IRAM_MAX_SIZE_8822B	196608
+#define WLAN_FW_DRAM_MAX_SIZE_8822B	49152
+#define WLAN_FW_ERAM_MAX_SIZE_8822B	0
+#define WLAN_FW_MAX_SIZE_8822B		(WLAN_FW_IRAM_MAX_SIZE_8822B + \
+	WLAN_FW_DRAM_MAX_SIZE_8822B + WLAN_FW_ERAM_MAX_SIZE_8822B)
+
+#endif

new file mode 100644
index 000000000000..22514ef4680d
@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_88XX_CFG_H_
+#define _HALMAC_88XX_CFG_H_
+
+#include "../halmac_api.h"
+
+#define TX_PAGE_SIZE_88XX		128
+#define TX_PAGE_SIZE_SHIFT_88XX		7 /* 128 = 2^7 */
+#define TX_ALIGN_SIZE_88XX		8
+#define SDIO_TX_MAX_SIZE_88XX		31744
+#define RX_BUF_FW_88XX			12288
+
+#define TX_DESC_SIZE_88XX		48
+#define RX_DESC_SIZE_88XX		24
+
+#define H2C_PKT_SIZE_88XX		32 /* Only support 32 byte packet now */
+#define H2C_PKT_HDR_SIZE_88XX		8
+#define C2H_DATA_OFFSET_88XX		10
+#define C2H_PKT_BUF_88XX		256
+
+/* HW memory address */
+#define OCPBASE_TXBUF_88XX		0x18780000
+#define OCPBASE_DMEM_88XX		0x00200000
+#define OCPBASE_EMEM_88XX		0x00100000
+
+#endif

new file mode 100644
index 000000000000..c03d4d0e4e8a
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_BD_NIC_H_
+#define _HALMAC_RX_BD_NIC_H_
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 31, 1)
+#define GET_RX_BD_TOTALRXPKTSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_RXTAG(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_FS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 15, 1)
+#define GET_RX_BD_LS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 14, 1)
+#define GET_RX_BD_RXBUFFSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 0, 14)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x04, 0, 32)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x08, 0, 32)
+
+#endif

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new file mode 100644
index 000000000000..3d43de98bb46
@@ -0,0 +1,847 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_gpio_8822b.h"
+#include "../halmac_gpio_88xx.h"
+
+/* GPIO0 definition */
+#define GPIO0_BT_GPIO0_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO0_BT_ACT_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO0_WL_ACT_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO0_WLMAC_DBG_GPIO0_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO0_WLPHY_DBG_GPIO0_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO0_BT_DBG_GPIO0_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+	0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO0_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO1 definition */
+#define GPIO1_BT_GPIO1_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO1_BT_3DD_SYNC_A_8822B	\
+	{HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO1_WL_CK_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO1_BT_CK_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO1_WLMAC_DBG_GPIO1_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO1_WLPHY_DBG_GPIO1_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO1_BT_DBG_GPIO1_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO1_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO2 definition */
+#define GPIO2_BT_GPIO2_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO2_WL_STATE_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO2_BT_STATE_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO2_WLMAC_DBG_GPIO2_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO2_WLPHY_DBG_GPIO2_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO2_BT_DBG_GPIO2_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO2_RFE_CTRL_5_8822B	\
+	{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(2), BIT(2)}
+#define GPIO2_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO3 definition */
+#define GPIO3_BT_GPIO3_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO3_WL_PRI_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO3_BT_PRI_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO3_WLMAC_DBG_GPIO3_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO3_WLPHY_DBG_GPIO3_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO3_BT_DBG_GPIO3_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO3_RFE_CTRL_4_8822B	\
+	{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(2), BIT(2)}
+#define GPIO3_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO4 definition */
+#define GPIO4_BT_SPI_D0_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO4_WL_SPI_D0_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO4_SDIO_INT_8822B	\
+	{HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x72, BIT(2), BIT(2)}
+#define GPIO4_JTAG_TRST_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO4_DBG_GNT_WL_8822B	\
+	{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x73, BIT(3), BIT(3)}
+#define GPIO4_WLMAC_DBG_GPIO4_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO4_WLPHY_DBG_GPIO4_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO4_BT_DBG_GPIO4_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO4_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO5 definition */
+#define GPIO5_BT_SPI_D1_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO5_WL_SPI_D1_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO5_JTAG_TDI_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO5_DBG_GNT_BT_8822B	\
+	{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x73, BIT(3), BIT(3)}
+#define GPIO5_WLMAC_DBG_GPIO5_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO5_WLPHY_DBG_GPIO5_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO5_BT_DBG_GPIO5_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO5_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO6 definition */
+#define GPIO6_BT_SPI_D2_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO6_WL_SPI_D2_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO6_EEDO_8822B	\
+	{HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x40, BIT(4), BIT(4)}
+#define GPIO6_JTAG_TDO_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO6_BT_3DD_SYNC_B_8822B	\
+	{HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x67, BIT(1), BIT(1)}
+#define GPIO6_BT_GPIO18_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x67, BIT(1), BIT(1)}
+#define GPIO6_SIN_8822B	\
+	{HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x41, BIT(0), BIT(0)}
+#define GPIO6_WLMAC_DBG_GPIO6_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO6_WLPHY_DBG_GPIO6_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO6_BT_DBG_GPIO6_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO6_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO7 definition */
+#define GPIO7_BT_SPI_D3_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO7_WL_SPI_D3_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO7_EEDI_8822B	\
+	{HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(4), BIT(4)}
+#define GPIO7_JTAG_TMS_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO7_BT_GPIO16_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x67, BIT(2), BIT(2)}
+#define GPIO7_SOUT_8822B	\
+	{HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x41, BIT(0), BIT(0)}
+#define GPIO7_WLMAC_DBG_GPIO7_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO7_WLPHY_DBG_GPIO7_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO7_BT_DBG_GPIO7_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO7_SW_IO_8822B \
+	{HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO8 definition */
+#define GPIO8_WL_EXT_WOL_8822B	\
+	{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, \
+	 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)}
+#define GPIO8_WL_LED_8822B	\
+	{HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, \
+	 0x4e, BIT(5), BIT(5)}
+#define GPIO8_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO9 definition */
+#define GPIO9_DIS_WL_N_8822B	\
+	{HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)}
+#define GPIO9_WL_EXT_WOL_8822B	\
+	{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x4a, BIT(0) | BIT(1), BIT(0)}
+#define GPIO9_USCTS0_8822B	\
+	{HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO9_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO10 definition */
+#define GPIO10_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO11 definition */
+#define GPIO11_DIS_BT_N_8822B	\
+	{HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, \
+	 0x6a, BIT(0), BIT(0)}
+#define GPIO11_USOUT0_8822B	\
+	{HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO11_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO12 definition */
+#define GPIO12_USIN0_8822B	\
+	{HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO12_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO13 definition */
+#define GPIO13_BT_WAKE_8822B	\
+	{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, \
+	 0x4e, BIT(6), BIT(6)}
+#define GPIO13_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO14 definition */
+#define GPIO14_UART_WAKE_8822B	\
+	{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, \
+	 0x4e, BIT(6), BIT(6)}
+#define GPIO14_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO15 definition */
+#define GPIO15_EXT_XTAL_8822B	\
+	{HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, \
+	 0x66, BIT(7), BIT(7)}
+#define GPIO15_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO0_8822B[] = {
+	GPIO0_BT_GPIO0_8822B,
+	GPIO0_BT_ACT_8822B,
+	GPIO0_WL_ACT_8822B,
+	GPIO0_WLMAC_DBG_GPIO0_8822B,
+	GPIO0_WLPHY_DBG_GPIO0_8822B,
+	GPIO0_BT_DBG_GPIO0_8822B,
+	GPIO0_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO1_8822B[] = {
+	GPIO1_BT_GPIO1_8822B,
+	GPIO1_BT_3DD_SYNC_A_8822B,
+	GPIO1_WL_CK_8822B,
+	GPIO1_BT_CK_8822B,
+	GPIO1_WLMAC_DBG_GPIO1_8822B,
+	GPIO1_WLPHY_DBG_GPIO1_8822B,
+	GPIO1_BT_DBG_GPIO1_8822B,
+	GPIO1_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO2_8822B[] = {
+	GPIO2_BT_GPIO2_8822B,
+	GPIO2_WL_STATE_8822B,
+	GPIO2_BT_STATE_8822B,
+	GPIO2_WLMAC_DBG_GPIO2_8822B,
+	GPIO2_WLPHY_DBG_GPIO2_8822B,
+	GPIO2_BT_DBG_GPIO2_8822B,
+	GPIO2_RFE_CTRL_5_8822B,
+	GPIO2_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO3_8822B[] = {
+	GPIO3_BT_GPIO3_8822B,
+	GPIO3_WL_PRI_8822B,
+	GPIO3_BT_PRI_8822B,
+	GPIO3_WLMAC_DBG_GPIO3_8822B,
+	GPIO3_WLPHY_DBG_GPIO3_8822B,
+	GPIO3_BT_DBG_GPIO3_8822B,
+	GPIO3_RFE_CTRL_4_8822B,
+	GPIO3_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO4_8822B[] = {
+	GPIO4_BT_SPI_D0_8822B,
+	GPIO4_WL_SPI_D0_8822B,
+	GPIO4_SDIO_INT_8822B,
+	GPIO4_JTAG_TRST_8822B,
+	GPIO4_DBG_GNT_WL_8822B,
+	GPIO4_WLMAC_DBG_GPIO4_8822B,
+	GPIO4_WLPHY_DBG_GPIO4_8822B,
+	GPIO4_BT_DBG_GPIO4_8822B,
+	GPIO4_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO5_8822B[] = {
+	GPIO5_BT_SPI_D1_8822B,
+	GPIO5_WL_SPI_D1_8822B,
+	GPIO5_JTAG_TDI_8822B,
+	GPIO5_DBG_GNT_BT_8822B,
+	GPIO5_WLMAC_DBG_GPIO5_8822B,
+	GPIO5_WLPHY_DBG_GPIO5_8822B,
+	GPIO5_BT_DBG_GPIO5_8822B,
+	GPIO5_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO6_8822B[] = {
+	GPIO6_BT_SPI_D2_8822B,
+	GPIO6_WL_SPI_D2_8822B,
+	GPIO6_EEDO_8822B,
+	GPIO6_JTAG_TDO_8822B,
+	GPIO6_BT_3DD_SYNC_B_8822B,
+	GPIO6_BT_GPIO18_8822B,
+	GPIO6_SIN_8822B,
+	GPIO6_WLMAC_DBG_GPIO6_8822B,
+	GPIO6_WLPHY_DBG_GPIO6_8822B,
+	GPIO6_BT_DBG_GPIO6_8822B,
+	GPIO6_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO7_8822B[] = {
+	GPIO7_BT_SPI_D3_8822B,
+	GPIO7_WL_SPI_D3_8822B,
+	GPIO7_EEDI_8822B,
+	GPIO7_JTAG_TMS_8822B,
+	GPIO7_BT_GPIO16_8822B,
+	GPIO7_SOUT_8822B,
+	GPIO7_WLMAC_DBG_GPIO7_8822B,
+	GPIO7_WLPHY_DBG_GPIO7_8822B,
+	GPIO7_BT_DBG_GPIO7_8822B,
+	GPIO7_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO8_8822B[] = {
+	GPIO8_WL_EXT_WOL_8822B,
+	GPIO8_WL_LED_8822B,
+	GPIO8_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO9_8822B[] = {
+	GPIO9_DIS_WL_N_8822B,
+	GPIO9_WL_EXT_WOL_8822B,
+	GPIO9_USCTS0_8822B,
+	GPIO9_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO10_8822B[] = {
+	GPIO10_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO11_8822B[] = {
+	GPIO11_DIS_BT_N_8822B,
+	GPIO11_USOUT0_8822B,
+	GPIO11_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO12_8822B[] = {
+	GPIO12_USIN0_8822B,
+	GPIO12_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO13_8822B[] = {
+	GPIO13_BT_WAKE_8822B,
+	GPIO13_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO14_8822B[] = {
+	GPIO14_UART_WAKE_8822B,
+	GPIO14_SW_IO_8822B
+};
+
+static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO15_8822B[] = {
+	GPIO15_EXT_XTAL_8822B,
+	GPIO15_SW_IO_8822B
+};
+
+static enum halmac_ret_status
+get_pinmux_list_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func,
+		      const struct halmac_gpio_pimux_list **list,
+		      u32 *list_size, u32 *gpio_id);
+
+static enum halmac_ret_status
+chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func);
+
+/**
+ * pinmux_get_func_8822b() -get current gpio status
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * @enable : function is enable(1) or disable(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_get_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func, u8 *enable)
+{
+	u32 list_size;
+	u32 cur_func;
+	u32 gpio_id;
+	enum halmac_ret_status status;
+	const struct halmac_gpio_pimux_list *list = NULL;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size,
+				       &gpio_id);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_parser_88xx(adapter, list, list_size, gpio_id,
+				    &cur_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_WL_LED:
+		*enable = (cur_func == HALMAC_WL_LED) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		*enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		*enable = (cur_func == HALMAC_GPIO13_14_WL_CTRL_EN) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		*enable = (cur_func == HALMAC_SW_IO) ? 1 : 0;
+		break;
+	default:
+		*enable = 0;
+		return HALMAC_RET_GET_PINMUX_ERR;
+	}
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_set_func_8822b() -set gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_set_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func)
+{
+	u32 list_size;
+	u32 gpio_id;
+	enum halmac_ret_status status;
+	const struct halmac_gpio_pimux_list *list = NULL;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG,
+		 "func name : %d\n", gpio_func);
+
+	status = chk_pinmux_valid_8822b(adapter, gpio_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size,
+				       &gpio_id);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_switch_88xx(adapter, list, list_size, gpio_id,
+				    gpio_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_record_88xx(adapter, gpio_func, 1);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_free_func_8822b() -free locked gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_free_func_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func)
+{
+	struct halmac_pinmux_info *info = &adapter->pinmux_info;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		info->sw_io_0 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		info->sw_io_1 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		info->sw_io_2 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		info->sw_io_3 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		info->sw_io_4 = 0;
+		info->sdio_int = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		info->sw_io_5 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		info->sw_io_6 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		info->sw_io_7 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		info->sw_io_8 = 0;
+		info->wl_led = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		info->sw_io_9 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		info->sw_io_10 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		info->sw_io_11 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		info->sw_io_12 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		info->bt_dev_wake = 0;
+		info->sw_io_13 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+		info->bt_host_wake = 0;
+		info->sw_io_14 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		info->sw_io_15 = 0;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "func : %X\n",
+		 gpio_func);
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_pinmux_list_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func,
+		      const struct halmac_gpio_pimux_list **list,
+		      u32 *list_size, u32 *gpio_id)
+{
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		*list = PINMUX_LIST_GPIO0_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8822B);
+		*gpio_id = HALMAC_GPIO0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		*list = PINMUX_LIST_GPIO1_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8822B);
+		*gpio_id = HALMAC_GPIO1;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		*list = PINMUX_LIST_GPIO2_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8822B);
+		*gpio_id = HALMAC_GPIO2;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		*list = PINMUX_LIST_GPIO3_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8822B);
+		*gpio_id = HALMAC_GPIO3;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		*list = PINMUX_LIST_GPIO4_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8822B);
+		*gpio_id = HALMAC_GPIO4;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		*list = PINMUX_LIST_GPIO5_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8822B);
+		*gpio_id = HALMAC_GPIO5;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		*list = PINMUX_LIST_GPIO6_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8822B);
+		*gpio_id = HALMAC_GPIO6;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		*list = PINMUX_LIST_GPIO7_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8822B);
+		*gpio_id = HALMAC_GPIO7;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		*list = PINMUX_LIST_GPIO8_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8822B);
+		*gpio_id = HALMAC_GPIO8;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		*list = PINMUX_LIST_GPIO9_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8822B);
+		*gpio_id = HALMAC_GPIO9;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		*list = PINMUX_LIST_GPIO10_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8822B);
+		*gpio_id = HALMAC_GPIO10;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		*list = PINMUX_LIST_GPIO11_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8822B);
+		*gpio_id = HALMAC_GPIO11;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		*list = PINMUX_LIST_GPIO12_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8822B);
+		*gpio_id = HALMAC_GPIO12;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		*list = PINMUX_LIST_GPIO13_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8822B);
+		*gpio_id = HALMAC_GPIO13;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+		*list = PINMUX_LIST_GPIO14_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8822B);
+		*gpio_id = HALMAC_GPIO14;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		*list = PINMUX_LIST_GPIO15_8822B;
+		*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8822B);
+		*gpio_id = HALMAC_GPIO15;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func)
+{
+	struct halmac_pinmux_info *info = &adapter->pinmux_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		if (info->sw_io_0 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		if (info->sw_io_1 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		if (info->sw_io_2 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		if (info->sw_io_3 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		if (info->sw_io_4 == 1 || info->sdio_int == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		if (info->sw_io_5 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		if (info->sw_io_6 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		if (info->sw_io_7 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		if (info->sw_io_8 == 1 || info->wl_led == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		if (info->sw_io_9 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		if (info->sw_io_10 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		if (info->sw_io_11 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		if (info->sw_io_12 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
+		if (info->sw_io_13 == 1 || info->bt_dev_wake == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
+		if (info->sw_io_14 == 1 || info->bt_host_wake == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		if (info->sw_io_15 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG,
+		 "chk_pinmux_valid func : %X status : %X\n", gpio_func, status);
+
+	return status;
+}

new file mode 100644
index 000000000000..f5d6d315ac3c
@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_GPIO_8822B_H_
+#define _HALMAC_GPIO_8822B_H_
+
+#include "../../halmac_api.h"
+#include "../../halmac_gpio_cmd.h"
+
+enum halmac_ret_status
+pinmux_get_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func, u8 *enable);
+
+enum halmac_ret_status
+pinmux_set_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func);
+
+enum halmac_ret_status
+pinmux_free_func_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func);
+
+#endif/* _HALMAC_GPIO_8822B_H_ */

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new file mode 100644
index 000000000000..5aab588eb094
@@ -0,0 +1,396 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pwr_seq_8822b.h"
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x004A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
+	{0x0300,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0301,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0012,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0012,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0001,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWR_DELAY_MS},
+	{0x0000,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
+	{0x0075,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x0075,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0xFF1A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
+	{0x10C3,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(0), 0},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+	{0x10A8,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x10A9,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xef},
+	{0x10AA,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x0c},
+	{0x0068,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0029,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xF9},
+	{0x0024,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0x0074,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0x00AF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0003,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+	{0x001F,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x00EF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0xFF1A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x30},
+	{0x0049,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x10C3,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+	{0x0000,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0007,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+	{0x004A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), 0},
+	{0x004F,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0046,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0x0046,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0062,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0081,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0044,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0040,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x90},
+	{0x0041,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},
+	{0x0042,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Card Enable Array */
+struct halmac_wlan_pwr_cfg *card_en_flow_8822b[] = {
+	TRANS_CARDDIS_TO_CARDEMU_8822B,
+	TRANS_CARDEMU_TO_ACT_8822B,
+	NULL
+};
+
+/* Card Disable Array */
+struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[] = {
+	TRANS_ACT_TO_CARDEMU_8822B,
+	TRANS_CARDEMU_TO_CARDDIS_8822B,
+	NULL
+};

new file mode 100644
index 000000000000..76d39b944a02
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_POWER_SEQUENCE_8822B
+#define HALMAC_POWER_SEQUENCE_8822B
+
+#include "../../halmac_pwr_seq_cmd.h"
+
+#define HALMAC_8822B_PWR_SEQ_VER  "V25"
+
+extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[];
+
+#endif

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new file mode 100644
index 000000000000..3d51acb5857e
@@ -0,0 +1,1918 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_efuse_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#define RSVD_EFUSE_SIZE		16
+#define RSVD_CS_EFUSE_SIZE	24
+#define PROTECT_EFUSE_SIZE	96
+#define FEATURE_DUMP_PHY_EFUSE	HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE
+#define FEATURE_DUMP_LOG_EFUSE	HALMAC_FEATURE_DUMP_LOGICAL_EFUSE
+
+static enum halmac_cmd_construct_state
+efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_dump_efuse_88xx(struct halmac_adapter *adapter,
+		     enum halmac_efuse_read_cfg cfg);
+
+static enum halmac_ret_status
+read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		   u8 *map);
+
+static enum halmac_ret_status
+eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
+
+static enum halmac_ret_status
+read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map);
+
+static enum halmac_ret_status
+proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+			  struct halmac_pg_efuse_info *info,
+			  enum halmac_efuse_read_cfg cfg);
+
+static enum halmac_ret_status
+dump_efuse_fw_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+dump_efuse_drv_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+static enum halmac_ret_status
+update_eeprom_mask_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static enum halmac_ret_status
+check_efuse_enough_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static enum halmac_ret_status
+pg_extend_efuse_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info, u8 word_en,
+		     u8 pre_word_en, u32 eeprom_offset);
+
+static enum halmac_ret_status
+proc_pg_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 word_en,
+		   u8 pre_word_en, u32 eeprom_offset);
+
+static enum halmac_ret_status
+program_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static void
+mask_eeprom_88xx(struct halmac_adapter *adapter,
+		 struct halmac_pg_efuse_info *info);
+
+/**
+ * dump_efuse_map_88xx() - dump "physical" efuse map
+ * @adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_efuse_map_88xx(struct halmac_adapter *adapter,
+		    enum halmac_efuse_read_cfg cfg)
+{
+	u8 *map = NULL;
+	u8 *efuse_map;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	if (cfg == HALMAC_EFUSE_R_FW &&
+	    halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "cfg = %d\n",
+		 cfg);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+		pr_err("Dump efuse in suspend\n");
+
+	*proc_status = HALMAC_CMD_PROCESS_IDLE;
+	adapter->evnt.phy_efuse_map = 1;
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank!!\n");
+		return status;
+	}
+
+	status = proc_dump_efuse_88xx(adapter, cfg);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("dump efuse!!\n");
+		return status;
+	}
+
+	if (adapter->efuse_map_valid == 1) {
+		*proc_status = HALMAC_CMD_PROCESS_DONE;
+		efuse_map = adapter->efuse_map;
+
+		map = kzalloc(efuse_size, GFP_KERNEL);
+		if (!map)
+			return HALMAC_RET_MALLOC_FAIL;
+		memset(map, 0xFF, efuse_size);
+		mutex_lock(&adapter->efuse_mutex);
+		memcpy(map, efuse_map, efuse_size - PROTECT_EFUSE_SIZE);
+		memcpy(map + efuse_size - PROTECT_EFUSE_SIZE +
+		       RSVD_CS_EFUSE_SIZE,
+		       efuse_map + efuse_size - PROTECT_EFUSE_SIZE +
+		       RSVD_CS_EFUSE_SIZE,
+		       PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
+		       RSVD_CS_EFUSE_SIZE);
+		mutex_unlock(&adapter->efuse_mutex);
+
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
+				*proc_status, map, efuse_size);
+		adapter->evnt.phy_efuse_map = 0;
+
+		kfree(map);
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_efuse_map_bt_88xx() - dump "BT physical" efuse map
+ * @adapter : the adapter of halmac
+ * @bank : bt efuse bank
+ * @size : bt efuse map size. get from halmac_get_efuse_size API
+ * @map : bt efuse map
+ * Author : Soar / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank, u32 size, u8 *map)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	if (adapter->hw_cfg_info.bt_efuse_size != size)
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+
+	if (bank >= HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+		pr_err("Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, bank);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank!!\n");
+		return status;
+	}
+
+	status = read_hw_efuse_88xx(adapter, 0, size, map);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("read hw efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * write_efuse_bt_88xx() - write "BT physical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : Write value
+ * @map : bt efuse map
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,
+		    enum halmac_efuse_bank bank)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (offset >= adapter->hw_cfg_info.efuse_size) {
+		pr_err("Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+		pr_err("Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, bank);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank!!\n");
+		return status;
+	}
+
+	status = write_hw_efuse_88xx(adapter, offset, value);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("write efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_efuse_bt_88xx() - read "BT physical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : 1 byte efuse value
+ * @bank : efuse bank
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
+		   enum halmac_efuse_bank bank)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (offset >= adapter->hw_cfg_info.efuse_size) {
+		pr_err("Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+		pr_err("Undefined BT bank\n");
+		return HALMAC_RET_EFUSE_BANK_INCORRECT;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, bank);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank\n");
+		return status;
+	}
+
+	status = read_efuse_88xx(adapter, offset, 1, value);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("read efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_efuse_auto_check_88xx() - check efuse after writing it
+ * @adapter : the adapter of halmac
+ * @enable : 1, enable efuse auto check. others, disable
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	adapter->efuse_auto_check_en = enable;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_efuse_available_size_88xx() - get efuse available size
+ * @adapter : the adapter of halmac
+ * @size : physical efuse available size
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+	enum halmac_ret_status status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	status = dump_log_efuse_map_88xx(adapter, HALMAC_EFUSE_R_DRV);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	*size = adapter->hw_cfg_info.efuse_size - PROTECT_EFUSE_SIZE -
+		adapter->efuse_end;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_efuse_size_88xx() - get "physical" efuse size
+ * @adapter : the adapter of halmac
+ * @size : physical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	*size = adapter->hw_cfg_info.efuse_size;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_log_efuse_size_88xx() - get "logical" efuse size
+ * @adapter : the adapter of halmac
+ * @size : logical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	*size = adapter->hw_cfg_info.eeprom_size;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_log_efuse_map_88xx() - dump "logical" efuse map
+ * @adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
+			enum halmac_efuse_read_cfg cfg)
+{
+	u8 *map = NULL;
+	u32 size = adapter->hw_cfg_info.eeprom_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	if (cfg == HALMAC_EFUSE_R_FW &&
+	    halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "cfg = %d\n",
+		 cfg);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+		pr_err("Dump efuse in suspend\n");
+
+	*proc_status = HALMAC_CMD_PROCESS_IDLE;
+	adapter->evnt.log_efuse_map = 1;
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank\n");
+		return status;
+	}
+
+	status = proc_dump_efuse_88xx(adapter, cfg);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("dump efuse\n");
+		return status;
+	}
+
+	if (adapter->efuse_map_valid == 1) {
+		*proc_status = HALMAC_CMD_PROCESS_DONE;
+
+		map = kzalloc(size, GFP_KERNEL);
+		if (!map)
+			return HALMAC_RET_MALLOC_FAIL;
+		memset(map, 0xFF, size);
+
+		if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+		    HALMAC_RET_SUCCESS) {
+			kfree(map);
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+		}
+
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,
+				*proc_status, map, size);
+		adapter->evnt.log_efuse_map = 0;
+
+		kfree(map);
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_logical_efuse_88xx() - read logical efuse map 1 byte
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : 1 byte efuse value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value)
+{
+	u8 *map = NULL;
+	u32 size = adapter->hw_cfg_info.eeprom_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	if (offset >= size) {
+		pr_err("Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank\n");
+		return status;
+	}
+
+	map = kzalloc(size, GFP_KERNEL);
+	if (!map)
+		return HALMAC_RET_MALLOC_FAIL;
+	memset(map, 0xFF, size);
+
+	status = read_log_efuse_map_88xx(adapter, map);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("read logical efuse\n");
+		kfree(map);
+		return status;
+	}
+
+	*value = *(map + offset);
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS) {
+		kfree(map);
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	kfree(map);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * write_log_efuse_88xx() - write "logical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	if (offset >= adapter->hw_cfg_info.eeprom_size) {
+		pr_err("Offset is too large\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank\n");
+		return status;
+	}
+
+	status = proc_write_log_efuse_88xx(adapter, offset, value);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("write logical efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pg_efuse_by_map_88xx() - pg logical efuse by map
+ * @adapter : the adapter of halmac
+ * @info : efuse map information
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info,
+		     enum halmac_efuse_read_cfg cfg)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {
+		pr_err("map size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if ((info->efuse_map_size & 0xF) > 0) {
+		pr_err("not multiple of 16\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (info->efuse_mask_size != info->efuse_map_size >> 4) {
+		pr_err("mask size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (!info->efuse_map) {
+		pr_err("map is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (!info->efuse_mask) {
+		pr_err("mask is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Wait event(efuse)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+		RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_WARNING,
+			 "Not idle(efuse)\n");
+		return HALMAC_RET_ERROR_STATE;
+	}
+
+	status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("switch efuse bank\n");
+		return status;
+	}
+
+	status = proc_pg_efuse_by_map_88xx(adapter, info, cfg);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("pg efuse\n");
+		return status;
+	}
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mask_log_efuse_88xx() - mask logical efuse
+ * @adapter : the adapter of halmac
+ * @info : efuse map information
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mask_log_efuse_88xx(struct halmac_adapter *adapter,
+		    struct halmac_pg_efuse_info *info)
+{
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s ===>\n",
+		 __func__);
+
+	if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {
+		pr_err("map size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if ((info->efuse_map_size & 0xF) > 0) {
+		pr_err("not multiple of 16\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (info->efuse_mask_size != info->efuse_map_size >> 4) {
+		pr_err("mask size error\n");
+		return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+	}
+
+	if (!info->efuse_map) {
+		pr_err("map is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (!info->efuse_mask) {
+		pr_err("mask is NULL\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	mask_eeprom_88xx(adapter, info);
+
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG, "%s <===\n",
+		 __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_cmd_construct_state
+efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+	return adapter->halmac_state.efuse_state.cmd_cnstr_state;
+}
+
+enum halmac_ret_status
+switch_efuse_bank_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank)
+{
+	u8 reg_value;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);
+
+	if (bank == (reg_value & (BIT(0) | BIT(1))))
+		return HALMAC_RET_SUCCESS;
+
+	reg_value &= ~(BIT(0) | BIT(1));
+	reg_value |= bank;
+	HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 1, reg_value);
+
+	reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);
+	if ((reg_value & (BIT(0) | BIT(1))) != bank)
+		return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_dump_efuse_88xx(struct halmac_adapter *adapter,
+		     enum halmac_efuse_read_cfg cfg)
+{
+	u32 h2c_init;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (cfg == HALMAC_EFUSE_R_AUTO) {
+		h2c_init = HALMAC_REG_R32(REG_H2C_PKT_READADDR);
+		if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE ||
+		    h2c_init == 0)
+			status = dump_efuse_drv_88xx(adapter);
+		else
+			status = dump_efuse_fw_88xx(adapter);
+	} else if (cfg == HALMAC_EFUSE_R_FW) {
+		status = dump_efuse_fw_88xx(adapter);
+	} else {
+		status = dump_efuse_drv_88xx(adapter);
+	}
+
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("dump efsue drv/fw\n");
+		return status;
+	}
+
+	return status;
+}
+
+enum halmac_ret_status
+cnv_efuse_state_88xx(struct halmac_adapter *adapter,
+		     enum halmac_cmd_construct_state dest_state)
+{
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&
+	    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY &&
+	    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_H2C_SENT)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (state->cmd_cnstr_state == dest_state)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (dest_state == HALMAC_CMD_CNSTR_BUSY) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_H2C_SENT)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	state->cmd_cnstr_state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		   u8 *map)
+{
+	u8 enable;
+	u32 value32;
+	u32 addr;
+	u32 tmp32;
+	u32 cnt;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	/* Read efuse no need 2.5V LDO */
+	enable = 0;
+	status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("dis ldo25\n");
+		return status;
+	}
+	value32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+
+	for (addr = offset; addr < offset + size; addr++) {
+		value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);
+		value32 |= ((addr & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR);
+		HALMAC_REG_W32(REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG));
+
+		cnt = 1000000;
+		do {
+			udelay(1);
+			tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+			cnt--;
+			if (cnt == 0) {
+				pr_err("read\n");
+				return HALMAC_RET_EFUSE_R_FAIL;
+			}
+		} while ((tmp32 & BIT_EF_FLAG) == 0);
+
+		*(map + addr - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	const u8 unlock_code = 0x69;
+	u8 value_read = 0;
+	u8 enable;
+	u32 value32;
+	u32 tmp32;
+	u32 cnt;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	mutex_lock(&adapter->efuse_mutex);
+	adapter->efuse_map_valid = 0;
+	mutex_unlock(&adapter->efuse_mutex);
+
+	HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code);
+
+	/* Enable 2.5V LDO */
+	enable = 1;
+	status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("en ldo25\n");
+		return status;
+	}
+
+	value32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+	value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);
+	value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) |
+			(value & BIT_MASK_EF_DATA);
+	HALMAC_REG_W32(REG_EFUSE_CTRL, value32 | BIT_EF_FLAG);
+
+	cnt = 1000000;
+	do {
+		udelay(1);
+		tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+		cnt--;
+		if (cnt == 0) {
+			pr_err("write!!\n");
+			return HALMAC_RET_EFUSE_W_FAIL;
+		}
+	} while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG));
+
+	HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00);
+
+	/* Disable 2.5V LDO */
+	enable = 0;
+	status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("dis ldo25\n");
+		return status;
+	}
+
+	if (adapter->efuse_auto_check_en == 1) {
+		if (read_hw_efuse_88xx(adapter, offset, 1, &value_read) !=
+		    HALMAC_RET_SUCCESS)
+			return HALMAC_RET_EFUSE_R_FAIL;
+		if (value_read != value) {
+			pr_err("efuse compare\n");
+			return HALMAC_RET_EFUSE_W_FAIL;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
+{
+	u8 i;
+	u8 value8;
+	u8 blk_idx;
+	u8 word_en;
+	u8 valid;
+	u8 hdr;
+	u8 hdr2 = 0;
+	u32 eeprom_idx;
+	u32 efuse_idx = 0;
+	struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;
+
+	memset(log_map, 0xFF, hw_info->eeprom_size);
+
+	do {
+		value8 = *(phy_map + efuse_idx);
+		hdr = value8;
+
+		if ((hdr & 0x1f) == 0x0f) {
+			efuse_idx++;
+			value8 = *(phy_map + efuse_idx);
+			hdr2 = value8;
+			if (hdr2 == 0xff)
+				break;
+			blk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07);
+			word_en = hdr2 & 0x0F;
+		} else {
+			blk_idx = (hdr & 0xF0) >> 4;
+			word_en = hdr & 0x0F;
+		}
+
+		if (hdr == 0xff)
+			break;
+
+		efuse_idx++;
+
+		if (efuse_idx >= hw_info->efuse_size - PROTECT_EFUSE_SIZE - 1)
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+		for (i = 0; i < 4; i++) {
+			valid = (u8)((~(word_en >> i)) & BIT(0));
+			if (valid == 1) {
+				eeprom_idx = (blk_idx << 3) + (i << 1);
+
+				if ((eeprom_idx + 1) > hw_info->eeprom_size) {
+					pr_err("efuse idx:0x%X\n",
+					       efuse_idx - 1);
+
+					pr_err("read hdr:0x%X\n", hdr);
+
+					pr_err("rad hdr2:0x%X\n", hdr2);
+
+					return HALMAC_RET_EEPROM_PARSING_FAIL;
+				}
+
+				value8 = *(phy_map + efuse_idx);
+				*(log_map + eeprom_idx) = value8;
+
+				eeprom_idx++;
+				efuse_idx++;
+
+				if (efuse_idx > hw_info->efuse_size -
+				    PROTECT_EFUSE_SIZE - 1)
+					return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+				value8 = *(phy_map + efuse_idx);
+				*(log_map + eeprom_idx) = value8;
+
+				efuse_idx++;
+
+				if (efuse_idx > hw_info->efuse_size -
+				    PROTECT_EFUSE_SIZE)
+					return HALMAC_RET_EEPROM_PARSING_FAIL;
+			}
+		}
+	} while (1);
+
+	adapter->efuse_end = efuse_idx;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
+{
+	u8 *local_map = NULL;
+	u32 efuse_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (adapter->efuse_map_valid == 0) {
+		efuse_size = adapter->hw_cfg_info.efuse_size;
+
+		local_map = kzalloc(efuse_size, GFP_KERNEL);
+		if (!local_map)
+			return HALMAC_RET_MALLOC_FAIL;
+
+		status = read_efuse_88xx(adapter, 0, efuse_size, local_map);
+		if (status != HALMAC_RET_SUCCESS) {
+			pr_err("read efuse\n");
+			kfree(local_map);
+			return status;
+		}
+
+		if (!adapter->efuse_map) {
+			adapter->efuse_map = kzalloc(efuse_size, GFP_KERNEL);
+			if (!adapter->efuse_map) {
+				kfree(local_map);
+				return HALMAC_RET_MALLOC_FAIL;
+			}
+		}
+
+		mutex_lock(&adapter->efuse_mutex);
+		memcpy(adapter->efuse_map, local_map, efuse_size);
+		adapter->efuse_map_valid = 1;
+		mutex_unlock(&adapter->efuse_mutex);
+
+		kfree(local_map);
+	}
+
+	if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+	    HALMAC_RET_SUCCESS)
+		return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+	return status;
+}
+
+static enum halmac_ret_status
+proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+			  struct halmac_pg_efuse_info *info,
+			  enum halmac_efuse_read_cfg cfg)
+{
+	u8 *updated_mask = NULL;
+	u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	updated_mask = kzalloc(mask_size, GFP_KERNEL);
+	if (!updated_mask)
+		return HALMAC_RET_MALLOC_FAIL;
+	memset(updated_mask, 0x00, mask_size);
+
+	status = update_eeprom_mask_88xx(adapter, info, updated_mask);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("update eeprom mask\n");
+		kfree(updated_mask);
+		return status;
+	}
+
+	status = check_efuse_enough_88xx(adapter, info, updated_mask);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("chk efuse enough\n");
+		kfree(updated_mask);
+		return status;
+	}
+
+	status = program_efuse_88xx(adapter, info, updated_mask);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("pg efuse\n");
+		kfree(updated_mask);
+		return status;
+	}
+
+	kfree(updated_mask);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dump_efuse_drv_88xx(struct halmac_adapter *adapter)
+{
+	u8 *map = NULL;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+
+	if (!adapter->efuse_map) {
+		adapter->efuse_map = kzalloc(efuse_size, GFP_KERNEL);
+		if (!adapter->efuse_map) {
+			reset_ofld_feature_88xx(adapter,
+						FEATURE_DUMP_PHY_EFUSE);
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	if (adapter->efuse_map_valid == 0) {
+		map = kzalloc(efuse_size, GFP_KERNEL);
+		if (!map)
+			return HALMAC_RET_MALLOC_FAIL;
+
+		if (read_hw_efuse_88xx(adapter, 0, efuse_size, map) !=
+		    HALMAC_RET_SUCCESS) {
+			kfree(map);
+			return HALMAC_RET_EFUSE_R_FAIL;
+		}
+
+		mutex_lock(&adapter->efuse_mutex);
+		memcpy(adapter->efuse_map, map, efuse_size);
+		adapter->efuse_map_valid = 1;
+		mutex_unlock(&adapter->efuse_mutex);
+
+		kfree(map);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dump_efuse_fw_88xx(struct halmac_adapter *adapter)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
+	hdr_info.content_size = 0;
+	hdr_info.ack = 1;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	adapter->halmac_state.efuse_state.seq_num = seq_num;
+
+	if (!adapter->efuse_map) {
+		adapter->efuse_map = kzalloc(efuse_size, GFP_KERNEL);
+		if (!adapter->efuse_map) {
+			reset_ofld_feature_88xx(adapter,
+						FEATURE_DUMP_PHY_EFUSE);
+			return HALMAC_RET_MALLOC_FAIL;
+		}
+	}
+
+	if (adapter->efuse_map_valid == 0) {
+		status = send_h2c_pkt_88xx(adapter, h2c_buf);
+		if (status != HALMAC_RET_SUCCESS) {
+			pr_err("send h2c pkt\n");
+			reset_ofld_feature_88xx(adapter,
+						FEATURE_DUMP_PHY_EFUSE);
+			return status;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	u8 byte1;
+	u8 byte2;
+	u8 blk;
+	u8 blk_idx;
+	u8 hdr;
+	u8 hdr2;
+	u8 *map = NULL;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	u32 end;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	map = kzalloc(eeprom_size, GFP_KERNEL);
+	if (!map)
+		return HALMAC_RET_MALLOC_FAIL;
+	memset(map, 0xFF, eeprom_size);
+
+	status = read_log_efuse_map_88xx(adapter, map);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("read logical efuse\n");
+		kfree(map);
+		return status;
+	}
+
+	if (*(map + offset) != value) {
+		end = adapter->efuse_end;
+		blk = (u8)(offset >> 3);
+		blk_idx = (u8)((offset & (8 - 1)) >> 1);
+
+		if (offset > 0x7f) {
+			hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
+			hdr2 = (u8)(((blk & 0x78) << 1) +
+						((0x1 << blk_idx) ^ 0x0F));
+		} else {
+			hdr = (u8)((blk << 4) + ((0x01 << blk_idx) ^ 0x0F));
+		}
+
+		if ((offset & 1) == 0) {
+			byte1 = value;
+			byte2 = *(map + offset + 1);
+		} else {
+			byte1 = *(map + offset - 1);
+			byte2 = value;
+		}
+
+		if (offset > 0x7f) {
+			if (adapter->hw_cfg_info.efuse_size <=
+			    4 + PROTECT_EFUSE_SIZE + end) {
+				kfree(map);
+				return HALMAC_RET_EFUSE_NOT_ENOUGH;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end, hdr);
+			if (status != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 1, hdr2);
+			if (status != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 2, byte1);
+			if (status != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 3, byte2);
+			if (status != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return status;
+			}
+		} else {
+			if (adapter->hw_cfg_info.efuse_size <=
+			    3 + PROTECT_EFUSE_SIZE + end) {
+				kfree(map);
+				return HALMAC_RET_EFUSE_NOT_ENOUGH;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end, hdr);
+			if (status != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 1, byte1);
+			if (status != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, end + 2, byte2);
+			if (status != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return status;
+			}
+		}
+	}
+
+	kfree(map);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map)
+{
+	if (!map) {
+		pr_err("malloc map\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (adapter->efuse_map_valid == 1) {
+		memcpy(map, adapter->efuse_map + offset, size);
+	} else {
+		if (read_hw_efuse_88xx(adapter, offset, size, map) !=
+		    HALMAC_RET_SUCCESS)
+			return HALMAC_RET_EFUSE_R_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_eeprom_mask_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+	u8 *map = NULL;
+	u8 clr_bit = 0;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	u8 *map_pg;
+	u8 *efuse_mask;
+	u16 i;
+	u16 j;
+	u16 map_offset;
+	u16 mask_offset;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	map = kzalloc(eeprom_size, GFP_KERNEL);
+	if (!map)
+		return HALMAC_RET_MALLOC_FAIL;
+	memset(map, 0xFF, eeprom_size);
+
+	memset(updated_mask, 0x00, info->efuse_mask_size);
+
+	status = read_log_efuse_map_88xx(adapter, map);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		kfree(map);
+		return status;
+	}
+
+	map_pg = info->efuse_map;
+	efuse_mask = info->efuse_mask;
+
+	for (i = 0; i < info->efuse_mask_size; i++)
+		*(updated_mask + i) = *(efuse_mask + i);
+
+	for (i = 0; i < info->efuse_map_size; i += 16) {
+		for (j = 0; j < 16; j += 2) {
+			map_offset = i + j;
+			mask_offset = i >> 4;
+			if (*(u16 *)(map_pg + map_offset) ==
+			    *(u16 *)(map + map_offset)) {
+				switch (j) {
+				case 0:
+					clr_bit = BIT(4);
+					break;
+				case 2:
+					clr_bit = BIT(5);
+					break;
+				case 4:
+					clr_bit = BIT(6);
+					break;
+				case 6:
+					clr_bit = BIT(7);
+					break;
+				case 8:
+					clr_bit = BIT(0);
+					break;
+				case 10:
+					clr_bit = BIT(1);
+					break;
+				case 12:
+					clr_bit = BIT(2);
+					break;
+				case 14:
+					clr_bit = BIT(3);
+					break;
+				default:
+					break;
+				}
+				*(updated_mask + mask_offset) &= ~clr_bit;
+			}
+		}
+	}
+
+	kfree(map);
+
+	return status;
+}
+
+static enum halmac_ret_status
+check_efuse_enough_88xx(struct halmac_adapter *adapter,
+			struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+	u8 pre_word_en;
+	u16 i;
+	u16 j;
+	u32 eeprom_offset;
+	u32 pg_num = 0;
+
+	for (i = 0; i < info->efuse_map_size; i = i + 8) {
+		eeprom_offset = i;
+
+		if ((eeprom_offset & 7) > 0)
+			pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+		else
+			pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+
+		if (pre_word_en > 0) {
+			if (eeprom_offset > 0x7f) {
+				pg_num += 2;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_en >> j) & 0x1) > 0)
+						pg_num += 2;
+				}
+			} else {
+				pg_num++;
+				for (j = 0; j < 4; j++) {
+					if (((pre_word_en >> j) & 0x1) > 0)
+						pg_num += 2;
+				}
+			}
+		}
+	}
+
+	if (adapter->hw_cfg_info.efuse_size <=
+	    (pg_num + PROTECT_EFUSE_SIZE + adapter->efuse_end))
+		return HALMAC_RET_EFUSE_NOT_ENOUGH;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+pg_extend_efuse_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info, u8 word_en,
+		     u8 pre_word_en, u32 eeprom_offset)
+{
+	u8 blk;
+	u8 hdr;
+	u8 hdr2;
+	u16 i;
+	u32 efuse_end;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	efuse_end = adapter->efuse_end;
+
+	blk = (u8)(eeprom_offset >> 3);
+	hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
+	hdr2 = (u8)(((blk & 0x78) << 1) + word_en);
+
+	status = write_hw_efuse_88xx(adapter, efuse_end, hdr);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("write efuse\n");
+		return status;
+	}
+
+	status = write_hw_efuse_88xx(adapter, efuse_end + 1, hdr2);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("write efuse(+1)\n");
+		return status;
+	}
+
+	efuse_end = efuse_end + 2;
+	for (i = 0; i < 4; i++) {
+		if (((pre_word_en >> i) & 0x1) > 0) {
+			status = write_hw_efuse_88xx(adapter, efuse_end,
+						     *(info->efuse_map +
+						     eeprom_offset +
+						     (i << 1)));
+			if (status != HALMAC_RET_SUCCESS) {
+				pr_err("write efuse(<<1)\n");
+				return status;
+			}
+
+			status = write_hw_efuse_88xx(adapter, efuse_end + 1,
+						     *(info->efuse_map +
+						     eeprom_offset + (i << 1)
+						     + 1));
+			if (status != HALMAC_RET_SUCCESS) {
+				pr_err("write efuse(<<1)+1\n");
+				return status;
+			}
+			efuse_end = efuse_end + 2;
+		}
+	}
+	adapter->efuse_end = efuse_end;
+	return status;
+}
+
+static enum halmac_ret_status
+proc_pg_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 word_en,
+		   u8 pre_word_en, u32 eeprom_offset)
+{
+	u8 blk;
+	u8 hdr;
+	u16 i;
+	u32 efuse_end;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	efuse_end = adapter->efuse_end;
+
+	blk = (u8)(eeprom_offset >> 3);
+	hdr = (u8)((blk << 4) + word_en);
+
+	status = write_hw_efuse_88xx(adapter, efuse_end, hdr);
+	if (status != HALMAC_RET_SUCCESS) {
+		pr_err("write efuse\n");
+		return status;
+	}
+	efuse_end = efuse_end + 1;
+	for (i = 0; i < 4; i++) {
+		if (((pre_word_en >> i) & 0x1) > 0) {
+			status = write_hw_efuse_88xx(adapter, efuse_end,
+						     *(info->efuse_map +
+						     eeprom_offset +
+						     (i << 1)));
+			if (status != HALMAC_RET_SUCCESS) {
+				pr_err("write efuse(<<1)\n");
+				return status;
+			}
+			status = write_hw_efuse_88xx(adapter, efuse_end + 1,
+						     *(info->efuse_map +
+						     eeprom_offset + (i << 1)
+						     + 1));
+			if (status != HALMAC_RET_SUCCESS) {
+				pr_err("write efuse(<<1)+1\n");
+				return status;
+			}
+			efuse_end = efuse_end + 2;
+		}
+	}
+	adapter->efuse_end = efuse_end;
+	return status;
+}
+
+static enum halmac_ret_status
+program_efuse_88xx(struct halmac_adapter *adapter,
+		   struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+	u8 pre_word_en;
+	u8 word_en;
+	u16 i;
+	u32 eeprom_offset;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	for (i = 0; i < info->efuse_map_size; i = i + 8) {
+		eeprom_offset = i;
+
+		if (((eeprom_offset >> 3) & 1) > 0) {
+			pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+			word_en = pre_word_en ^ 0x0F;
+		} else {
+			pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+			word_en = pre_word_en ^ 0x0F;
+		}
+
+		if (pre_word_en > 0) {
+			if (eeprom_offset > 0x7f) {
+				status = pg_extend_efuse_88xx(adapter, info,
+							      word_en,
+							      pre_word_en,
+							      eeprom_offset);
+				if (status != HALMAC_RET_SUCCESS) {
+					pr_err("extend efuse\n");
+					return status;
+				}
+			} else {
+				status = proc_pg_efuse_88xx(adapter, info,
+							    word_en,
+							    pre_word_en,
+							    eeprom_offset);
+				if (status != HALMAC_RET_SUCCESS) {
+					pr_err("extend efuse");
+					return status;
+				}
+			}
+		}
+	}
+
+	return status;
+}
+
+static void
+mask_eeprom_88xx(struct halmac_adapter *adapter,
+		 struct halmac_pg_efuse_info *info)
+{
+	u8 pre_word_en;
+	u8 *updated_mask;
+	u8 *efuse_map;
+	u16 i;
+	u16 j;
+	u32 offset;
+
+	updated_mask = info->efuse_mask;
+	efuse_map = info->efuse_map;
+
+	for (i = 0; i < info->efuse_map_size; i = i + 8) {
+		offset = i;
+
+		if (((offset >> 3) & 1) > 0)
+			pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+		else
+			pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+
+		for (j = 0; j < 4; j++) {
+			if (((pre_word_en >> j) & 0x1) == 0) {
+				*(efuse_map + offset + (j << 1)) = 0xFF;
+				*(efuse_map + offset + (j << 1) + 1) = 0xFF;
+			}
+		}
+	}
+}
+
+enum halmac_ret_status
+get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seg_id;
+	u8 seg_size;
+	u8 seq_num;
+	u8 fw_rc;
+	u8 *map = NULL;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+	enum halmac_cmd_process_status proc_status;
+
+	seq_num = (u8)EFUSE_DATA_GET_H2C_SEQ(buf);
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG,
+		 "Seq num : h2c->%d c2h->%d\n", state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		pr_err("Seq num mismatch : h2c->%d c2h->%d\n", state->seq_num,
+		       seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		pr_err("not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	seg_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(buf);
+	seg_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(buf);
+	if (seg_id == 0)
+		adapter->efuse_seg_size = seg_size;
+
+	map = kzalloc(eeprom_size, GFP_KERNEL);
+	if (!map)
+		return HALMAC_RET_MALLOC_FAIL;
+	memset(map, 0xFF, eeprom_size);
+
+	mutex_lock(&adapter->efuse_mutex);
+	memcpy(adapter->efuse_map + seg_id * adapter->efuse_seg_size,
+	       buf + C2H_DATA_OFFSET_88XX, seg_size);
+	mutex_unlock(&adapter->efuse_mutex);
+
+	if (EFUSE_DATA_GET_END_SEGMENT(buf) == 0) {
+		kfree(map);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = state->fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+
+		mutex_lock(&adapter->efuse_mutex);
+		adapter->efuse_map_valid = 1;
+		mutex_unlock(&adapter->efuse_mutex);
+
+		if (adapter->evnt.phy_efuse_map == 1) {
+			PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE,
+					proc_status, adapter->efuse_map,
+					adapter->hw_cfg_info.efuse_size);
+			adapter->evnt.phy_efuse_map = 0;
+		}
+
+		if (adapter->evnt.log_efuse_map == 1) {
+			if (eeprom_parser_88xx(adapter, adapter->efuse_map,
+					       map) != HALMAC_RET_SUCCESS) {
+				kfree(map);
+				return HALMAC_RET_EEPROM_PARSING_FAIL;
+			}
+			PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,
+					map, eeprom_size);
+			adapter->evnt.log_efuse_map = 0;
+		}
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+
+		if (adapter->evnt.phy_efuse_map == 1) {
+			PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, proc_status,
+					&state->fw_rc, 1);
+			adapter->evnt.phy_efuse_map = 0;
+		}
+
+		if (adapter->evnt.log_efuse_map == 1) {
+			PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,
+					&state->fw_rc, 1);
+			adapter->evnt.log_efuse_map = 0;
+		}
+	}
+
+	kfree(map);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size)
+{
+	u8 *map = NULL;
+	u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	*proc_status = state->proc_status;
+
+	if (!data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (!size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+		if (*size < efuse_size) {
+			*size = efuse_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = efuse_size;
+
+		map = kzalloc(efuse_size, GFP_KERNEL);
+		if (!map)
+			return HALMAC_RET_MALLOC_FAIL;
+		memset(map, 0xFF, efuse_size);
+		mutex_lock(&adapter->efuse_mutex);
+		memcpy(map, adapter->efuse_map,
+		       efuse_size - PROTECT_EFUSE_SIZE);
+		memcpy(map + efuse_size - PROTECT_EFUSE_SIZE +
+		       RSVD_CS_EFUSE_SIZE,
+		       adapter->efuse_map + efuse_size - PROTECT_EFUSE_SIZE +
+		       RSVD_CS_EFUSE_SIZE,
+		       PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
+		       RSVD_CS_EFUSE_SIZE);
+		mutex_unlock(&adapter->efuse_mutex);
+
+		memcpy(data, map, *size);
+
+		kfree(map);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size)
+{
+	u8 *map = NULL;
+	u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	*proc_status = state->proc_status;
+
+	if (!data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (!size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+		if (*size < eeprom_size) {
+			*size = eeprom_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = eeprom_size;
+
+		map = kzalloc(eeprom_size, GFP_KERNEL);
+		if (!map)
+			return HALMAC_RET_MALLOC_FAIL;
+		memset(map, 0xFF, eeprom_size);
+
+		if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+		    HALMAC_RET_SUCCESS) {
+			kfree(map);
+			return HALMAC_RET_EEPROM_PARSING_FAIL;
+		}
+
+		memcpy(data, map, *size);
+
+		kfree(map);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num = 0;
+	u8 fw_rc;
+	struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	RT_TRACE(adapter->drv_adapter, COMP_HALMAC, DBG_DMESG,
+		 "Seq num : h2c->%d c2h->%d\n", state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		pr_err("Seq num mismatch : h2c->%d c2h->%d\n", state->seq_num,
+		       seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		pr_err("not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u32
+get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter)
+{
+	return PROTECT_EFUSE_SIZE;
+}