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spi: bcm-qspi: Fix spi-nor chip select logic for BSPI

PATCH Superseded Kamal Dasu 1 participant 3 messages Apr 25, 2018

Subsystems (2)
SPI Broadcom SPI driver

v1 of 2 Superseded Latest is v2 →

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Kamal Dasu

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#0 lore raw

cover spi: bcm-qspi: Fix spi-nor chip select logic for BSPI

spi-nor master controller driver needs to verify the chip select bit in the cs register for any cs change during trasfers. Also CDRAM PCS field not used in BSPI mode, set defualt to ~1 indicating active low for zeroth bit. Also always enable/disable BSPI_MAST_N_BOOT_CTRL when using BSPI mode.

*** BLURB HERE ***

Kamal Dasu (2):
spi: bcm-qspi: Avoid setting MSPI_CDRAM_PCS for spi-nor master
spi: bcm-qspi: Always change BSPI_MAST_N_BOOT_CTRL state

 drivers/spi/spi-bcm-qspi.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH 1/2 spi: bcm-qspi: Avoid setting MSPI_CDRAM_PCS for spi-nor master

Added fix for probing of spi-nor device non-zero chip selects. Set MSPI_CDRAM_PCS (peripheral chip select) with spi master for MSPI controller and not for MSPI/BSPI spi-nor master controller. Ensure setting of cs bit in chip select register on chip select change.

Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)
drivers/spi/spi-bcm-qspi.c +16 -8
index 1596d35..2946989 100644
@@ -519,16 +519,19 @@ static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
 
 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
 {
-	u32 data = 0;
+	u32 rd = 0;
+	u32 wr = 0;
 
-	if (qspi->curr_cs == cs)
-		return;
 	if (qspi->base[CHIP_SELECT]) {
-		data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
-		data = (data & ~0xff) | (1 << cs);
-		bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
+		rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
+		wr = (rd & ~0xff) | (1 << cs);
+		if (rd == wr)
+			return;
+		bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
 		usleep_range(10, 20);
 	}
+
+	dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
 	qspi->curr_cs = cs;
 }
 

@@ -755,8 +758,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
 			dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
 		}
 		mspi_cdram = MSPI_CDRAM_CONT_BIT;
-		mspi_cdram |= (~(1 << spi->chip_select) &
-			       MSPI_CDRAM_PCS);
+
+		if (has_bspi(qspi))
+			mspi_cdram &= ~1;
+		else
+			mspi_cdram |= (~(1 << spi->chip_select) &
+				       MSPI_CDRAM_PCS);
+
 		mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
 				MSPI_CDRAM_BITSE_BIT);
Signature · 1 line
2.7.4
author
#2 lore raw

PATCH 2/2 spi: bcm-qspi: Always change BSPI_MAST_N_BOOT_CTRL state

In reply to Kamal Dasu

Always confirm the BSPI_MAST_N_BOOT_CTRL bit when enabling or disabling BSPI transfers.

Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/spi/spi-bcm-qspi.c +2 -2
index 2946989..6573152 100644
@@ -490,7 +490,7 @@ static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
 
 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
 {
-	if (!has_bspi(qspi) || (qspi->bspi_enabled))
+	if (!has_bspi(qspi))
 		return;
 
 	qspi->bspi_enabled = 1;

@@ -505,7 +505,7 @@ static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
 
 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
 {
-	if (!has_bspi(qspi) || (!qspi->bspi_enabled))
+	if (!has_bspi(qspi))
 		return;
 
 	qspi->bspi_enabled = 0;
Signature · 1 line
2.7.4