clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
Subsystems (3)
PATCH 1/1 clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
From: Amit Nischal <[email protected]>
The default behavior of the GDSC enable/disable sequence is to poll the status bits of either the actual GDSCR or the corresponding HW_CTRL registers.
On targets which have support for a CFG_GDSCR register, the status bits might not show the correct state of the GDSC, especially in the disable sequence, where the status bit will be cleared even before the core is completely power collapsed. On targets with this issue, poll the power on/off bits in the CFG_GDSCR register instead to correctly determine the GDSC state.
--- drivers/clk/qcom/gdsc.c | 42 ++++++++++++++++++++++++++---------------- drivers/clk/qcom/gdsc.h | 1 + 2 files changed, 27 insertions(+), 16 deletions(-)
drivers/clk/qcom/gdsc.c +26 -16
@@ -32,6 +32,11 @@#define SW_COLLAPSE_MASK BIT(0)#define GMEM_CLAMP_IO_MASK BIT(0) +/* CFG_GDSCR */ +#define GDSC_POWER_UP_COMPLETE BIT(16) +#define GDSC_POWER_DOWN_COMPLETE BIT(15) +#define CFG_GDSCR_OFFSET 0x4 +/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ #define EN_REST_WAIT_VAL (0x2 << 20)#define EN_FEW_WAIT_VAL (0x8 << 16)
@@ -44,15 +49,28 @@#define domain_to_gdsc (domain) container_of(domain, struct gdsc, pd) -static int gdsc_is_enabled (struct gdsc *sc,unsigned int reg) +static int gdsc_is_enabled (struct gdsc *sc,bool en) { +unsigned int reg;u32 val;int ret; +if (sc->flags &POLL_CFG_GDSCR ) + reg = sc->gdscr +CFG_GDSCR_OFFSET ; +else + reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr; + ret =regmap_read (sc->regmap, reg, &val);if (ret)return ret; +if (sc->flags &POLL_CFG_GDSCR ) { +if (en) +return !!(val &GDSC_POWER_UP_COMPLETE ); +else +return !(val &GDSC_POWER_DOWN_COMPLETE ); + } +return !!(val &PWR_ON_MASK ); }
@@ -63,17 +81,17 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)return regmap_update_bits (sc->regmap, sc->gdscr,HW_CONTROL_MASK , val); } -static int gdsc_poll_status (struct gdsc *sc,unsigned int reg,bool en) +static int gdsc_poll_status (struct gdsc *sc,bool en) {ktime_t start; start =ktime_get ();do { -if (gdsc_is_enabled (sc, reg) == en) +if (gdsc_is_enabled (sc, en) == en)return 0 ; }while (ktime_us_delta (ktime_get (), start) <TIMEOUT_US ); -if (gdsc_is_enabled (sc, reg) == en) +if (gdsc_is_enabled (sc, en) == en)return 0 ;return -ETIMEDOUT ;
@@ -83,7 +101,6 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) {int ret;u32 val = en ?0 :SW_COLLAPSE_MASK ; -unsigned int status_reg = sc->gdscr; ret =regmap_update_bits (sc->regmap, sc->gdscr,SW_COLLAPSE_MASK , val);if (ret)
@@ -100,8 +117,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)return 0 ; } -if (sc->gds_hw_ctrl) { - status_reg = sc->gds_hw_ctrl; +if (sc->gds_hw_ctrl)/* * The gds hw controller asserts/de-asserts the status bit soon * after it receives a power on/off request from a master.
@@ -113,9 +129,8 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)* and polling the status bit. */ udelay (1 ); - } -return gdsc_poll_status (sc, status_reg, en); +return gdsc_poll_status (sc, en); }static inline int gdsc_deassert_reset (struct gdsc *sc)
@@ -222,8 +237,6 @@ static int gdsc_disable(struct generic_pm_domain *domain)/* Turn off HW trigger mode if supported */ if (sc->flags &HW_CTRL ) { -unsigned int reg; - ret =gdsc_hwctrl (sc, false);if (ret <0 )return ret;
@@ -235,8 +248,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)*/ udelay (1 ); - reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr; - ret =gdsc_poll_status (sc, reg, true); + ret =gdsc_poll_status (sc, true);if (ret)return ret; }
@@ -258,7 +270,6 @@ static int gdsc_init(struct gdsc *sc) {u32 mask, val;int on, ret; -unsigned int reg;/* * Disable HW trigger: collapse/restore occur based on registers writes.
@@ -279,8 +290,7 @@ static int gdsc_init(struct gdsc *sc)return ret; } - reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr; - on =gdsc_is_enabled (sc, reg); + on =gdsc_is_enabled (sc, true);if (on <0 )return on;
drivers/clk/qcom/gdsc.h +1 -0
@@ -53,6 +53,7 @@ struct gdsc {#define VOTABLE BIT(0)#define CLAMP_IO BIT(1)#define HW_CTRL BIT(2) +#define POLL_CFG_GDSCR BIT(5)struct reset_controller_dev *rcdev;unsigned int *resets;unsigned int reset_count;
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Hi,
drivers/clk/qcom/gdsc.c line 61
Quoted 11 lines · Taniya Das
drivers/clk/qcom/gdsc.c +6
-1-static int gdsc_is_enabled (struct gdsc *sc,unsigned int reg) +static int gdsc_is_enabled (struct gdsc *sc,bool en) { +unsigned int reg;u32 val;int ret; +if (sc->flags &POLL_CFG_GDSCR ) + reg = sc->gdscr +CFG_GDSCR_OFFSET ; +else + reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
nit: why two spaces after the "?" in this new patch? Should be just one.
drivers/clk/qcom/gdsc.h struct gdsc { · line 56
Quoted 9 lines
drivers/clk/qcom/gdsc.h +1
-0@@ -53,6 +53,7 @@ struct gdsc {#define VOTABLE BIT(0)#define CLAMP_IO BIT(1)#define HW_CTRL BIT(2) +#define POLL_CFG_GDSCR BIT(5)
This doesn't apply cleanly to clk-next because clk-next already has the old patch #1 and patch #2 from your series. You should have applied your patch to clk-next before sending out.
Also a nit here is that you have two spaces before "BIT(5)" but all other entries in this list have a tab before them. You should be consistent and use a tab.
In general I'd tend to assume that Stephen could handle this small merge conflict and fixing the whitespace issues when applying, but if he tells you to spin then you certainly should. I'll also say that I'm nowhere near an expert on gdsc but it looks like Stephen's previous comments were addressed and the patch seems sane in general.
Stephen: feel free to add my Reviewed-by: if you wish when applying (or Taniya, if you end up spinning).
-Doug
Hello Doug,
Thanks for the comments, I have based my latest patch on top of the earlier patches (clk-qcom-sdm845 branch of clk-next).
Quoted 49 lines · Doug Anderson
Hi,
drivers/clk/qcom/gdsc.c line 61
Quoted 11 lines · Taniya Das
drivers/clk/qcom/gdsc.c +6
-1-static int gdsc_is_enabled (struct gdsc *sc,unsigned int reg) +static int gdsc_is_enabled (struct gdsc *sc,bool en) { +unsigned int reg;u32 val;int ret; +if (sc->flags &POLL_CFG_GDSCR ) + reg = sc->gdscr +CFG_GDSCR_OFFSET ; +else + reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;nit: why two spaces after the "?" in this new patch? Should be just one.
drivers/clk/qcom/gdsc.h struct gdsc { · line 56
Quoted 9 lines
drivers/clk/qcom/gdsc.h +1
-0@@ -53,6 +53,7 @@ struct gdsc {#define VOTABLE BIT(0)#define CLAMP_IO BIT(1)#define HW_CTRL BIT(2) +#define POLL_CFG_GDSCR BIT(5)This doesn't apply cleanly to clk-next because clk-next already has the old patch #1 and patch #2 from your series. You should have applied your patch to clk-next before sending out.
Also a nit here is that you have two spaces before "BIT(5)" but all other entries in this list have a tab before them. You should be consistent and use a tab.
In general I'd tend to assume that Stephen could handle this small merge conflict and fixing the whitespace issues when applying, but if he tells you to spin then you certainly should. I'll also say that I'm nowhere near an expert on gdsc but it looks like Stephen's previous comments were addressed and the patch seems sane in general.
Stephen: feel free to add my Reviewed-by: if you wish when applying (or Taniya, if you end up spinning).-Doug
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --