clk: qcom: Add support for RCG to register for DFS

drivers/clk/qcom/clk-rcg2.c +4 -0

index e63db10..7c35bca 100644
@@ -122,6 +131,10 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
        int ret;
        u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
 
+       /* In DFS mode skip updating the RCG CFG */
+       if (rcg->flags & DFS_ENABLE_RCG)
+               return 0;
+
        ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
                                 CFG_SRC_SEL_MASK, cfg);
        if (ret)

drivers/clk/qcom/clk-rcg2.c +11 -0

+       if (ret)
+               goto err;
+
+       mask = BIT(rcg->hid_width) - 1;
+       *pre_div = cfg & mask ? (cfg & mask) : 1;
+
+       *mode = cfg & CFG_MODE_MASK;
+       *mode >>= CFG_MODE_SHIFT;
+
+       cfg &= CFG_SRC_SEL_MASK;
+       cfg >>= CFG_SRC_SEL_SHIFT;

drivers/clk/qcom/clk-rcg2.c +40 -0

+{
+       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+       u32 val, mask;
+       int ret = 0;
+
+       if (!hw)
+               return -EINVAL;
+
+       *m = *n = 0;
+
+       if (mode) {
+               /* Calculate M & N values */
+               mask = BIT(rcg->mnd_width) - 1;
+               ret =  regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + m_offset,
+                                       &val);
+               if (ret) {
+                       pr_err("Failed to read M offset register\n");
+                       goto err;
+               }
+
+               val &= mask;
+               *m  = val;
+
+               ret =  regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + n_offset,
+                                       &val);
+               if (ret) {
+                       pr_err("Failed to read N offset register\n");
+                       goto err;
+               }
+
+               /* val ~(N-M) */
+               val = ~val;
+               val &= mask;
+               val += *m;
+               *n = val;
+       }
+err:
+       return ret;
+}
+

drivers/clk/qcom/clk-rcg2.c +4 -0

+
+       /* Check for DFS_EN */
+       ret = regmap_read(clk->clkr.regmap, clk->cmd_rcgr + SE_CMD_DFSR_OFFSET,
+                                               &val);

drivers/clk/qcom/clk-rcg2.c +13 -0

+       if (!dfs_freq_tbl)
+               return -ENOMEM;
+
+       /* Populate the Perf Level */
+       for (i = 0; i < MAX_PERF_LEVEL; i++) {
+               /* Get parent index and mode */
+               index = clk_parent_index_pre_div_and_mode(&clk->clkr.hw,
+                                                       SE_PERF_DFSR(i), &mode,
+                                                       &pre_div);
+               if (index < 0) {
+                       pr_err("Failed to get parent index & mode %d\n", index);
+                       return index;
+               }

drivers/clk/qcom/clk-rcg2.c +14 -0

+
+               ret = calculate_m_and_n(&clk->clkr.hw, SE_PERF_M_DFSR(i),
+                                       SE_PERF_N_DFSR(i), mode, &m, &n);
+               if (ret)
+                       goto err;
+
+               dfs_freq_tbl[i].m = m;
+               dfs_freq_tbl[i].n = n;
+
+               /* calculate the final frequency */
+               calc_freq = calc_rate(prate, dfs_freq_tbl[i].m,
+                                               dfs_freq_tbl[i].n, mode,
+                                               dfs_freq_tbl[i].pre_div);
+

drivers/clk/qcom/clk-rcg2.c +4 -0

+       clk->freq_tbl = dfs_freq_tbl;
+err:
+       return ret;
+}

drivers/clk/qcom/common.c +0 -0

index b8064a3..b27699b 100644

drivers/clk/qcom/common.c +3 -0

@@ -288,4 +288,25 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
 }
 EXPORT_SYMBOL_GPL(qcom_cc_probe);
 
+int qcom_cc_register_rcg_dfs(struct platform_device *pdev,
+                        const struct qcom_cc_dfs_desc *desc)
+{

drivers/clk/qcom/common.c +8 -0

+                       break;
+               }
+       }
+
+       return ret;
+}
+EXPORT_SYMBOL(qcom_cc_register_rcg_dfs);
+
 MODULE_LICENSE("GPL v2");

drivers/clk/qcom/common.h +1 -1

index 00196ee..6627aec 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014, 2018, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and