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clk: meson: meson8b: enable CLK_MESON_MPLL_ROUND_CLOSEST for all MPLLs

PATCH New Martin Blumenstingl 2 participants 3 messages Apr 28, 2018 – May 15, 2018

Subsystems (3)
Arm/Amlogic Meson SoC support Common clk Arm/Amlogic Meson SoC clock framework
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Martin Blumenstingl

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#0 lore raw

PATCH 1/1 clk: meson: meson8b: enable CLK_MESON_MPLL_ROUND_CLOSEST for all MPLLs

Until recently the clk-mpll implementation always used DIV_ROUND_UP_ULL(). However, since commit 1b0e500dc606e9 ("clk: meson:
mpll: add round closest support") the default was changed to round down the SDM divisor.
This broke RGMII Ethernet on Meson8b (which uses MPLL2 as RGMII TX clock). With the old implementation the MPLL2 output was 249999701Hz, but with "round closest" disabled the output is 212500000Hz.

Enabling CLK_MESON_MPLL_ROUND_CLOSEST for all MPLL2 clocks on Meson8b fixes this because we now get the same 249999701Hz from MPLL2 as before.

Fixes 1b0e500dc606e9 ("clk: meson: mpll: add round closest support")
Signed-off-by Martin Blumenstingl <[email protected]>
---
 drivers/clk/meson/meson8b.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/meson/meson8b.c +3 -0
index d0524ec71aad..2639a892a5d4 100644
@@ -382,6 +382,7 @@ static struct clk_regmap meson8b_mpll0_div = {
 			.width   = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0_div",

@@ -423,6 +424,7 @@ static struct clk_regmap meson8b_mpll1_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1_div",

@@ -464,6 +466,7 @@ static struct clk_regmap meson8b_mpll2_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2_div",
Signature · 1 line
2.17.0
maintainer
#1 lore raw

PATCH 1/1 clk: meson: meson8b: enable CLK_MESON_MPLL_ROUND_CLOSEST for all MPLLs

Quoted 11 lines · Martin Blumenstingl

Until recently the clk-mpll implementation always used DIV_ROUND_UP_ULL(). However, since commit 1b0e500dc606e9 ("clk: meson:
mpll: add round closest support") the default was changed to round down the SDM divisor.
This broke RGMII Ethernet on Meson8b (which uses MPLL2 as RGMII TX clock). With the old implementation the MPLL2 output was 249999701Hz, but with "round closest" disabled the output is 212500000Hz.

Enabling CLK_MESON_MPLL_ROUND_CLOSEST for all MPLL2 clocks on Meson8b fixes this because we now get the same 249999701Hz from MPLL2 as before.

It should either be rounding up or down, not down or 'more down' I guess I need to revisit this series. In the mean time, I'll drop it. Thanks for reporting the issue

Quoted 35 lines
Fixes 1b0e500dc606e9 ("clk: meson: mpll: add round closest support")
Signed-off-by Martin Blumenstingl <[email protected]>
---
 drivers/clk/meson/meson8b.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/meson/meson8b.c +3 -0
index d0524ec71aad..2639a892a5d4 100644
@@ -382,6 +382,7 @@ static struct clk_regmap meson8b_mpll0_div = {
 			.width   = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0_div",

@@ -423,6 +424,7 @@ static struct clk_regmap meson8b_mpll1_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1_div",

@@ -464,6 +466,7 @@ static struct clk_regmap meson8b_mpll2_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2_div",
maintainer
#2 lore raw

PATCH 1/1 clk: meson: meson8b: enable CLK_MESON_MPLL_ROUND_CLOSEST for all MPLLs

Quoted 9 lines · Jerome Brunet
Quoted 8 lines · Martin Blumenstingl

Until recently the clk-mpll implementation always used DIV_ROUND_UP_ULL(). However, since commit 1b0e500dc606e9 ("clk: meson:
mpll: add round closest support") the default was changed to round down the SDM divisor.
This broke RGMII Ethernet on Meson8b (which uses MPLL2 as RGMII TX clock). With the old implementation the MPLL2 output was 249999701Hz, but with "round closest" disabled the output is 212500000Hz.

Quoted 6 lines
Quoted 2 lines

Enabling CLK_MESON_MPLL_ROUND_CLOSEST for all MPLL2 clocks on Meson8b fixes this because we now get the same 249999701Hz from MPLL2 as before.

It should either be rounding up or down, not down or 'more down' I guess I need to revisit this series. In the mean time, I'll drop it. Thanks for reporting the issue

Hi Martin,

I think I found the problem in the mpll round closest code.
It does not seem to be a 32bit overflow, as we had before. Apparently, I got confused with rounding up and down stuff :(

I'll post a v2 soon. I'll wait for your feedback before applying it this time

Thanks again for reporting the issue.

Cheers
Jerome

Quoted 38 lines
Quoted 36 lines
Fixes 1b0e500dc606e9 ("clk: meson: mpll: add round closest support")
Signed-off-by Martin Blumenstingl <[email protected]>
---
 drivers/clk/meson/meson8b.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/meson/meson8b.c +3 -0
index d0524ec71aad..2639a892a5d4 100644
@@ -382,6 +382,7 @@ static struct clk_regmap meson8b_mpll0_div = {
 			.width   = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0_div",

@@ -423,6 +424,7 @@ static struct clk_regmap meson8b_mpll1_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1_div",

@@ -464,6 +466,7 @@ static struct clk_regmap meson8b_mpll2_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2_div",