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clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL

PATCH New Martin Blumenstingl 2 participants 2 messages May 20, 2018 – May 21, 2018

Subsystems (3)
Arm/Amlogic Meson SoC support Common clk Arm/Amlogic Meson SoC clock framework
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Martin Blumenstingl

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PATCH v2 1/1 clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL

Until commit 05f814402d6174 ("clk: meson: add fdiv clock gates") we relied on the bootloader to enable the fclk_div clock gates. It turns out that our clock tree is incomplete at least on Meson8b (tested with an Odroid-C1, which uses an RGMII PHY) because after the mentioned commit Ethernet is not working anymore (no RX/TX activity can be seen). At the same time Ethernet was still working on Meson8m2 with a RMII PHY.

Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops working on Odroid-C1. Unfortunately it's currently not clear what the Ethernet controller IP block uses the fclk_div2 clock for. Mark the clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by most bootloaders by default, which is why we didn't notice it before).

Fixes 05f814402d6174 ("clk: meson: add fdiv clock gates")
Signed-off-by Martin Blumenstingl <[email protected]>
Tested-by Kevin Hilman <[email protected]>

---
changes since v1 at [0]:
- only fclk_div2 has to be kept running (so the commit message and the patch itself are updated)
- added a FIXME comment to the code

[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-May/007272.html

 drivers/clk/meson/meson8b.c | 7 +++++++
 1 file changed, 7 insertions(+)
drivers/clk/meson/meson8b.c +7 -0
index 40068c1b5e80..415ba1d8a904 100644
@@ -246,6 +246,13 @@ static struct clk_regmap meson8b_fclk_div2 = {
 		.ops = &clk_regmap_gate_ops,
 		.parent_names = (const char *[]){ "fclk_div2_div" },
 		.num_parents = 1,
+		/*
+		 * FIXME: Ethernet with a RGMII PHYs is not working if
+		 * fclk_div2 is disabled. it is currently unclear why this
+		 * is. keep it enabled until the Ethernet driver knows how
+		 * to manage this clock.
+		 */
+		.flags = CLK_IS_CRITICAL,
 	},
 };
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#1 lore raw

PATCH v2 1/1 clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL

Quoted 22 lines · Martin Blumenstingl

Until commit 05f814402d6174 ("clk: meson: add fdiv clock gates") we relied on the bootloader to enable the fclk_div clock gates. It turns out that our clock tree is incomplete at least on Meson8b (tested with an Odroid-C1, which uses an RGMII PHY) because after the mentioned commit Ethernet is not working anymore (no RX/TX activity can be seen). At the same time Ethernet was still working on Meson8m2 with a RMII PHY.

Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops working on Odroid-C1. Unfortunately it's currently not clear what the Ethernet controller IP block uses the fclk_div2 clock for. Mark the clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by most bootloaders by default, which is why we didn't notice it before).

Fixes 05f814402d6174 ("clk: meson: add fdiv clock gates")
Signed-off-by Martin Blumenstingl <[email protected]>
Tested-by Kevin Hilman <[email protected]>

---
changes since v1 at [0]:
- only fclk_div2 has to be kept running (so the commit message and the patch itself are updated)
- added a FIXME comment to the code

Quoted 4 lines

[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-May/007272.html

 drivers/clk/meson/meson8b.c | 7 +++++++
 1 file changed, 7 insertions(+)

Added :
Cc: stable at vger.kernel.org

and applied. Thx Martin