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ARM: dts: Fix SPI node for Arria10

PATCH In review [email protected] 2 participants 4 messages May 29, 2018 – Jun 22, 2018

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#0 lore raw

PATCH 1/2 ARM: dts: Fix SPI node for Arria10

From: Thor Thayer <[email protected]>

Remove the unused bus-num node and change num-chipselect to num-cs to match SPI bindings.

Fixes f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip")
Signed-off-by Thor Thayer <[email protected]>
Cc [email protected]
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
arch/arm/boot/dts/socfpga_arria10.dtsi +1 -2
index bead79e4b2aa..9138f834bad4 100644
@@ -593,8 +593,7 @@
 			#size-cells = <0>;
 			reg = <0xffda5000 0x100>;
 			interrupts = <0 102 4>;
-			num-chipselect = <4>;
-			bus-num = <0>;
+			num-cs = <4>;
 			/*32bit_access;*/
 			tx-dma-channel = <&pdma 16>;
 			rx-dma-channel = <&pdma 17>;
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH 2/2 ARM: dts: Add SPI0 node for Arria10

From: Thor Thayer <[email protected]>

Add the SPI0 node for Arria10.

Signed-off-by Thor Thayer <[email protected]>
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm/boot/dts/socfpga_arria10.dtsi +12 -0
index 9138f834bad4..ee9a5fc616a8 100644
@@ -587,6 +587,18 @@
 			status = "disabled";
 		};
 
+		spi0: spi@ffda4000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xffda4000 0x100>;
+			interrupts = <0 101 4>;
+			num-cs = <4>;
+			/*32bit_access;*/
+			clocks = <&spi_m_clk>;
+			status = "disabled";
+		};
+
 		spi1: spi@ffda5000 {
 			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
Signature · 1 line
2.7.4
author
#2 lore raw
In reply to [email protected]

Hi Dinh,

Quoted 18 lines · On 05/29/2018 01:08 PM, [email protected] wrote:

From: Thor Thayer <[email protected]>

Remove the unused bus-num node and change num-chipselect to num-cs to match SPI bindings.

Fixes f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip")
Signed-off-by Thor Thayer <[email protected]>
Cc [email protected]
---
  arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)
arch/arm/boot/dts/socfpga_arria10.dtsi +0 -0
index bead79e4b2aa..9138f834bad4 100644

arch/arm/boot/dts/socfpga_arria10.dtsi line 599

Quoted 9 lines
arch/arm/boot/dts/socfpga_arria10.dtsi +1 -2
@@ -593,8 +593,7 @@
  			#size-cells = <0>;
  			reg = <0xffda5000 0x100>;
  			interrupts = <0 102 4>;
-			num-chipselect = <4>;
-			bus-num = <0>;
+			num-cs = <4>;
  			/*32bit_access;*/
  			tx-dma-channel = <&pdma 16>;
  			rx-dma-channel = <&pdma 17>;

Any update on this patch?

#3 lore raw
Quoted 25 lines · Thor Thayer

Hi Dinh,

Quoted 22 lines · On 05/29/2018 01:08 PM, [email protected] wrote:

From: Thor Thayer <[email protected]>

Remove the unused bus-num node and change num-chipselect to num-cs to match SPI bindings.

Fixes f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10

SR chip")

Signed-off-by Thor Thayer <[email protected]>
Cc [email protected]

---
  arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--

  1 file changed, 1 insertion(+), 2 deletions(-)
arch/arm/boot/dts/socfpga_arria10.dtsi +0 -0
index bead79e4b2aa..9138f834bad4 100644
@@ -593,8 +593,7 @@
               #size-cells = <0>;
               reg = <0xffda5000 0x100>;
               interrupts = <0 102 4>;
Quoted 8 lines

arch/arm/boot/dts/socfpga_arria10.dtsi line 599

Quoted 7 lines
arch/arm/boot/dts/socfpga_arria10.dtsi +1 -2
-            num-chipselect = <4>;
-            bus-num = <0>;
+            num-cs = <4>;
               /*32bit_access;*/
               tx-dma-channel = <&pdma 16>;
               rx-dma-channel = <&pdma 17>;

Any update on this patch?

I've applied both patches.

Thanks,
Dinh