ARM: socfpga: Assure correct ACTLR configuration

PATCH New Marek Vasut 3 participants 8 messages May 29, 2018 – Jul 3, 2018

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Arm (32-bit) Arm sub-architectures Arm/socfpga architecture

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Marek Vasut

author

2018-05-29 16:39 UTC #0 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared.

Signed-off-by Marek Vasut <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

---
NOTE: This gem was well hidden in the Altera U-Boot fork and is really needed.
What is not entirely clear to me is WHY ? So why is this needed ?

 arch/arm/mach-socfpga/board.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

arch/arm/mach-socfpga/board.c +12 -1

index 189e12a668..ffdabc04fc 100644
@@ -18,7 +18,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void s_init(void) {}
+void s_init(void) {
+	/*
+	 * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled.
+	 * This is optional on CycloneV / ArriaV.
+	 * This is mandatory on Arria10, otherwise Linux refuses to boot.
+	 */
+	asm volatile(
+		"mcr p15, 0, %0, c1, c0, 1\n"
+		"isb\n"
+		"dsb\n"
+	::"r"(0x44));
+}
 
 /*
  * Miscellaneous platform dependent initialisations

Signature · 1 line

2.17.0

See

2018-05-31 09:52 UTC #1 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Quoted 4 lines · Marek Vasut

Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared.

Quoted 8 lines

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
NOTE: This gem was well hidden in the Altera U-Boot fork and is really needed.
What is not entirely clear to me is WHY ? So why is this needed ?

I vaguely recall it's related to HW constrain. And check back the downstream U-Boot, actually we need to set the bit instead clearing it. https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2
014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl310.c

Thanks
Chin Liang

[...]

Marek Vasut

author

2018-05-31 10:00 UTC #2 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Quoted 14 lines · Chin Liang

Quoted 4 lines · Marek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared.
Quoted 8 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
NOTE: This gem was well hidden in the Altera U-Boot fork and is really needed.
What is not entirely clear to me is WHY ? So why is this needed ?

Quoted 4 lines

I vaguely recall it's related to HW constrain. And check back the downstream U-Boot, actually we need to set the bit instead clearing it. https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2
014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl310.c

You are clearing it here:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/lowlevel_init.S#L35

The PL310 configuration is a different register. What HW constraint ? I'd really like to understand this problem.

Signature · 2 lines

Best regards,
Marek Vasut

Marek Vasut

author

2018-06-06 18:47 UTC #3 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Quoted 20 lines · Marek Vasut

Quoted 14 lines · Chin Liang
Quoted 4 lines · Marek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared.
Quoted 8 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
NOTE: This gem was well hidden in the Altera U-Boot fork and is really needed.
What is not entirely clear to me is WHY ? So why is this needed ?
Quoted 4 lines
I vaguely recall it's related to HW constrain. And check back the downstream U-Boot, actually we need to set the bit instead clearing it. https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2
014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl310.c

Quoted 5 lines

You are clearing it here:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/lowlevel_init.S#L35
The PL310 configuration is a different register. What HW constraint ? I'd really like to understand this problem.

Bump ? I had a report the register even has to be set to 0 , otherwise there are ethernet problems. What is going on with this register ?

Signature · 2 lines

Best regards,
Marek Vasut

Marek Vasut

author

2018-06-23 03:55 UTC #4 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Quoted 21 lines · Marek Vasut

Quoted 20 lines · Marek Vasut
Quoted 18 lines · Chin Liang
Quoted 4 lines · Marek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared.
Quoted 8 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
NOTE: This gem was well hidden in the Altera U-Boot fork and is really needed.
What is not entirely clear to me is WHY ? So why is this needed ?
I vaguely recall it's related to HW constrain. And check back the downstream U-Boot, actually we need to set the bit instead clearing it. https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2
014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl310.c

Quoted 8 lines

Quoted 5 lines
You are clearing it here:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/lowlevel_init.S#L35
The PL310 configuration is a different register. What HW constraint ? I'd really like to understand this problem.
Bump ? I had a report the register even has to be set to 0 , otherwise there are ethernet problems. What is going on with this register ?

Bump again ?

Signature · 2 lines

Best regards,
Marek Vasut

Marek Vasut

2018-06-23 04:23 UTC #5 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Quoted 25 lines · Marek Vasut

Quoted 24 lines · Marek Vasut
Quoted 23 lines · Marek Vasut
Quoted 14 lines · Chin Liang
Quoted 4 lines · Marek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise the Linux kernel refuses to boot. In particular, the "Write Full Line of Zeroes" bit must be cleared.
Quoted 8 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
NOTE: This gem was well hidden in the Altera U-Boot fork and is really needed.
What is not entirely clear to me is WHY ? So why is this needed ?
Quoted 4 lines
I vaguely recall it's related to HW constrain. And check back the downstream U-Boot, actually we need to set the bit instead clearing it. https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2
014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl310.c
You are clearing it here:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/lowlevel_init.S#L35

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
The PL310 configuration is a different register. What HW constraint ? I'd really like to understand this problem.
Bump ? I had a report the register even has to be set to 0 , otherwise there are ethernet problems. What is going on with this register ?
Bump again ?

Expanding the CC list. I am tempted to stop accepting any socfpga patches until this is resolved.

Signature · 2 lines

Best regards,
Marek Vasut

See

2018-07-03 15:10 UTC #6 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Quoted 42 lines · Marek Vasut

Quoted 41 lines · Marek Vasut
Quoted 39 lines · Marek Vasut
Quoted 37 lines · Marek Vasut
Quoted 19 lines · Chin Liang
Quoted 10 lines · Marek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise
the Linux kernel refuses to boot. In particular, the "Write Full Line
of Zeroes" bit must be cleared.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Quoted 7 lines
---
NOTE: This gem was well hidden in the Altera U-Boot fork and is
really needed.
What is not entirely clear to me is WHY ? So why is this needed
?
Quoted 8 lines
I vaguely recall it's related to HW constrain. And check back the
downstream U-Boot, actually we need to set the bit instead clearing
it. https://github.com/altera-opensource/u-boot-socfpga/blob/
socfpga_v2 014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl3 10.c
You are clearing it here:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpg
a_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/l owlevel_init.S#L35
The PL310 configuration is a different register. What HW constraint ?
I'd really like to understand this problem.

Quoted 9 lines

Quoted 6 lines
Quoted 4 lines
Bump ? I had a report the register even has to be set to 0 , otherwise
there are ethernet problems. What is going on with this register ?
Bump again ?
Expanding the CC list. I am tempted to stop accepting any socfpga patches until this is resolved.

Just realize this is not addressed as Ley Foon talked to me

We checked with HW team that the full line of zeroes is a special setup of signals between A9 and L2 cache controller. As they recalled that this signal is not 100% AXI compliance, it may hang the system if L2 cache is disabled while full line of zeroes is set.

In A10, one thing new is we enabled L2 cache in BootROM and this bit is set. When entering the U-Boot, we are ensuring all cache are disabled. At this point, we need to ensure full line of zeroes bit is cleared. Only when U-Boot renable the cache including L2, this bit is set again.

Hope this explains.

Thanks
Chin Liang

Marek Vasut

2018-07-03 16:52 UTC #7 lore raw

PATCH 1/1 ARM: socfpga: Assure correct ACTLR configuration

Quoted 47 lines · Chin Liang

Quoted 46 lines · Marek Vasut
Quoted 45 lines · Marek Vasut
Quoted 43 lines · Marek Vasut
Quoted 29 lines · Marek Vasut
Quoted 19 lines · Chin Liang
Quoted 10 lines · Marek Vasut
Make sure the ARM ACTLR register has correct configuration, otherwise
the Linux kernel refuses to boot. In particular, the "Write Full Line
of Zeroes" bit must be cleared.
Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Quoted 7 lines
---
NOTE: This gem was well hidden in the Altera U-Boot fork and is
really needed.
What is not entirely clear to me is WHY ? So why is this needed
?
Quoted 8 lines
I vaguely recall it's related to HW constrain. And check back the
downstream U-Boot, actually we need to set the bit instead clearing
it. https://github.com/altera-opensource/u-boot-socfpga/blob/
socfpga_v2 014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl3 10.c
Quoted 8 lines
You are clearing it here:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpg
a_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/l owlevel_init.S#L35
The PL310 configuration is a different register. What HW constraint ?
I'd really like to understand this problem.
Bump ? I had a report the register even has to be set to 0 , otherwise
there are ethernet problems. What is going on with this register ?

Quoted 7 lines

Quoted 5 lines
Quoted 2 lines
Bump again ?
Expanding the CC list. I am tempted to stop accepting any socfpga patches until this is resolved.
Just realize this is not addressed as Ley Foon talked to me

I am real grateful for that.

Quoted 11 lines

We checked with HW team that the full line of zeroes is a special setup of signals between A9 and L2 cache controller. As they recalled that this signal is not 100% AXI compliance, it may hang the system if L2 cache is disabled while full line of zeroes is set.
In A10, one thing new is we enabled L2 cache in BootROM and this bit is set. When entering the U-Boot, we are ensuring all cache are disabled. At this point, we need to ensure full line of zeroes bit is cleared. Only when U-Boot renable the cache including L2, this bit is set again.
Hope this explains.

I'll have to give it some thought, but I think so.

Is there an errata or some piece of documentation I can refer to about this behavior ? I'd like to add link to the commit message.

Thanks, really appreciated!

Signature · 2 lines

Best regards,
Marek Vasut