Add suppport for sn65dsi86 bridge chip and Innolux 2k edp panel
Subsystems (7)
v8 cover Add suppport for sn65dsi86 bridge chip and Innolux 2k edp panel
Changes in current patchset:
- Moved dsi register/attach function to bridge probe.
- Renames and added more description to lane-mapping dt property.
- Removed some unnecessary headers/macros from driver.
Sandeep Panda (4):
drm/bridge: add support for sn65dsi86 bridge driver
dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings drm/panel: add Innolux TV123WAM panel driver support
dt-bindings: drm/panel: Document Innolux TV123WAM panel bindings
.../bindings/display/bridge/ti,sn65dsi86.txt | 109 ++++ .../bindings/display/panel/innolux,tv123wam.txt | 20 + drivers/gpu/drm/bridge/Kconfig | 9 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 666 +++++++++++++++++++++ drivers/gpu/drm/panel/panel-simple.c | 27 + 6 files changed, 832 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt create mode 100644 Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ Freedreno mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/freedreno
A message that is not in the archive (sent off-list or not yet received): 1528177218-1051-1-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
v8 cover Add suppport for sn65dsi86 bridge chip and Innolux 2k edp panel
Changes in current patchset:
- Moved dsi register/attach function to bridge probe.
- Renames and added more description to lane-mapping dt property.
- Removed some unnecessary headers/macros from driver.
Sandeep Panda (4):
drm/bridge: add support for sn65dsi86 bridge driver
dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings drm/panel: add Innolux TV123WAM panel driver support
dt-bindings: drm/panel: Document Innolux TV123WAM panel bindings
.../bindings/display/bridge/ti,sn65dsi86.txt | 109 ++++ .../bindings/display/panel/innolux,tv123wam.txt | 20 + drivers/gpu/drm/bridge/Kconfig | 9 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 666 +++++++++++++++++++++ drivers/gpu/drm/panel/panel-simple.c | 27 + 6 files changed, 832 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt create mode 100644 Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
Signature · 7 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ Freedreno mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/freedreno
PATCH v8 1/4 drm/bridge: add support for sn65dsi86 bridge driver
In reply to a message not in the archiveAdd support for TI's sn65dsi86 dsi2edp bridge chip. The chip converts DSI transmitted signal to eDP signal, which is fed to the connected eDP panel.
This chip can be controlled via either i2c interface or dsi interface. Currently in driver all the control registers are being accessed through i2c interface only. Also as of now HPD support has not been added to bridge chip driver.
Changes in v1:
- Split the dt-bindings and the driver support into separate patches (Andrzej Hajda).
- Use of gpiod APIs to parse and configure gpios instead of obsolete ones (Andrzej Hajda).
- Use macros to define the register offsets (Andrzej Hajda).
Changes in v2:
- Separate out edp panel specific HW resource handling from bridge driver and create a separate edp panel drivers to handle panel specific mode information and HW resources (Sean Paul).
- Replace pr_* APIs to DRM_* APIs to log error or debug information (Sean Paul).
- Remove some of the unnecessary structure/variable from driver (Sean Paul).
- Rename the function and structure prefix "sn65dsi86" to "ti_sn_bridge" (Sean Paul / Rob Herring).
- Remove most of the hard-coding and modified the bridge init sequence based on current mode (Sean Paul).
- Remove the existing function to retrieve the EDID data and implemented this as an i2c_adapter and use drm_get_edid() (Sean Paul).
- Remove the dummy irq handler implementation, will add back the proper irq handling later (Sean Paul).
- Capture the required enable gpios in a single array based on dt entry instead of having individual descriptor for each gpio (Sean Paul).
Changes in v3:
- Remove usage of irq_gpio and replace it as "interrupts" property (Rob Herring).
- Remove the unnecessary header file inclusions (Sean Paul).
- Rearrange the header files in alphabetical order (Sean Paul).
- Use regmap interface to perform i2c transactions.
- Update Copyright/License field and address other review comments (Jordan Crouse).
Changes in v4:
- Update License/Copyright (Sean Paul).
- Add Kconfig and Makefile changes (Sean Paul).
- Drop i2c gpio handling from this bridge driver, since i2c sda/scl gpios will be handled by i2c master.
- Update required supplies names.
- Remove unnecessary goto statements (Sean Paul).
- Add mutex lock to power_ctrl API to avoid race conditions (Sean Paul).
- Add support to parse reference clk frequency from dt(optional).
- Update the bridge chip enable/disable sequence.
Changes in v5:
- Fixed Kbuild test service reported warnings.
Changes in v6:
- Use PM runtime based ref-counting instead of local ref_count mechanism (Stephen Boyd).
- Clean up some debug logs and indentations (Sean Paul).
- Simplify dp rate calculation (Sean Paul).
- Add support to configure refclk based on input REFCLK pin or DACP/N pin (Stephen Boyd).
Changes in v7:
- Use static supply entries instead of dynamic allocation (Andrzej Hajda).
- Defer bridge driver probe if panel is not probed (Andrzej Hajda).
- Update of_graph APIs for correct node reference management. (Andrzej Hajda).
- Remove local display_mode object (Andrzej Hajda).
- Remove version id check function from driver.
Changes in v8:
- Move dsi register/attach function to bridge driver probe (Andrzej Hajda).
- Introduce a new helper function to write 16bit words into consecutive registers (Andrzej Hajda).
- Remove unnecessary macros (Andrzej Hajda).
--- drivers/gpu/drm/bridge/Kconfig | 9 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 666 ++++++++++++++++++++++++++++++++++ 3 files changed, 676 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
drivers/gpu/drm/bridge/Kconfig +9 -0
@@ -108,6 +108,15 @@ config DRM_TI_TFP410 ---help--- Texas Instruments TFP410 DVI/HDMI Transmitter driver +config DRM_TI_SN65DSI86 + tristate "TI SN65DSI86 DSI to eDP bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + select DRM_PANEL + ---help--- + Texas Instruments SN65DSI86 DSI to eDP Bridge driver + source "drivers/gpu/drm/bridge/analogix/Kconfig" source "drivers/gpu/drm/bridge/adv7511/Kconfig"
drivers/gpu/drm/bridge/Makefile +1 -0
@@ -12,4 +12,5 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o +obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-y += synopsys/
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +666 -0
666 lines not on this page · raw message
Signature · 7 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ Freedreno mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [PATCH v8 1/4] drm/bridge: add support for sn65dsi86 bridge driver
Quoted 10 lines · Sandeep Panda
Add support for TI's sn65dsi86 dsi2edp bridge chip. The chip converts DSI transmitted signal to eDP signal, which is fed to the connected eDP panel.
This chip can be controlled via either i2c interface or dsi interface. Currently in driver all the control registers are being accessed through i2c interface only. Also as of now HPD support has not been added to bridge chip driver.
Quoted 6 lines
Changes in v1:
- Split the dt-bindings and the driver support into separate patches (Andrzej Hajda).
- Use of gpiod APIs to parse and configure gpios instead of obsolete ones (Andrzej Hajda).
- Use macros to define the register offsets (Andrzej Hajda).
This is pretty useless for changelog. This is useful for review but not down the line when this is applied
Since you have cover letter, you may add it there. Or after sob and --- tag in the patch, that way it is skipped while applying..
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 67
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+#define SN_ENABLE_VID_STREAM_BIT BIT(3) +#define SN_DSIA_NUM_LANES_BITS (BIT(4) | BIT(3)) +#define SN_DP_NUM_LANES_BITS (BIT(5) | BIT(4)) +#define SN_DP_DATA_RATE_BITS (BIT(7) | BIT(6) | BIT(5))
GENMASK(7, 5)
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 112
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+static int __maybe_unused ti_sn_bridge_resume (struct device *dev) +{ +struct ti_sn_bridge *pdata =dev_get_drvdata (dev); +int ret =0 ;
superfluous initialization
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 128
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+static int __maybe_unused ti_sn_bridge_suspend (struct device *dev) +{ +struct ti_sn_bridge *pdata =dev_get_drvdata (dev); +int ret =0 ;
here as well
Quoted 5 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0+static int ti_sn_bridge_connector_get_modes (struct drm_connector *connector) +{ +struct ti_sn_bridge *pdata =connector_to_ti_sn_bridge (connector); +struct edid *edid; +u32 num_modes;
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 164
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+ +if (pdata->panel) { +DRM_DEBUG_KMS ("get mode from connected drm_panel\n" ); +return drm_panel_get_modes (pdata->panel); + } + +if (!pdata->ddc) +return 0 ; + +pm_runtime_get_sync (pdata->dev);
you should check return of this
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 314
Quoted 3 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +3
-0+static void ti_sn_bridge_set_refclk (struct ti_sn_bridge *pdata) +{ +int i =0 ;
superfluous initialization
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 406
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+static void ti_sn_bridge_enable (struct drm_bridge *bridge) +{ +struct ti_sn_bridge *pdata =bridge_to_ti_sn_bridge (bridge); +unsigned int val =0 ;
here as well
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 465
Quoted 5 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0+static void ti_sn_bridge_pre_enable (struct drm_bridge *bridge) +{ +struct ti_sn_bridge *pdata =bridge_to_ti_sn_bridge (bridge); + +pm_runtime_get_sync (pdata->dev);
error check required
Signature · 5 lines
~Vinod _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v8 1/4] drm/bridge: add support for sn65dsi86 bridge driver
Quoted 18 lines · Vinod
Quoted 10 lines · Sandeep Panda
Add support for TI's sn65dsi86 dsi2edp bridge chip. The chip converts DSI transmitted signal to eDP signal, which is fed to the connected eDP panel.
This chip can be controlled via either i2c interface or dsi interface. Currently in driver all the control registers are being accessed through i2c interface only. Also as of now HPD support has not been added to bridge chip driver.
Quoted 6 lines
Changes in v1:
- Split the dt-bindings and the driver support into separate patches (Andrzej Hajda).
- Use of gpiod APIs to parse and configure gpios instead of obsolete ones (Andrzej Hajda).
- Use macros to define the register offsets (Andrzej Hajda).
Quoted 5 lines
This is pretty useless for changelog. This is useful for review but not down the line when this is applied
Since you have cover letter, you may add it there. Or after sob and --- tag in the patch, that way it is skipped while applying..
FWIW, in drm we prefer the changelog is included in the commit message. It gives credit to the reviewers, sometimes explains why decisions were made, and commit message space is cheap :-).
Sean
Quoted 62 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 67
Quoted 5 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+#define SN_ENABLE_VID_STREAM_BIT BIT(3) +#define SN_DSIA_NUM_LANES_BITS (BIT(4) | BIT(3)) +#define SN_DP_NUM_LANES_BITS (BIT(5) | BIT(4)) +#define SN_DP_DATA_RATE_BITS (BIT(7) | BIT(6) | BIT(5))
GENMASK(7, 5)drivers/gpu/drm/bridge/ti-sn65dsi86.c line 112
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+static int __maybe_unused ti_sn_bridge_resume (struct device *dev) +{ +struct ti_sn_bridge *pdata =dev_get_drvdata (dev); +int ret =0 ;superfluous initialization
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 128
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+static int __maybe_unused ti_sn_bridge_suspend (struct device *dev) +{ +struct ti_sn_bridge *pdata =dev_get_drvdata (dev); +int ret =0 ;here as well
Quoted 5 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0+static int ti_sn_bridge_connector_get_modes (struct drm_connector *connector) +{ +struct ti_sn_bridge *pdata =connector_to_ti_sn_bridge (connector); +struct edid *edid; +u32 num_modes;drivers/gpu/drm/bridge/ti-sn65dsi86.c line 164
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+ +if (pdata->panel) { +DRM_DEBUG_KMS ("get mode from connected drm_panel\n" ); +return drm_panel_get_modes (pdata->panel); + } + +if (!pdata->ddc) +return 0 ; + +pm_runtime_get_sync (pdata->dev);you should check return of this
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 314
Quoted 3 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +3
-0+static void ti_sn_bridge_set_refclk (struct ti_sn_bridge *pdata) +{ +int i =0 ;superfluous initialization
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 406
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+static void ti_sn_bridge_enable (struct drm_bridge *bridge) +{ +struct ti_sn_bridge *pdata =bridge_to_ti_sn_bridge (bridge); +unsigned int val =0 ;here as well
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 465
Quoted 5 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0+static void ti_sn_bridge_pre_enable (struct drm_bridge *bridge) +{ +struct ti_sn_bridge *pdata =bridge_to_ti_sn_bridge (bridge); + +pm_runtime_get_sync (pdata->dev);error check required
Signature · 1 line
~Vinod
Signature · 5 lines
Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v8 1/4] drm/bridge: add support for sn65dsi86 bridge driver
In reply to Sandeep PandaQuoted 117 lines · Sandeep Panda
Add support for TI's sn65dsi86 dsi2edp bridge chip. The chip converts DSI transmitted signal to eDP signal, which is fed to the connected eDP panel.
This chip can be controlled via either i2c interface or dsi interface. Currently in driver all the control registers are being accessed through i2c interface only. Also as of now HPD support has not been added to bridge chip driver.
Changes in v1:
- Split the dt-bindings and the driver support into separate patches (Andrzej Hajda).
- Use of gpiod APIs to parse and configure gpios instead of obsolete ones (Andrzej Hajda).
- Use macros to define the register offsets (Andrzej Hajda).Changes in v2:
- Separate out edp panel specific HW resource handling from bridge driver and create a separate edp panel drivers to handle panel specific mode information and HW resources (Sean Paul).
- Replace pr_* APIs to DRM_* APIs to log error or debug information (Sean Paul).
- Remove some of the unnecessary structure/variable from driver (Sean Paul).
- Rename the function and structure prefix "sn65dsi86" to "ti_sn_bridge" (Sean Paul / Rob Herring).
- Remove most of the hard-coding and modified the bridge init sequence based on current mode (Sean Paul).
- Remove the existing function to retrieve the EDID data and implemented this as ani2c_adapterand usedrm_get_edid()(Sean Paul).
- Remove the dummy irq handler implementation, will add back the proper irq handling later (Sean Paul).
- Capture the required enable gpios in a single array based on dt entry instead of having individual descriptor for each gpio (Sean Paul).Changes in v3:
- Remove usage ofirq_gpioand replace it as "interrupts" property (Rob Herring).
- Remove the unnecessary header file inclusions (Sean Paul).
- Rearrange the header files in alphabetical order (Sean Paul).
- Use regmap interface to perform i2c transactions.
- Update Copyright/License field and address other review comments (Jordan Crouse).Changes in v4:
- Update License/Copyright (Sean Paul).
- AddKconfigandMakefilechanges (Sean Paul).
- Drop i2c gpio handling from this bridge driver, since i2c sda/scl gpios will be handled by i2c master.
- Update required supplies names.
- Remove unnecessary goto statements (Sean Paul).
- Add mutex lock topower_ctrlAPI to avoid race conditions (Sean Paul).
- Add support to parse reference clk frequency from dt(optional).
- Update the bridge chip enable/disable sequence.Changes in v5:
- FixedKbuildtest service reported warnings.Changes in v6:
- Use PM runtime based ref-counting instead of localref_countmechanism (Stephen Boyd).
- Clean up some debug logs and indentations (Sean Paul).
- Simplify dp rate calculation (Sean Paul).
- Add support to configure refclk based on input REFCLK pin or DACP/N pin (Stephen Boyd).Changes in v7:
- Use static supply entries instead of dynamic allocation (Andrzej Hajda).
- Defer bridge driver probe if panel is not probed (Andrzej Hajda).
- Updateof_graphAPIs for correct node reference management. (Andrzej Hajda).
- Remove localdisplay_modeobject (Andrzej Hajda).
- Remove version id check function from driver.Changes in v8:
- Move dsi register/attach function to bridge driver probe (Andrzej Hajda).
- Introduce a new helper function to write 16bit words into consecutive registers (Andrzej Hajda).
- Remove unnecessary macros (Andrzej Hajda).Signed-off-by Sandeep Panda <[email protected]>--- drivers/gpu/drm/bridge/Kconfig | 9 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 666 ++++++++++++++++++++++++++++++++++ 3 files changed, 676 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.cdrivers/gpu/drm/bridge/Kconfig +9
-0@@ -108,6 +108,15 @@ config DRM_TI_TFP410 ---help--- Texas Instruments TFP410 DVI/HDMI Transmitter driver +config DRM_TI_SN65DSI86 + tristate "TI SN65DSI86 DSI to eDP bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + select DRM_PANEL + ---help--- + Texas Instruments SN65DSI86 DSI to eDP Bridge driver + source "drivers/gpu/drm/bridge/analogix/Kconfig" source "drivers/gpu/drm/bridge/adv7511/Kconfig"drivers/gpu/drm/bridge/Makefile +0
-0
drivers/gpu/drm/bridge/Makefile obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o · line 15
Quoted 4 lines
drivers/gpu/drm/bridge/Makefile +1
-0@@ -12,4 +12,5 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o +obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
SN65DSI86 should be in front of TFP410 here and above.
drivers/gpu/drm/bridge/ti-sn65dsi86.c
Quoted 6 lines
drivers/gpu/drm/bridge/Makefile +0
-0obj-y += synopsys/drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +0
-0
/snip
Quoted 31 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +31
-0+ +#define REFCLK_LUT_SIZE 5 + +/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ +static const u32 ti_sn_bridge_refclk_lut[] = { +12000000 , +19200000 , +26000000 , +27000000 , +38400000 , +}; + +/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ +static const u32 ti_sn_bridge_dsiclk_lut[] = { +468000000 , +384000000 , +416000000 , +486000000 , +460800000 , +}; + +static void ti_sn_bridge_set_refclk (struct ti_sn_bridge *pdata) +{ +int i =0 ; +u8 refclk_src; +u32 refclk_rate; +const u32 *refclk_lut; + +if (pdata->refclk) { + refclk_src =DPPLL_CLK_SRC_REFCLK ; + refclk_rate =clk_get_rate (pdata->refclk);
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 331
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+ refclk_lut = ti_sn_bridge_refclk_lut; +clk_prepare_enable (pdata->refclk); + }else { + refclk_src =DPPLL_CLK_SRC_DSICLK ; + refclk_rate =ti_sn_bridge_get_dsi_freq (pdata) *1000 ; + refclk_lut = ti_sn_bridge_dsiclk_lut; + } + +/* for i equals to REFCLK_LUT_SIZE means default frequency */ +for (i =0 ; i <REFCLK_LUT_SIZE ; i++)
Instead of REFCLK_LUT_SIZE, use a local variable, ie:
size_t refclk_lut_size;
...
if(pdata->refclk) {
...
refclk_lut = ti_sn_bridge_refclk_lut;
refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
...
} else {
...
refclk_lut = ti_sn_bridge_dsiclk_lut;
refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
}And remove REFCLK_LUT_SIZE.
Quoted 71 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +71
-0+if (refclk_lut[i] == refclk_rate) +break ; + +regmap_write (pdata->regmap,SN_REFCLK_FREQ_REG , + (refclk_src | (i <<SN_DSIA_REFCLK_OFFSET ))); +} + +/** +* LUT index corresponds to register value and +* LUT values corresponds to dp data rate supported +* by the bridge in Mbps unit. +*/ +static const unsigned int ti_sn_bridge_dp_rate_lut[] = { +0 ,1620 ,2160 ,2430 ,2700 ,3240 ,4320 ,5400 +}; + +static void ti_sn_bridge_set_dsi_dp_rate (struct ti_sn_bridge *pdata) +{ +unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz; +unsigned int val =0 , i =0 ; +struct drm_display_mode *mode = + &pdata->bridge.encoder->crtc->state->adjusted_mode; + +/* set DSIA clk frequency */ + bit_rate_mhz = (mode->clock /1000 ) * +mipi_dsi_pixel_format_to_bpp (pdata->dsi->format); + clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes *2 ); + +/* for each increment in val, frequency increases by 5MHz */ + val = (MIN_DSI_CLK_FREQ_MHZ /5 ) + + (((clk_freq_mhz -MIN_DSI_CLK_FREQ_MHZ ) /5 ) &0xFF ); +regmap_write (pdata->regmap,SN_DSIA_CLK_FREQ_REG , val); + +/* set DP data rate */ + dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) *DP_CLK_FUDGE_NUM ) / +DP_CLK_FUDGE_DEN ; +for (i =0 ; i <ARRAY_SIZE (ti_sn_bridge_dp_rate_lut) -1 ; i++) +if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz) +break ; + +regmap_update_bits (pdata->regmap,SN_DATARATE_CONFIG_REG , +SN_DP_DATA_RATE_BITS , i <<SN_DP_DATA_RATE_OFFSET ); +} + +static void ti_sn_bridge_set_video_timings (struct ti_sn_bridge *pdata) +{ +struct drm_display_mode *mode = + &pdata->bridge.encoder->crtc->state->adjusted_mode; + +ti_sn_bridge_write_u16 (pdata,SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG , + mode->hdisplay); +ti_sn_bridge_write_u16 (pdata,SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG , + mode->vdisplay); +ti_sn_bridge_write_u16 (pdata,SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG , + mode->hsync_end - mode->hsync_start); +ti_sn_bridge_write_u16 (pdata,SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG , + mode->vsync_end - mode->vsync_start); + +regmap_write (pdata->regmap,SN_CHA_HORIZONTAL_BACK_PORCH_REG , + (mode->htotal - mode->hsync_end) &0xFF ); +regmap_write (pdata->regmap,SN_CHA_VERTICAL_BACK_PORCH_REG , + (mode->vtotal - mode->vsync_end) &0xFF ); + +regmap_write (pdata->regmap,SN_CHA_HORIZONTAL_FRONT_PORCH_REG , + (mode->hsync_start - mode->hdisplay) &0xFF ); +regmap_write (pdata->regmap,SN_CHA_VERTICAL_FRONT_PORCH_REG , + (mode->vsync_start - mode->vdisplay) &0xFF ); + +usleep_range (10000 ,10500 );/* 10ms delay recommended by spec */ +} +
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 412
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+static void ti_sn_bridge_enable (struct drm_bridge *bridge) +{ +struct ti_sn_bridge *pdata =bridge_to_ti_sn_bridge (bridge); +unsigned int val =0 ; + +if (pdata->panel) { +drm_panel_prepare (pdata->panel); +/* in case drm_panel is connected then HPD is not supported */ +regmap_update_bits (pdata->regmap,SN_HPD_DISABLE_REG , +SN_HPD_DISABLE_BIT , !0 );
What is !0?
Sean
/snip
Signature · 5 lines
Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v8 1/4] drm/bridge: add support for sn65dsi86 bridge driver
Quoted 123 lines · Sean Paul
Quoted 122 lines · Sandeep Panda
Add support for TI's sn65dsi86 dsi2edp bridge chip. The chip converts DSI transmitted signal to eDP signal, which is fed to the connected eDP panel.
This chip can be controlled via either i2c interface or dsi interface. Currently in driver all the control registers are being accessed through i2c interface only. Also as of now HPD support has not been added to bridge chip driver.
Changes in v1:
- Split the dt-bindings and the driver support into separate patches (Andrzej Hajda).
- Use of gpiod APIs to parse and configure gpios instead of obsolete
ones
(Andrzej Hajda).
- Use macros to define the register offsets (Andrzej Hajda).Changes in v2:
- Separate out edp panel specific HW resource handling from bridge driver and create a separate edp panel drivers to handle panel specific mode information and HW resources (Sean Paul).
- Replace pr_* APIs to DRM_* APIs to log error or debug information (Sean Paul).
- Remove some of the unnecessary structure/variable from driver (Sean Paul).
- Rename the function and structure prefix "sn65dsi86" to
"ti_sn_bridge"
(Sean Paul / Rob Herring).
- Remove most of the hard-coding and modified the bridge init
sequence
based on current mode (Sean Paul).
- Remove the existing function to retrieve the EDID data and implemented this as ani2c_adapterand usedrm_get_edid()(Sean
Paul).
- Remove the dummy irq handler implementation, will add back the proper irq handling later (Sean Paul).
- Capture the required enable gpios in a single array based on dt
entry
instead of having individual descriptor for each gpio (Sean Paul).Changes in v3:
- Remove usage ofirq_gpioand replace it as "interrupts" property
(Rob
Herring).
- Remove the unnecessary header file inclusions (Sean Paul).
- Rearrange the header files in alphabetical order (Sean Paul).
- Use regmap interface to perform i2c transactions.
- Update Copyright/License field and address other review comments (Jordan Crouse).Changes in v4:
- Update License/Copyright (Sean Paul).
- AddKconfigandMakefilechanges (Sean Paul).
- Drop i2c gpio handling from this bridge driver, since i2c sda/scl
gpios
will be handled by i2c master.
- Update required supplies names.
- Remove unnecessary goto statements (Sean Paul).
- Add mutex lock topower_ctrlAPI to avoid race conditions (Sean Paul).
- Add support to parse reference clk frequency from dt(optional).
- Update the bridge chip enable/disable sequence.Changes in v5:
- FixedKbuildtest service reported warnings.Changes in v6:
- Use PM runtime based ref-counting instead of localref_count
mechanism
(Stephen Boyd).
- Clean up some debug logs and indentations (Sean Paul).
- Simplify dp rate calculation (Sean Paul).
- Add support to configure refclk based on input REFCLK pin or DACP/N pin (Stephen Boyd).Changes in v7:
- Use static supply entries instead of dynamic allocation (Andrzej Hajda).
- Defer bridge driver probe if panel is not probed (Andrzej Hajda).
- Updateof_graphAPIs for correct node reference management.
(Andrzej
Hajda).
- Remove localdisplay_modeobject (Andrzej Hajda).
- Remove version id check function from driver.Changes in v8:
- Move dsi register/attach function to bridge driver probe (Andrzej Hajda).
- Introduce a new helper function to write 16bit words into
consecutive
registers (Andrzej Hajda).
- Remove unnecessary macros (Andrzej Hajda).Signed-off-by Sandeep Panda <[email protected]>--- drivers/gpu/drm/bridge/Kconfig | 9 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 666 ++++++++++++++++++++++++++++++++++ 3 files changed, 676 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.cdrivers/gpu/drm/bridge/Kconfig +9
-0@@ -108,6 +108,15 @@ config DRM_TI_TFP410 ---help--- Texas Instruments TFP410 DVI/HDMI Transmitter driver +config DRM_TI_SN65DSI86 + tristate "TI SN65DSI86 DSI to eDP bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + select DRM_PANEL + ---help--- + Texas Instruments SN65DSI86 DSI to eDP Bridge driver + source "drivers/gpu/drm/bridge/analogix/Kconfig"
Quoted 13 lines
drivers/gpu/drm/bridge/Makefile obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o · line 15
Quoted 10 lines
drivers/gpu/drm/bridge/Kconfig +0
-0source "drivers/gpu/drm/bridge/adv7511/Kconfig"drivers/gpu/drm/bridge/Makefile +1
-0@@ -12,4 +12,5 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o +obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.oSN65DSI86 should be in front of TFP410 here and above.
Ok.
Quoted 70 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c
Quoted 6 lines
drivers/gpu/drm/bridge/Makefile +0
-0obj-y += synopsys/drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +0
-0/snip
Quoted 33 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+ +#define REFCLK_LUT_SIZE 5 + +/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +9
-0+static const u32 ti_sn_bridge_refclk_lut[] = { +12000000 , +19200000 , +26000000 , +27000000 , +38400000 , +}; + +/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +18
-0+static const u32 ti_sn_bridge_dsiclk_lut[] = { +468000000 , +384000000 , +416000000 , +486000000 , +460800000 , +}; + +static void ti_sn_bridge_set_refclk (struct ti_sn_bridge *pdata) +{ +int i =0 ; +u8 refclk_src; +u32 refclk_rate; +const u32 *refclk_lut; + +if (pdata->refclk) { + refclk_src =DPPLL_CLK_SRC_REFCLK ; + refclk_rate =clk_get_rate (pdata->refclk);drivers/gpu/drm/bridge/ti-sn65dsi86.c line 331
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+ refclk_lut = ti_sn_bridge_refclk_lut; +clk_prepare_enable (pdata->refclk); + }else { + refclk_src =DPPLL_CLK_SRC_DSICLK ; + refclk_rate =ti_sn_bridge_get_dsi_freq (pdata) *1000 ; + refclk_lut = ti_sn_bridge_dsiclk_lut; + } + +/* for i equals to REFCLK_LUT_SIZE means default frequency */ +for (i =0 ; i <REFCLK_LUT_SIZE ; i++)Instead of
REFCLK_LUT_SIZE, use a local variable, ie:size_t refclk_lut_size; ... if(pdata->refclk) { ... refclk_lut = ti_sn_bridge_refclk_lut; refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); ... } else { ... refclk_lut = ti_sn_bridge_dsiclk_lut; refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); }
Quoted 1 line
And remove
REFCLK_LUT_SIZE.
Ok.
Quoted 78 lines
Quoted 78 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +35
-0+if (refclk_lut[i] == refclk_rate) +break ; + +regmap_write (pdata->regmap,SN_REFCLK_FREQ_REG , + (refclk_src | (i <<SN_DSIA_REFCLK_OFFSET ))); +} + +/** +* LUT index corresponds to register value and +* LUT values corresponds to dp data rate supported +* by the bridge in Mbps unit. +*/ +static const unsigned int ti_sn_bridge_dp_rate_lut[] = { +0 ,1620 ,2160 ,2430 ,2700 ,3240 ,4320 ,5400 +}; + +static void ti_sn_bridge_set_dsi_dp_rate (struct ti_sn_bridge *pdata) +{ +unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz; +unsigned int val =0 , i =0 ; +struct drm_display_mode *mode = + &pdata->bridge.encoder->crtc->state->adjusted_mode; + +/* set DSIA clk frequency */ + bit_rate_mhz = (mode->clock /1000 ) * +mipi_dsi_pixel_format_to_bpp (pdata->dsi->format); + clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes *2 ); + +/* for each increment in val, frequency increases by 5MHz */ + val = (MIN_DSI_CLK_FREQ_MHZ /5 ) + + (((clk_freq_mhz -MIN_DSI_CLK_FREQ_MHZ ) /5 ) &0xFF ); +regmap_write (pdata->regmap,SN_DSIA_CLK_FREQ_REG , val); + +/* set DP data rate */ + dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) *
DP_CLK_FUDGE_NUM) /drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+DP_CLK_FUDGE_DEN ; +for (i =0 ; i <ARRAY_SIZE (ti_sn_bridge_dp_rate_lut) -1 ; i++) +if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz) +break ; + +regmap_update_bits (pdata->regmap,SN_DATARATE_CONFIG_REG , +SN_DP_DATA_RATE_BITS , i <<SN_DP_DATA_RATE_OFFSET ); +} + +static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge*pdata)
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +30
-0+{ +struct drm_display_mode *mode = + &pdata->bridge.encoder->crtc->state->adjusted_mode; + +ti_sn_bridge_write_u16 (pdata,SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG , + mode->hdisplay); +ti_sn_bridge_write_u16 (pdata,SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG , + mode->vdisplay); +ti_sn_bridge_write_u16 (pdata,SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG , + mode->hsync_end - mode->hsync_start); +ti_sn_bridge_write_u16 (pdata,SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG , + mode->vsync_end - mode->vsync_start); + +regmap_write (pdata->regmap,SN_CHA_HORIZONTAL_BACK_PORCH_REG , + (mode->htotal - mode->hsync_end) &0xFF ); +regmap_write (pdata->regmap,SN_CHA_VERTICAL_BACK_PORCH_REG , + (mode->vtotal - mode->vsync_end) &0xFF ); + +regmap_write (pdata->regmap,SN_CHA_HORIZONTAL_FRONT_PORCH_REG , + (mode->hsync_start - mode->hdisplay) &0xFF ); +regmap_write (pdata->regmap,SN_CHA_VERTICAL_FRONT_PORCH_REG , + (mode->vsync_start - mode->vdisplay) &0xFF ); + +usleep_range (10000 ,10500 );/* 10ms delay recommended by spec */ +} + +static void ti_sn_bridge_enable (struct drm_bridge *bridge) +{ +struct ti_sn_bridge *pdata =bridge_to_ti_sn_bridge (bridge); +unsigned int val =0 ;
Quoted 8 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 412
Quoted 6 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +6
-0+ +if (pdata->panel) { +drm_panel_prepare (pdata->panel); +/* in case drm_panel is connected then HPD is not supported */ +regmap_update_bits (pdata->regmap,SN_HPD_DISABLE_REG , +SN_HPD_DISABLE_BIT , !0 );What is !0?
There was a comment to make it like this, but i think SN_HPD_DISABLE_BIT makes it more readable. I will change this as it was previously.
Quoted 4 lines
Sean
/snip
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A message that is not in the archive (sent off-list or not yet received): 1528177218-1051-3-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
Re: [PATCH v8 1/4] drm/bridge: add support for sn65dsi86 bridge driver
Quoting Sandeep Panda (2018-06-04 22:40:15)
Quoted 11 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0@@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ +
[...]
Quoted 9 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +9
-0+ +static const struct regmap_config ti_sn_bridge_regmap_config = { + .reg_bits =8 , + .val_bits =8 , + .volatile_table = &ti_sn_bridge_volatile_table, + .cache_type =REGCACHE_NONE , +}; + +static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 112
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+ unsigned int reg, u16 val) +{ +regmap_write (pdata->regmap, reg, val &0xFF ); +regmap_write (pdata->regmap, reg +1 , val >>8 ); +} + +static int __maybe_unused ti_sn_bridge_resume (struct device *dev) +{ +struct ti_sn_bridge *pdata =dev_get_drvdata (dev); +int ret =0 ;
Please don't assign variables and then reassign them again immediately after. It hides use before real initialization bugs.
Quoted 2 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +2
-0+ + ret =regulator_bulk_enable (SN_REGULATOR_SUPPLY_NUM , pdata->supplies);
[...]
Quoted 16 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +16
-0+ +static int ti_sn_bridge_probe (struct i2c_client *client, +const struct i2c_device_id *id) +{ +struct ti_sn_bridge *pdata; +struct device_node *ddc_node; +struct mipi_dsi_host *host; +struct mipi_dsi_device *dsi; +int ret =0 ; +const struct mipi_dsi_device_info info = { .type ="ti_sn_bridge" , + .channel =0 , + .node =NULL , + }; + +if (!i2c_check_functionality (client->adapter,I2C_FUNC_I2C )) { +DRM_ERROR ("device doesn't support I2C\n" );
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 563
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+return -ENODEV ; + } + + ret =ti_sn_bridge_parse_dsi_host (pdata); +if (ret) +return ret; + + host =of_find_mipi_dsi_host_by_node (pdata->host_node); +if (!host) { +DRM_ERROR ("failed to find dsi host\n" );
Not sure we want to print an error and then return -EPROBE_DEFER. Usually EPROBE_DEFER is silent.
Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+ ret = -EPROBE_DEFER ; + goto err_dsi_host; + } +
[...]
Quoted 5 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0+ +/* TODO: setting to 4 lanes always for now */ + dsi->lanes =4 ; + dsi->format =MIPI_DSI_FMT_RGB888 ; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 588
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+MIPI_DSI_MODE_EOT_PACKET |MIPI_DSI_MODE_VIDEO_HSE ; + + ret =mipi_dsi_attach (dsi); +if (ret <0 ) { +DRM_ERROR ("failed to attach dsi to host\n" ); + goto err_dsi_attach; + } + pdata->dsi = dsi; + + pdata->refclk =devm_clk_get (pdata->dev,"refclk" );
We need to check for error
if (IS_ERR(pdata->refclk))
And then if it's EPROBE_DEFER I suppose we would bail out, otherwise assume it's not present?
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Re: [PATCH v8 1/4] drm/bridge: add support for sn65dsi86 bridge driver
Quoted 27 lines · Stephen Boyd
Quoting Sandeep Panda (2018-06-04 22:40:15)
Quoted 11 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0@@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ +[...]
Quoted 14 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +14
-0+ +static const struct regmap_config ti_sn_bridge_regmap_config = { + .reg_bits =8 , + .val_bits =8 , + .volatile_table = &ti_sn_bridge_volatile_table, + .cache_type =REGCACHE_NONE , +}; + +static void ti_sn_bridge_write_u16 (struct ti_sn_bridge *pdata, +unsigned int reg,u16 val) +{ +regmap_write (pdata->regmap, reg, val &0xFF ); +regmap_write (pdata->regmap, reg +1 , val >>8 ); +}
Quoted 9 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c line 112
Quoted 5 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0+ +static int __maybe_unused ti_sn_bridge_resume (struct device *dev) +{ +struct ti_sn_bridge *pdata =dev_get_drvdata (dev); +int ret =0 ;Please don't assign variables and then reassign them again immediately after. It hides use before real initialization bugs.
Ok.
Quoted 60 lines
Quoted 3 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +2
-0+ + ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM,
pdata->supplies);[...]
Quoted 17 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+ +static int ti_sn_bridge_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ti_sn_bridge *pdata; + struct device_node *ddc_node; + struct mipi_dsi_host *host; + struct mipi_dsi_device *dsi; + int ret = 0; + const struct mipi_dsi_device_info info = { .type ="
ti_sn_bridge",drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +6
-0+ .channel = 0, + .node = NULL, + }; + +if (!i2c_check_functionality (client->adapter,I2C_FUNC_I2C )) { +DRM_ERROR ("device doesn't support I2C\n" );drivers/gpu/drm/bridge/ti-sn65dsi86.c line 563
Quoted 10 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +10
-0+return -ENODEV ; + } + + ret =ti_sn_bridge_parse_dsi_host (pdata); +if (ret) +return ret; + + host =of_find_mipi_dsi_host_by_node (pdata->host_node); +if (!host) { +DRM_ERROR ("failed to find dsi host\n" );Not sure we want to print an error and then return -EPROBE_DEFER. Usually
EPROBE_DEFERis silent.Quoted 4 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +4
-0+ ret = -EPROBE_DEFER ; + goto err_dsi_host; + } +[...]
Quoted 8 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +5
-0+ +/* TODO: setting to 4 lanes always for now */ + dsi->lanes =4 ; + dsi->format =MIPI_DSI_FMT_RGB888 ; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_SYNC_PULSE|
+MIPI_DSI_MODE_EOT_PACKET|MIPI_DSI_MODE_VIDEO_HSE;drivers/gpu/drm/bridge/ti-sn65dsi86.c line 588
Quoted 9 lines
drivers/gpu/drm/bridge/ti-sn65dsi86.c new file +9
-0+ + ret =mipi_dsi_attach (dsi); +if (ret <0 ) { +DRM_ERROR ("failed to attach dsi to host\n" ); + goto err_dsi_attach; + } + pdata->dsi = dsi; + + pdata->refclk =devm_clk_get (pdata->dev,"refclk" );We need to check for error
Quoted 4 lines
if (IS_ERR(pdata->refclk))And then if it's
EPROBE_DEFERI suppose we would bail out, otherwise assume it's not present?
Yes found this issue while testing the driver on actual sn65dsi86 HW, i will fix this in next patchset.
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PATCH v8 2/4 dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
In reply to a message not in the archiveDocument the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with existing bindings (Andrzej Hajda).
- Add missing dt-binding that are parsed by corresponding driver (Andrzej Hajda).
Changes in v2:
- Remove edp panel specific dt-binding entries. Only keep bridge
specific entries (Sean Paul).
- Remove custom-modes dt entry since its usage is removed from driver also (Sean Paul).
- Remove is-pluggable dt entry since this will not be needed anymore (Sean Paul).
Changes in v3:
- Remove irq-gpio dt entry and instead populate is an interrupt property (Rob Herring).
Changes in v4:
- Add link to bridge chip datasheet (Stephen Boyd)
- Add vpll and vcc regulator supply bindings (Stephen Boyd)
- Add ref clk optional dt binding (Stephen Boyd)
- Add gpio-controller optional dt binding (Stephen Boyd)
Changes in v5:
- Use clock property to specify the input refclk (Stephen Boyd).
- Update gpio cell and pwm cell numbers (Stephen Boyd).
Changes in v6:
- Add property to mention the lane mapping scheme and polarity inversion (Stephen Boyd).
Changes in v7:
- Detail description of lane mapping scheme dt property (Andrzej Hajda/ Rob Herring).
- Removed HDP gpio binding, since the bridge uses IRQ signal to determine HPD, and IRQ property is already documented in binding.
--- .../bindings/display/bridge/ti,sn65dsi86.txt | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +109 -0
@@ -0,0 +1,109 @@ +SN65DSI86 DSI to eDP bridge chip +-------------------------------- + +This is the binding for Texas Instruments SN65DSI86 bridge. +http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf + +Required properties: +- compatible: Must be "ti,sn65dsi86" +- reg: i2c address of the chip, 0x2d as per datasheet +- enable-gpios: OF device-tree gpio specification for bridge_en pin (active high) + +- vccio-supply: A 1.8V supply that powers up the digital IOs. +- vpll-supply: A 1.8V supply that powers up the displayport PLL. +- vcca-supply: A 1.2V supply that powers up the analog circuits. +- vcc-supply: A 1.2V supply that powers up the digital core. + +Optional properties: +- interrupts: Specifier for the SN65DSI86 interrupt line. + +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing + +- gpio-controller: Marks the device has a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. + See ../../gpio/gpio.txt for more information. +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of + the cell formats. + +- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. + +- lane-mapping: Specification to describe the logical to physical lane + mapping scheme and polarity inversion of eDP lanes on PCB. + Each pair present at index n (where n lies between 0 and 3) + describes the lane mapping of logical lane to physical lane n + and the polarity(it should be either 1 or 0) of the physical lane n. + + For example: + lane-mapping = <2 1>, + <1 0>, + <3 1>, + <0 0>; + + The above mapping describes that logical lane 2 is mapped to + physical lane 0 and polarity of physical lane 0 is inverted, + logical lane 1 is mapped to physical lane 1 and polarity of + physical lane 1 is normal, logical lane 3 is mapped to physical + lane 2 and polarity of physical lane 2 is inverted, logical lane 0 + is mapped to physical lane 4 and polarity of physical lane 3 is normal. + + If this property is not mentioned then it is assumed that physical + lanes 0 through 3 are mapped to logical lanes 0 through 3 and polarity + of all physical lanes is normal. + +Required nodes: +This device has two video ports. Their connections are modelled using the +OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. + +- Video port 0 for DSI input +- Video port 1 for eDP output + +Example +------- + +edp-bridge@2d { + compatible = "ti,sn65dsi86"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2d>; + + enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + + vccio-supply = <&pm8916_l17>; + vcca-supply = <&pm8916_l6>; + vpll-supply = <&pm8916_l17>; + vcc-supply = <&pm8916_l6>; + + clock-names = "refclk"; + clocks = <&input_refclk>; + + lane-mapping = <0 0>, /* Logical lane 0 is routed to physical lane 0 (!inv) */ + <1 1>, /* Logical lane 1 is routed to physical lane 1 (inv) */ + <2 0>, /* Logical lane 2 is routed to physical lane 2 (!inv) */ + <3 1>; /* Logical lane 3 is routed to physical lane 3 (inv) */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}
Signature · 7 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ Freedreno mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/freedreno
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Re: [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
Quoted 73 lines · Sandeep Panda
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with existing bindings (Andrzej Hajda).
- Add missing dt-binding that are parsed by corresponding driver (Andrzej Hajda).Changes in v2:
- Remove edp panel specific dt-binding entries. Only keep bridge
specific entries (Sean Paul).
- Remove custom-modes dt entry since its usage is removed from driver also (Sean Paul).
- Remove is-pluggable dt entry since this will not be needed anymore (Sean Paul).Changes in v3:
- Remove irq-gpio dt entry and instead populate is an interrupt property (Rob Herring).Changes in v4:
- Add link to bridge chip datasheet (Stephen Boyd)
- Add vpll and vcc regulator supply bindings (Stephen Boyd)
- Add ref clk optional dt binding (Stephen Boyd)
- Add gpio-controller optional dt binding (Stephen Boyd)Changes in v5:
- Use clock property to specify the input refclk (Stephen Boyd).
- Update gpio cell and pwm cell numbers (Stephen Boyd).Changes in v6:
- Add property to mention the lane mapping scheme and polarity inversion (Stephen Boyd).Changes in v7:
- Detail description of lane mapping scheme dt property (Andrzej Hajda/ Rob Herring).
- Removed HDP gpio binding, since the bridge uses IRQ signal to determine HPD, and IRQ property is already documented in binding.Signed-off-by Sandeep Panda <[email protected]>--- .../bindings/display/bridge/ti,sn65dsi86.txt | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txtDocumentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +23
-0@@ -0,0 +1,109 @@ +SN65DSI86 DSI to eDP bridge chip +-------------------------------- + +This is the binding for Texas Instruments SN65DSI86 bridge. +http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf + +Required properties: +- compatible: Must be "ti,sn65dsi86" +- reg: i2c address of the chip, 0x2d as per datasheet +- enable-gpios: OF device-tree gpio specification for bridge_en pin (active high) + +- vccio-supply: A 1.8V supply that powers up the digital IOs. +- vpll-supply: A 1.8V supply that powers up the displayport PLL. +- vcca-supply: A 1.2V supply that powers up the analog circuits. +- vcc-supply: A 1.2V supply that powers up the digital core. + +Optional properties: +- interrupts: Specifier for the SN65DSI86 interrupt line. + +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing + +- gpio-controller: Marks the device has a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt line 33
Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +10
-0+ the second cell is used to specify flags. + See ../../gpio/gpio.txt for more information. +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of + the cell formats. + +- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. + +- lane-mapping: Specification to describe the logical to physical lane
As I mentioned in v7, we already have a property for this. It's called 'data-lanes' and defined in media/video-interfaces.txt. Use that. If you need polarity too, then add a property for that. And add it to video-interfaces.txt.
Quoted 84 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +76
-0+ mapping scheme and polarity inversion of eDP lanes on PCB. + Each pair present at index n (where n lies between 0 and 3) + describes the lane mapping of logical lane to physical lane n + and the polarity(it should be either 1 or 0) of the physical lane n. + + For example: + lane-mapping = <2 1>, + <1 0>, + <3 1>, + <0 0>; + + The above mapping describes that logical lane 2 is mapped to + physical lane 0 and polarity of physical lane 0 is inverted, + logical lane 1 is mapped to physical lane 1 and polarity of + physical lane 1 is normal, logical lane 3 is mapped to physical + lane 2 and polarity of physical lane 2 is inverted, logical lane 0 + is mapped to physical lane 4 and polarity of physical lane 3 is normal. + + If this property is not mentioned then it is assumed that physical + lanes 0 through 3 are mapped to logical lanes 0 through 3 and polarity + of all physical lanes is normal. + +Required nodes: +This device has two video ports. Their connections are modelled using the +OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. + +- Video port 0 for DSI input +- Video port 1 for eDP output + +Example +------- + +edp-bridge@2d { + compatible = "ti,sn65dsi86"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2d>; + + enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + + vccio-supply = <&pm8916_l17>; + vcca-supply = <&pm8916_l6>; + vpll-supply = <&pm8916_l17>; + vcc-supply = <&pm8916_l6>; + + clock-names = "refclk"; + clocks = <&input_refclk>; + + lane-mapping = <0 0>, /* Logical lane 0 is routed to physical lane 0 (!inv) */ + <1 1>, /* Logical lane 1 is routed to physical lane 1 (inv) */ + <2 0>, /* Logical lane 2 is routed to physical lane 2 (!inv) */ + <3 1>; /* Logical lane 3 is routed to physical lane 3 (inv) */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}Signature · 7 lines
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Re: [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
Quoted 93 lines · Rob Herring
Quoted 92 lines · Sandeep Panda
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with
existing
bindings (Andrzej Hajda).
- Add missing dt-binding that are parsed by corresponding driver (Andrzej Hajda).Changes in v2:
- Remove edp panel specific dt-binding entries. Only keep bridge specific entries (Sean Paul).
- Remove custom-modes dt entry since its usage is removed from driver
also (Sean Paul).
- Remove is-pluggable dt entry since this will not be needed anymore
(Sean Paul).Changes in v3:
- Remove irq-gpio dt entry and instead populate is an interrupt property (Rob Herring).Changes in v4:
- Add link to bridge chip datasheet (Stephen Boyd)
- Add vpll and vcc regulator supply bindings (Stephen Boyd)
- Add ref clk optional dt binding (Stephen Boyd)
- Add gpio-controller optional dt binding (Stephen Boyd)Changes in v5:
- Use clock property to specify the input refclk (Stephen Boyd).
- Update gpio cell and pwm cell numbers (Stephen Boyd).Changes in v6:
- Add property to mention the lane mapping scheme and polarity
inversion
(Stephen Boyd).Changes in v7:
- Detail description of lane mapping scheme dt property (Andrzej Hajda/ Rob Herring).
- Removed HDP gpio binding, since the bridge uses IRQ signal to determine HPD, and IRQ property is already documented in binding.Signed-off-by Sandeep Panda <[email protected]>--- .../bindings/display/bridge/ti,sn65dsi86.txt | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt(quoted diff) +0
-0
b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txtDocumentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +10
-0@@ -0,0 +1,109 @@ +SN65DSI86 DSI to eDP bridge chip +-------------------------------- + +This is the binding for Texas Instruments SN65DSI86 bridge. +http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf + +Required properties: +- compatible: Must be "ti,sn65dsi86" +- reg: i2c address of the chip, 0x2d as per datasheet +- enable-gpios: OF device-tree gpio specification for bridge_en pin(active high)
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +10
-0+ +- vccio-supply: A 1.8V supply that powers up the digital IOs. +- vpll-supply: A 1.8V supply that powers up the displayport PLL. +- vcca-supply: A 1.2V supply that powers up the analog circuits. +- vcc-supply: A 1.2V supply that powers up the digital core. + +Optional properties: +- interrupts: Specifier for the SN65DSI86 interrupt line. + +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDIDprobing
++- gpio-controller: Marks the device has a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin numberand
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +3
-0+ the second cell is used to specify flags. + See ../../gpio/gpio.txt for more information. +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for descriptionof
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +5
-0+ the cell formats. + +- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
Quoted 8 lines
Quoted 3 lines
+
+- lane-mapping: Specification to describe the logical to physical laneAs I mentioned in v7, we already have a property for this. It's called 'data-lanes' and defined in
media/video-interfaces.txt. Use that. If you need polarity too, then add a property for that. And add it to video-interfaces.txt.
The data-lanes property mentioned in media/video-interfaces.txt is referring to DSI/CSI lanes where assumption is clock lane is fixed at index 0. But here the we want to mention about eDP lanes which do not have dedicated clock lane. So can we still use the existing data-lanes property here?
Quoted 90 lines
Quoted 90 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +4
-0+ mapping scheme and polarity inversion of eDP lanes on PCB. + Each pair present at index n (where n lies between 0 and 3) + describes the lane mapping of logical lane to physical lane n + and the polarity(it should be either 1 or 0) of the physical lanen.
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +13
-0+ + For example: + lane-mapping = <2 1>, + <1 0>, + <3 1>, + <0 0>; + + The above mapping describes that logical lane 2 is mapped to + physical lane 0 and polarity of physical lane 0 is inverted, + logical lane 1 is mapped to physical lane 1 and polarity of + physical lane 1 is normal, logical lane 3 is mapped to physical + lane 2 and polarity of physical lane 2 is inverted, logical lane 0 + is mapped to physical lane 4 and polarity of physical lane 3 isnormal.
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +3
-0+ + If this property is not mentioned then it is assumed that physical + lanes 0 through 3 are mapped to logical lanes 0 through 3 andpolarity
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +4
-0+ of all physical lanes is normal. + +Required nodes: +This device has two video ports. Their connections are modelled usingthe
+OF graph bindings specified inDocumentation/devicetree/bindings/graph.txt.Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +26
-0+ +- Video port 0 for DSI input +- Video port 1 for eDP output + +Example +------- + +edp-bridge@2d { + compatible = "ti,sn65dsi86"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2d>; + + enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + + vccio-supply = <&pm8916_l17>; + vcca-supply = <&pm8916_l6>; + vpll-supply = <&pm8916_l17>; + vcc-supply = <&pm8916_l6>; + + clock-names = "refclk"; + clocks = <&input_refclk>; + + lane-mapping = <0 0>, /* Logical lane 0 is routed to physical lane0 (!inv) */
(quoted diff) +1
-0+ <1 1>, /* Logical lane 1 is routed to physical lane 1 (inv)*/
(quoted diff) +1
-0+ <2 0>, /* Logical lane 2 is routed to physical lane 2 (!inv)*/
(quoted diff) +1
-0+ <3 1>; /* Logical lane 3 is routed to physical lane 3 (inv)*/
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +22
-1+ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +} --The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Quoted 4 lines
Quoted 4 lines
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Re: [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
Quoting [email protected] (2018-06-05 21:50:16)
Quoted 3 lines · Rob Herring
Quoted 2 lines · Sandeep Panda
Quoted 1 line
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
[...]
Quoted 20 lines
Quoted 11 lines
Quoted 11 lines
and
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +3
-0+ the second cell is used to specify flags. + See ../../gpio/gpio.txt for more information. +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for descriptionof
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +6
-0+ the cell formats. + +- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. +Quoted 8 lines
Quoted 2 lines
+- lane-mapping: Specification to describe the logical to physical lane
As I mentioned in v7, we already have a property for this. It's called 'data-lanes' and defined in
media/video-interfaces.txt. Use that. If you
need polarity too, then add a property for that. And add it to video-interfaces.txt.
Quoted 7 lines
The data-lanes property mentioned in
media/video-interfaces.txtis referring
to DSI/CSI lanes where assumption is clock lane is fixed at index 0. But here
the we want to mention about eDP lanes which do not have dedicated clock lane.
So can we still use the existing data-lanes property here?
Why is that a problem? It's just a property name.
There are data-lanes and clock-lanes properties in the video-interfaces.txt file by the way. It would be nice if that document could be updated for displayport and DSI (e.g. clock-noncontinuous or link-frequencies) or even just mention in there that these can apply to DSI and displayport too.
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Re: [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
Quoted 33 lines · Stephen Boyd
Quoting [email protected] (2018-06-05 21:50:16)
Quoted 3 lines · Rob Herring
Quoted 2 lines · Sandeep Panda
Quoted 1 line
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
[...]
Quoted 20 lines
Quoted 11 lines
Quoted 11 lines
and
(quoted diff) +3
-0+ the second cell is used to specify flags. + See ../../gpio/gpio.txt for more information. +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for descriptionof
(quoted diff) +6
-0+ the cell formats. + +- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. +Quoted 8 lines
Quoted 2 lines
+- lane-mapping: Specification to describe the logical to physical lane
As I mentioned in v7, we already have a property for this. It's called 'data-lanes' and defined in
media/video-interfaces.txt. Use that. If you
need polarity too, then add a property for that. And add it to video-interfaces.txt.Quoted 7 lines
The data-lanes property mentioned in
media/video-interfaces.txtis referring
to DSI/CSI lanes where assumption is clock lane is fixed at index 0. But here
the we want to mention about eDP lanes which do not have dedicated clock lane.
So can we still use the existing data-lanes property here?
Quoted 7 lines
Why is that a problem? It's just a property name.
There are data-lanes and clock-lanes properties in the video-interfaces.txt file by the way. It would be nice if that document could be updated for displayport and DSI (e.g. clock-noncontinuous or link-frequencies) or even just mention in there that these can apply to DSI and displayport too.
For this current review, i have modified the property description to point to media/video.txt for explanation.
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Re: [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
In reply to Rob HerringQuoting Rob Herring (2018-06-05 08:20:50)
Quoted 12 lines
Quoted 12 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +12
-0+ +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing + +- gpio-controller: Marks the device has a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. + See ../../gpio/gpio.txt for more information. +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of + the cell formats. + +- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt line 33
Quoted 3 lines
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +3
-0+ clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. + +- lane-mapping: Specification to describe the logical to physical laneAs I mentioned in v7, we already have a property for this. It's called 'data-lanes' and defined in
media/video-interfaces.txt. Use that. If you need polarity too, then add a property for that. And add it to video-interfaces.txt.
Looks like inversion is already handled by the 'lane-polarities' property.
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Re: [PATCH v8 2/4] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
In reply to Rob HerringQuoted 93 lines · Rob Herring
Quoted 92 lines · Sandeep Panda
Document the bindings used for the sn65dsi86 DSI to eDP bridge.
Changes in v1:
- Rephrase the dt-binding descriptions to be more inline with
existing
bindings (Andrzej Hajda).
- Add missing dt-binding that are parsed by corresponding driver (Andrzej Hajda).Changes in v2:
- Remove edp panel specific dt-binding entries. Only keep bridge specific entries (Sean Paul).
- Remove custom-modes dt entry since its usage is removed from driver
also (Sean Paul).
- Remove is-pluggable dt entry since this will not be needed anymore
(Sean Paul).Changes in v3:
- Remove irq-gpio dt entry and instead populate is an interrupt property (Rob Herring).Changes in v4:
- Add link to bridge chip datasheet (Stephen Boyd)
- Add vpll and vcc regulator supply bindings (Stephen Boyd)
- Add ref clk optional dt binding (Stephen Boyd)
- Add gpio-controller optional dt binding (Stephen Boyd)Changes in v5:
- Use clock property to specify the input refclk (Stephen Boyd).
- Update gpio cell and pwm cell numbers (Stephen Boyd).Changes in v6:
- Add property to mention the lane mapping scheme and polarity
inversion
(Stephen Boyd).Changes in v7:
- Detail description of lane mapping scheme dt property (Andrzej Hajda/ Rob Herring).
- Removed HDP gpio binding, since the bridge uses IRQ signal to determine HPD, and IRQ property is already documented in binding.Signed-off-by Sandeep Panda <[email protected]>--- .../bindings/display/bridge/ti,sn65dsi86.txt | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt(quoted diff) +0
-0
b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txtDocumentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +10
-0@@ -0,0 +1,109 @@ +SN65DSI86 DSI to eDP bridge chip +-------------------------------- + +This is the binding for Texas Instruments SN65DSI86 bridge. +http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf + +Required properties: +- compatible: Must be "ti,sn65dsi86" +- reg: i2c address of the chip, 0x2d as per datasheet +- enable-gpios: OF device-tree gpio specification for bridge_en pin(active high)
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +10
-0+ +- vccio-supply: A 1.8V supply that powers up the digital IOs. +- vpll-supply: A 1.8V supply that powers up the displayport PLL. +- vcca-supply: A 1.2V supply that powers up the analog circuits. +- vcc-supply: A 1.2V supply that powers up the digital core. + +Optional properties: +- interrupts: Specifier for the SN65DSI86 interrupt line. + +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDIDprobing
++- gpio-controller: Marks the device has a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin numberand
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +3
-0+ the second cell is used to specify flags. + See ../../gpio/gpio.txt for more information. +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for descriptionof
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +5
-0+ the cell formats. + +- clock-names: should be "refclk" +- clocks: Specification for input reference clock. The reference + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
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+
+- lane-mapping: Specification to describe the logical to physical laneAs I mentioned in v7, we already have a property for this. It's called 'data-lanes' and defined in
media/video-interfaces.txt. Use that. If you need polarity too, then add a property for that. And add it to video-interfaces.txt.
Ok. modified in next patchset.
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Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +4
-0+ mapping scheme and polarity inversion of eDP lanes on PCB. + Each pair present at index n (where n lies between 0 and 3) + describes the lane mapping of logical lane to physical lane n + and the polarity(it should be either 1 or 0) of the physical lanen.
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +13
-0+ + For example: + lane-mapping = <2 1>, + <1 0>, + <3 1>, + <0 0>; + + The above mapping describes that logical lane 2 is mapped to + physical lane 0 and polarity of physical lane 0 is inverted, + logical lane 1 is mapped to physical lane 1 and polarity of + physical lane 1 is normal, logical lane 3 is mapped to physical + lane 2 and polarity of physical lane 2 is inverted, logical lane 0 + is mapped to physical lane 4 and polarity of physical lane 3 isnormal.
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +3
-0+ + If this property is not mentioned then it is assumed that physical + lanes 0 through 3 are mapped to logical lanes 0 through 3 andpolarity
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +4
-0+ of all physical lanes is normal. + +Required nodes: +This device has two video ports. Their connections are modelled usingthe
+OF graph bindings specified inDocumentation/devicetree/bindings/graph.txt.Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +26
-0+ +- Video port 0 for DSI input +- Video port 1 for eDP output + +Example +------- + +edp-bridge@2d { + compatible = "ti,sn65dsi86"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2d>; + + enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + + vccio-supply = <&pm8916_l17>; + vcca-supply = <&pm8916_l6>; + vpll-supply = <&pm8916_l17>; + vcc-supply = <&pm8916_l6>; + + clock-names = "refclk"; + clocks = <&input_refclk>; + + lane-mapping = <0 0>, /* Logical lane 0 is routed to physical lane0 (!inv) */
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-0+ <1 1>, /* Logical lane 1 is routed to physical lane 1 (inv)*/
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-0+ <2 0>, /* Logical lane 2 is routed to physical lane 2 (!inv)*/
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-0+ <3 1>; /* Logical lane 3 is routed to physical lane 3 (inv)*/
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt new file +22
-1+ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +} --The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
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PATCH v8 3/4 drm/panel: add Innolux TV123WAM panel driver support
In reply to a message not in the archiveAdd support for Innolux TV123WAM, which is a 12.3" eDP display panel with 2160x1440 resolution.
Changes in v1:
- Add the compatibility string, display_mode and panel_desc structures in alphabetical order (Sean Paul).
--- drivers/gpu/drm/panel/panel-simple.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
drivers/gpu/drm/panel/panel-simple.c +27 -0
@@ -1190,6 +1190,30 @@ static void panel_simple_shutdown(struct device *dev) }, }; +static const struct drm_display_mode innolux_tv123wam_mode = { + .clock =206016 , + .hdisplay =2160 , + .hsync_start =2160 +48 , + .hsync_end =2160 +48 +32 , + .htotal =2160 +48 +32 +80 , + .vdisplay =1440 , + .vsync_start =1440 +3 , + .vsync_end =1440 +3 +10 , + .vtotal =1440 +3 +10 +27 , + .vrefresh =60 , + .flags =DRM_MODE_FLAG_PHSYNC |DRM_MODE_FLAG_PVSYNC , +}; + +static const struct panel_desc innolux_tv123wam = { + .modes = &innolux_tv123wam_mode, + .num_modes =1 , + .bpc =8 , + .size = { + .width =259 , + .height =173 , + }, +}; +static const struct drm_display_mode innolux_zj070na_01p_mode = { .clock =51501 , .hdisplay =1024 ,
@@ -2037,6 +2061,9 @@ static void panel_simple_shutdown(struct device *dev) .compatible = "innolux,n156bge-l21", .data = &innolux_n156bge_l21, }, { + .compatible = "innolux,tv123wam", + .data = &innolux_tv123wam, + }, { .compatible = "innolux,zj070na-01p", .data = &innolux_zj070na_01p, }, {
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ Freedreno mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/freedreno
A message that is not in the archive (sent off-list or not yet received): 1528177218-1051-5-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
Sean Paul
Reviewed-byRe: [PATCH v8 3/4] drm/panel: add Innolux TV123WAM panel driver support
Quoted 8 lines · Sandeep Panda
Add support for Innolux TV123WAM, which is a 12.3" eDP display panel with 2160x1440 resolution.
Changes in v1:
- Add the compatibility string,display_modeandpanel_descstructures in alphabetical order (Sean Paul).Signed-off-by Sandeep Panda <[email protected]>
Quoted 53 lines
--- drivers/gpu/drm/panel/panel-simple.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)drivers/gpu/drm/panel/panel-simple.c +27
-0@@ -1190,6 +1190,30 @@ static void panel_simple_shutdown(struct device *dev) }, }; +static const struct drm_display_mode innolux_tv123wam_mode = { + .clock =206016 , + .hdisplay =2160 , + .hsync_start =2160 +48 , + .hsync_end =2160 +48 +32 , + .htotal =2160 +48 +32 +80 , + .vdisplay =1440 , + .vsync_start =1440 +3 , + .vsync_end =1440 +3 +10 , + .vtotal =1440 +3 +10 +27 , + .vrefresh =60 , + .flags =DRM_MODE_FLAG_PHSYNC |DRM_MODE_FLAG_PVSYNC , +}; + +static const struct panel_desc innolux_tv123wam = { + .modes = &innolux_tv123wam_mode, + .num_modes =1 , + .bpc =8 , + .size = { + .width =259 , + .height =173 , + }, +}; +static const struct drm_display_mode innolux_zj070na_01p_mode = { .clock =51501 , .hdisplay =1024 ,@@ -2037,6 +2061,9 @@ static void panel_simple_shutdown(struct device *dev) .compatible = "innolux,n156bge-l21", .data = &innolux_n156bge_l21, }, { + .compatible = "innolux,tv123wam", + .data = &innolux_tv123wam, + }, { .compatible = "innolux,zj070na-01p", .data = &innolux_zj070na_01p, }, {Signature · 2 lines
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Signature · 5 lines
Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ Freedreno mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/freedreno
PATCH v8 4/4 dt-bindings: drm/panel: Document Innolux TV123WAM panel bindings
In reply to a message not in the archiveInnolux TV123WAM is a 12.3" eDP display panel with 2160x1440 resolution, which can be supported by simple panel driver.
Changes in v1:
- Make use of simple panel driver instead of creating a new driver for this panel (Sean Paul).
- Combine dt-binding and driver changes into one patch as done by other existing panel support changes.
Changes in v2:
- Separate driver change from dt-binding documentation (Rob Herring).
- Add the properties from simple-panel binding that are applicable to this panel (Rob Herring).
--- .../bindings/display/panel/innolux,tv123wam.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt
Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt new file +20 -0
@@ -0,0 +1,20 @@ +Innolux TV123WAM 12.3 inch eDP 2K display panel + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. + +Required properties: +- compatible: should be "innolux,tv123wam" +- power-supply: regulator to provide the supply voltage + +Optional properties: +- enable-gpios: GPIO pin to enable or disable the panel +- backlight: phandle of the backlight device attached to the panel + +Example: + panel_edp: panel-edp { + compatible = "innolux,tv123wam"; + enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>; + power-supply = <&pm8916_l2>; + backlight = <&backlight>; + };
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