clean up DPU custom properties

index 52a026d..b73112a 100644
@@ -137,32 +137,6 @@ enum msm_mdp_crtc_property {
 	CRTC_PROP_COUNT
 };
 
-enum msm_mdp_conn_property {
-	/* blob properties, always put these first */
-	CONNECTOR_PROP_DPU_INFO,
-	CONNECTOR_PROP_HDR_INFO,
-	CONNECTOR_PROP_PP_DITHER,
-
-	/* # of blob properties */
-	CONNECTOR_PROP_BLOBCOUNT,
-
-	/* range properties */
-	CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
-	CONNECTOR_PROP_DST_X,
-	CONNECTOR_PROP_DST_Y,
-	CONNECTOR_PROP_DST_W,
-	CONNECTOR_PROP_DST_H,
-	CONNECTOR_PROP_BL_SCALE,
-	CONNECTOR_PROP_AD_BL_SCALE,
-
-	/* enum/bitmask properties */
-	CONNECTOR_PROP_AUTOREFRESH,
-	CONNECTOR_PROP_LP,
-
-	/* total # of properties */
-	CONNECTOR_PROP_COUNT
-};
-
 struct msm_vblank_ctrl {
 	struct kthread_work work;
 	struct list_head event_list;

@@ -428,7 +402,6 @@ struct msm_drm_private {
 	/* Properties */
 	struct drm_property *plane_property[PLANE_PROP_COUNT];
 	struct drm_property *crtc_property[CRTC_PROP_COUNT];
-	struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
 
 	/* Color processing properties for the crtc */
 	struct drm_property **cp_property;

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index 678bf12..763dd0c 100644
@@ -20,6 +20,7 @@
 #define _DPU_CRTC_H_
 
 #include <linux/kthread.h>
+#include <uapi/drm/dpu_drm.h>
 #include <drm/drm_crtc.h>
 #include "msm_prop.h"
 #include "dpu_kms.h"

@@ -86,7 +87,6 @@ struct dpu_crtc_smmu_state_data {
  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
  * @hw_lm:	LM HW Driver context
  * @hw_ctl:	CTL Path HW driver context
- * @hw_dspp:	DSPP HW driver context
  * @hw_ds:	DS HW driver context
  * @encoder:	Encoder attached to this lm & ctl
  * @mixer_op_mode:	mixer blending operation mode

@@ -95,7 +95,6 @@ struct dpu_crtc_smmu_state_data {
 struct dpu_crtc_mixer {
 	struct dpu_hw_mixer *hw_lm;
 	struct dpu_hw_ctl *hw_ctl;
-	struct dpu_hw_dspp *hw_dspp;
 	struct dpu_hw_ds *hw_ds;
 	struct drm_encoder *encoder;
 	u32 mixer_op_mode;

index 823e9d2..713540e 100644
@@ -1738,8 +1738,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
 
 		if (phys->split_role != ENC_ROLE_SLAVE)
 			set_bit(i, dpu_enc->frame_busy_mask);
-		if (phys->hw_ctl->ops.reg_dma_flush)
-			phys->hw_ctl->ops.reg_dma_flush(phys->hw_ctl);
 		if (!phys->ops.needs_single_flush ||
 				!phys->ops.needs_single_flush(phys))
 			_dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);

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index acfda2a..ffea915 100644
@@ -567,6 +567,9 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
 	ddev->mode_config.funcs = &mode_config_funcs;
 	ddev->mode_config.helper_private = &mode_config_helper_funcs;
 
+	/* Enable normalization of plane zpos */
+	ddev->mode_config.normalize_zpos = true;
+
 	if (kms) {
 		ret = kms->funcs->hw_init(kms);
 		if (ret) {

index 85c0229..7eafca3 100644
@@ -102,34 +102,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
 	dpu_cstate = to_dpu_crtc_state(state);
 	memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-	perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-		dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-	perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-		dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-
-	if (dpu_cstate->bw_split_vote) {
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_IB);
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_IB);
-	} else {
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-		perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-		perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-	}
-
-	perf->core_clk_rate =
-			dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_CLK);
-
 	if (!dpu_cstate->bw_control) {
 		for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
 			perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *

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index 763dd0c..f100e07 100644
@@ -26,7 +26,6 @@
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
 #include "dpu_hw_blk.h"
-#include "dpu_hw_ds.h"
 
 #define DPU_CRTC_NAME_SIZE	12
 

@@ -87,7 +86,6 @@ struct dpu_crtc_smmu_state_data {
  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
  * @hw_lm:	LM HW Driver context
  * @hw_ctl:	CTL Path HW driver context
- * @hw_ds:	DS HW driver context
  * @encoder:	Encoder attached to this lm & ctl
  * @mixer_op_mode:	mixer blending operation mode
  * @flush_mask:	mixer flush mask for ctl, mixer and pipe

@@ -95,7 +93,6 @@ struct dpu_crtc_smmu_state_data {
 struct dpu_crtc_mixer {
 	struct dpu_hw_mixer *hw_lm;
 	struct dpu_hw_ctl *hw_ctl;
-	struct dpu_hw_ds *hw_ds;
 	struct drm_encoder *encoder;
 	u32 mixer_op_mode;
 	u32 flush_mask;

@@ -316,12 +313,6 @@ struct dpu_crtc_respool {
  * @property_state: Local storage for msm_prop properties
  * @property_values: Current crtc property values
  * @input_fence_timeout_ns : Cached input fence timeout, in ns
- * @num_dim_layers: Number of dim layers
- * @dim_layer: Dim layer configs
- * @num_ds: Number of destination scalers to be configured
- * @num_ds_enabled: Number of destination scalers enabled
- * @ds_dirty: Boolean to indicate if dirty or not
- * @ds_cfg: Destination scaler config
  * @new_perf: new performance state being requested
  */
 struct dpu_crtc_state {

@@ -338,12 +329,6 @@ struct dpu_crtc_state {
 	struct msm_property_state property_state;
 	struct msm_property_value property_values[CRTC_PROP_COUNT];
 	uint64_t input_fence_timeout_ns;
-	uint32_t num_dim_layers;
-	struct dpu_hw_dim_layer dim_layer[DPU_MAX_DIM_LAYERS];
-	uint32_t num_ds;
-	uint32_t num_ds_enabled;
-	bool ds_dirty;
-	struct dpu_hw_ds_cfg ds_cfg[DPU_MAX_DS_COUNT];
 
 	struct dpu_core_perf_params new_perf;
 	struct dpu_crtc_respool rp;

@@ -364,7 +349,6 @@ struct dpu_crtc_state {
 /**
  * dpu_crtc_get_mixer_width - get the mixer width
  * Mixer width will be same as panel width(/2 for split)
- * unless destination scaler feature is enabled
  */
 static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
 	struct dpu_crtc_state *cstate, struct drm_display_mode *mode)

@@ -374,10 +358,7 @@ static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
 	if (!dpu_crtc || !cstate || !mode)
 		return 0;
 
-	if (cstate->num_ds_enabled)
-		mixer_width = cstate->ds_cfg[0].lm_width;
-	else
-		mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
+	mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
 			mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
 
 	return mixer_width;

@@ -385,8 +366,7 @@ static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
 
 /**
  * dpu_crtc_get_mixer_height - get the mixer height
- * Mixer height will be same as panel height unless
- * destination scaler feature is enabled
+ * Mixer height will be same as panel height
  */
 static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc,
 		struct dpu_crtc_state *cstate, struct drm_display_mode *mode)

@@ -394,8 +374,7 @@ static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc,
 	if (!dpu_crtc || !cstate || !mode)
 		return 0;
 
-	return (cstate->num_ds_enabled ?
-			cstate->ds_cfg[0].lm_height : mode->vdisplay);
+	return mode->vdisplay;
 }
 
 /**

index 713540e..7dd609c 100644
@@ -229,18 +229,6 @@ struct dpu_encoder_virt {
 };
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
-
-void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, u32 idle_timeout)
-{
-	struct dpu_encoder_virt *dpu_enc;
-
-	if (!drm_enc)
-		return;
-
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
-	dpu_enc->idle_timeout = idle_timeout;
-}
-
 static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc,
 								bool enable)
 {

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index ef22c86..e29e5da 100644
@@ -67,20 +67,6 @@ struct dpu_hw_lm_ops {
 	void (*setup_gc)(struct dpu_hw_mixer *mixer,
 			void *cfg);
 
-	/**
-	 * setup_dim_layer: configure dim layer settings
-	 * @ctx: Pointer to layer mixer context
-	 * @dim_layer: dim layer configs
-	 */
-	void (*setup_dim_layer)(struct dpu_hw_mixer *ctx,
-			struct dpu_hw_dim_layer *dim_layer);
-
-	/**
-	 * clear_dim_layer: clear dim layer settings
-	 * @ctx: Pointer to layer mixer context
-	 */
-	void (*clear_dim_layer)(struct dpu_hw_mixer *ctx);
-
 	/* setup_misr: enables/disables MISR in HW register */
 	void (*setup_misr)(struct dpu_hw_mixer *ctx,
 			bool enable, u32 frame_count);

index fcd164f..836ff9e 100644
@@ -99,7 +99,6 @@ enum dpu_hw_blk_type {
 	DPU_HW_BLK_TOP = 0,
 	DPU_HW_BLK_SSPP,
 	DPU_HW_BLK_LM,
-	DPU_HW_BLK_DS,
 	DPU_HW_BLK_CTL,
 	DPU_HW_BLK_CDM,
 	DPU_HW_BLK_PINGPONG,

@@ -469,20 +468,5 @@ struct dpu_mdss_color {
 #define DPU_DBG_MASK_TOP      (1 << 8)
 #define DPU_DBG_MASK_VBIF     (1 << 9)
 #define DPU_DBG_MASK_ROT      (1 << 10)
-#define DPU_DBG_MASK_DS       (1 << 11)
-
-/**
- * struct dpu_hw_dim_layer: dim layer configs
- * @flags: Flag to represent INCLUSIVE/EXCLUSIVE
- * @stage: Blending stage of dim layer
- * @color_fill: Color fill to be used for the layer
- * @rect: Dim layer coordinates
- */
-struct dpu_hw_dim_layer {
-	uint32_t flags;
-	uint32_t stage;
-	struct dpu_mdss_color color_fill;
-	struct dpu_rect rect;
-};
 
 #endif  /* _DPU_HW_MDSS_H */

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index 5770ac0..904499a 100644
@@ -86,25 +86,10 @@ enum msm_mdp_plane_property {
 
 enum msm_mdp_crtc_property {
 	CRTC_PROP_INFO,
-	CRTC_PROP_DEST_SCALER_LUT_ED,
-	CRTC_PROP_DEST_SCALER_LUT_CIR,
-	CRTC_PROP_DEST_SCALER_LUT_SEP,
 
 	/* # of blob properties */
 	CRTC_PROP_BLOBCOUNT,
 
-	/* range properties */
-	CRTC_PROP_DIM_LAYER_V1 = CRTC_PROP_BLOBCOUNT,
-	CRTC_PROP_CORE_CLK,
-	CRTC_PROP_CORE_AB,
-	CRTC_PROP_CORE_IB,
-	CRTC_PROP_LLCC_AB,
-	CRTC_PROP_LLCC_IB,
-	CRTC_PROP_DRAM_AB,
-	CRTC_PROP_DRAM_IB,
-	CRTC_PROP_IDLE_TIMEOUT,
-	CRTC_PROP_DEST_SCALER,
-
 	/* total # of properties */
 	CRTC_PROP_COUNT
 };

index 7eafca3..6c0f66c 100644
@@ -19,8 +19,6 @@
 #include <linux/clk.h>
 #include <linux/bitmap.h>
 
-#include "msm_prop.h"
-
 #include "dpu_kms.h"
 #include "dpu_trace.h"
 #include "dpu_crtc.h"

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index f100e07..cc23b33 100644
@@ -22,7 +22,6 @@
 #include <linux/kthread.h>
 #include <uapi/drm/dpu_drm.h>
 #include <drm/drm_crtc.h>
-#include "msm_prop.h"
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
 #include "dpu_hw_blk.h"

@@ -201,10 +200,6 @@ struct dpu_crtc {
 	struct drm_pending_vblank_event *event;
 	u32 vsync_count;
 
-	struct msm_property_info property_info;
-	struct msm_property_data property_data[CRTC_PROP_COUNT];
-	struct drm_property_blob *blob_info;
-
 	struct dpu_hw_stage_cfg stage_cfg;
 	struct dentry *debugfs_root;
 

@@ -326,8 +321,6 @@ struct dpu_crtc_state {
 	bool is_ppsplit;
 	struct dpu_rect lm_bounds[CRTC_DUAL_MIXERS];
 
-	struct msm_property_state property_state;
-	struct msm_property_value property_values[CRTC_PROP_COUNT];
 	uint64_t input_fence_timeout_ns;
 
 	struct dpu_core_perf_params new_perf;

@@ -338,15 +331,6 @@ struct dpu_crtc_state {
 	container_of(x, struct dpu_crtc_state, base)
 
 /**
- * dpu_crtc_get_property - query integer value of crtc property
- * @S: Pointer to crtc state
- * @X: Property index, from enum msm_mdp_crtc_property
- * Returns: Integer value of requested property
- */
-#define dpu_crtc_get_property(S, X) \
-	((S) && ((X) < CRTC_PROP_COUNT) ? ((S)->property_values[(X)].value) : 0)
-
-/**
  * dpu_crtc_get_mixer_width - get the mixer width
  * Mixer width will be same as panel width(/2 for split)
  */

index 3dbfd8b..ce92901 100644
@@ -20,8 +20,6 @@
 #define __DPU_ENCODER_H__
 
 #include <drm/drm_crtc.h>
-
-#include "msm_prop.h"
 #include "dpu_hw_mdss.h"
 
 #define DPU_ENCODER_FRAME_EVENT_DONE			BIT(0)

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index a06c8b4..f6fe6dd 100644
@@ -21,7 +21,6 @@
 
 #include <drm/drm_crtc.h>
 
-#include "msm_prop.h"
 #include "dpu_kms.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_sspp.h"

@@ -44,8 +43,6 @@
  */
 struct dpu_plane_state {
 	struct drm_plane_state base;
-	struct msm_property_state property_state;
-	struct msm_property_value property_values[PLANE_PROP_COUNT];
 	struct msm_gem_address_space *aspace;
 	void *input_fence;
 	enum dpu_stage stage;

@@ -74,15 +71,6 @@ struct dpu_multirect_plane_states {
 	container_of(x, struct dpu_plane_state, base)
 
 /**
- * dpu_plane_get_property - Query integer value of plane property
- * @S: Pointer to plane state
- * @X: Property index, from enum msm_mdp_plane_property
- * Returns: Integer value of requested property
- */
-#define dpu_plane_get_property(S, X) ((S) && ((X) < PLANE_PROP_COUNT) ? \
-	((S)->property_values[(X)].value) : 0)
-
-/**
  * dpu_plane_pipe - return sspp identifier for the given plane
  * @plane:   Pointer to DRM plane object
  * Returns: sspp identifier of the given plane

index 904499a..1affc7f 100644
@@ -74,26 +74,13 @@ struct msm_file_private {
 };
 
 enum msm_mdp_plane_property {
-	/* # of blob properties */
-	PLANE_PROP_BLOBCOUNT,
-
 	/* range properties */
-	PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT,
+	PLANE_PROP_ZPOS,
 
 	/* total # of properties */
 	PLANE_PROP_COUNT
 };
 
-enum msm_mdp_crtc_property {
-	CRTC_PROP_INFO,
-
-	/* # of blob properties */
-	CRTC_PROP_BLOBCOUNT,
-
-	/* total # of properties */
-	CRTC_PROP_COUNT
-};
-
 struct msm_vblank_ctrl {
 	struct kthread_work work;
 	struct list_head event_list;

@@ -358,7 +345,6 @@ struct msm_drm_private {
 
 	/* Properties */
 	struct drm_property *plane_property[PLANE_PROP_COUNT];
-	struct drm_property *crtc_property[CRTC_PROP_COUNT];
 
 	/* Color processing properties for the crtc */
 	struct drm_property **cp_property;

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index 7cf5a7a..a7d9aff 100644
@@ -2583,24 +2583,6 @@ struct plane_state {
 	u32 pipe_id;
 };
 
-static int pstate_cmp(const void *a, const void *b)
-{
-	struct plane_state *pa = (struct plane_state *)a;
-	struct plane_state *pb = (struct plane_state *)b;
-	int rc = 0;
-	int pa_zpos, pb_zpos;
-
-	pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS);
-	pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS);
-
-	if (pa_zpos != pb_zpos)
-		rc = pa_zpos - pb_zpos;
-	else
-		rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
-
-	return rc;
-}
-
 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {

@@ -2666,8 +2648,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 		pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
 		pstates[cnt].drm_pstate = pstate;
-		pstates[cnt].stage = dpu_plane_get_property(
-				pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS);
+		pstates[cnt].stage = pstate->normalized_zpos;
 		pstates[cnt].pipe_id = dpu_plane_pipe(plane);
 
 		/* check dim layer stage with every plane */

@@ -2723,21 +2704,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		}
 	}
 
-	/* assign mixer stages based on sorted zpos property */
-	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
-
-	if (!dpu_is_custom_client()) {
-		int stage_old = pstates[0].stage;
-
-		z_pos = 0;
-		for (i = 0; i < cnt; i++) {
-			if (stage_old != pstates[i].stage)
-				++z_pos;
-			stage_old = pstates[i].stage;
-			pstates[i].stage = z_pos;
-		}
-	}
-
 	z_pos = -1;
 	for (i = 0; i < cnt; i++) {
 		/* reset counts at every new blend stage */

index e81cb1f..c6be158 100644
@@ -59,6 +59,7 @@
 #define DPU_NAME_SIZE  12
 
 #define DPU_PLANE_COLOR_FILL_FLAG	BIT(31)
+#define DPU_ZPOS_MAX 255
 
 /* multirect rect index */
 enum {

@@ -1516,9 +1517,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,
 		/* reserve zpos == 0 for primary planes */
 		zpos_def = drm_plane_index(plane) + 1;
 	}
-
-	msm_property_install_range(&pdpu->property_info, "zpos",
-		0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
 }
 
 static int dpu_plane_atomic_set_property(struct drm_plane *plane,

@@ -1956,6 +1954,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	struct msm_drm_private *priv;
 	struct dpu_kms *kms;
 	enum drm_plane_type type;
+	int zpos_max = DPU_ZPOS_MAX;
 	int ret = -EINVAL;
 
 	if (!dev) {

@@ -2049,6 +2048,17 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 
 	pdpu->catalog = kms->catalog;
 
+	if (kms->catalog->mixer_count &&
+		kms->catalog->mixer[0].sblk->maxblendstages) {
+		zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
+		if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
+			zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
+	}
+
+	ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
+	if (ret)
+		DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
+
 	/* success! finalize initialization */
 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
 

index cc23b33..39def93 100644
@@ -20,7 +20,6 @@
 #define _DPU_CRTC_H_
 
 #include <linux/kthread.h>
-#include <uapi/drm/dpu_drm.h>
 #include <drm/drm_crtc.h>
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"

index 830b69e..5b4d529 100644
@@ -10,7 +10,6 @@
  * GNU General Public License for more details.
  */
 
-#include <uapi/drm/dpu_drm.h>
 #include "dpu_kms.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_hwio.h"

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