common/memsize.c: Increase save array for supporting memory size > 4GB

PATCH New tien.fong.chee at intel.com 4 participants 8 messages Jun 20, 2018 – Jul 11, 2018

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tien.fong.chee at intel.com

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2018-06-20 07:06 UTC #0 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

From: Tien Fong Chee <[email protected]>

In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger memory.

Signed-off-by Tien Fong Chee <[email protected]>

---

Changes in v2:
- Change save array size to save[BITS_PER_LONG - 1]

---
 common/memsize.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

common/memsize.c +1 -1

index 5670e95..13b0047 100644
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
 long get_ram_size(long *base, long maxsize)
 {
 	volatile long *addr;
-	long           save[31];
+	long           save[BITS_PER_LONG - 1];
 	long           save_base;
 	long           cnt;
 	long           val;

Signature · 1 line

2.2.0

Marek Vasut

2018-06-21 04:34 UTC #1 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

Quoted 20 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>
In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger memory.
Signed-off-by Tien Fong Chee <[email protected]>
---
Changes in v2:
- Change save array size to save[BITS_PER_LONG - 1]
---
 common/memsize.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
common/memsize.c +0 -0
index 5670e95..13b0047 100644

common/memsize.c DECLARE_GLOBAL_DATA_PTR; · line 32

Quoted 8 lines

common/memsize.c +1 -1

@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
 long get_ram_size(long *base, long maxsize)
 {
 	volatile long *addr;
-	long           save[31];
+	long           save[BITS_PER_LONG - 1];
 	long           save_base;
 	long           cnt;
 	long           val;

Does this work with LPAE systems, where bits per long == 32 and the address space is bigger ? Or with similar setups ? I mean, you can have

Quoted 1 line

4 GiB of RAM on 32bit system ...

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2018-06-21 06:31 UTC #2 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

Quoted 26 lines · Marek Vasut

Quoted 25 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger memory.
Signed-off-by Tien Fong Chee <[email protected]>
---
Changes in v2:
- Change save array size to save[BITS_PER_LONG - 1]
---
common/memsize.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
common/memsize.c +0 -1
index 5670e95..13b0047 100644
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
  long get_ram_size(long *base, long maxsize)
  {
  	volatile long *addr;
-	long           save[31];

Quoted 10 lines

common/memsize.c DECLARE_GLOBAL_DATA_PTR; · line 32
Quoted 5 lines
common/memsize.c +1 -0
+	long           save[BITS_PER_LONG - 1];
  	long           save_base;
  	long           cnt;
  	long           val;
Does this work with LPAE systems, where bits per long == 32 and the address space is bigger ? Or with similar setups ? I mean, you can have
Quoted 2 lines
4 GiB of RAM on 32bit system ...

This function is designed to work with 32bit or 64 bits system, for example the argument such as maxsize can be 32bit or 64 bit, if value larger than 4GiB is passed as maxsize argument with 32bit system, the whole thing will go wrong.

Marek Vasut

2018-06-23 03:29 UTC #3 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

Quoted 36 lines · Tien Fong

Quoted 35 lines · Marek Vasut
Quoted 22 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger memory.
Signed-off-by Tien Fong Chee <[email protected]>
---
Changes in v2:
- Change save array size to save[BITS_PER_LONG - 1]
---
common/memsize.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
common/memsize.c +0 -0
index 5670e95..13b0047 100644
common/memsize.c DECLARE_GLOBAL_DATA_PTR; · line 32
Quoted 8 lines
common/memsize.c +1 -1
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
  long get_ram_size(long *base, long maxsize)
  {
  	volatile long *addr;
-	long           save[31];
+	long           save[BITS_PER_LONG - 1];
  	long           save_base;
  	long           cnt;
  	long           val;
Does this work with LPAE systems, where bits per long == 32 and the address space is bigger ? Or with similar setups ? I mean, you can have
Quoted 1 line

Quoted 5 lines

Quoted 1 line
Quoted 1 line
4 GiB of RAM on 32bit system ...
This function is designed to work with 32bit or 64 bits system, for example the argument such as maxsize can be 32bit or 64 bit, if value larger than 4GiB is passed as maxsize argument with 32bit system, the whole thing will go wrong.

And what do you do when you identify a problem in mainline ? :-)

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2018-07-02 13:51 UTC #4 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

Quoted 44 lines · Marek Vasut

Quoted 43 lines · Tien Fong
Quoted 41 lines · Marek Vasut
Quoted 24 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger
memory.
Signed-off-by Tien Fong Chee <[email protected]>
---
Changes in v2:
- Change save array size to save[BITS_PER_LONG - 1]
---
common/memsize.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
common/memsize.c +0 -0
index 5670e95..13b0047 100644
common/memsize.c DECLARE_GLOBAL_DATA_PTR; · line 32
Quoted 8 lines
common/memsize.c +1 -1
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
  long get_ram_size(long *base, long maxsize)
  {
  	volatile long *addr;
-	long           save[31];
+	long           save[BITS_PER_LONG - 1];
  	long           save_base;
  	long           cnt;
  	long           val;
Does this work with LPAE systems, where bits per long == 32 and the
address space is bigger ? Or with similar setups ? I mean, you can
have
Quoted 2 lines

Quoted 9 lines

Quoted 7 lines
Quoted 1 line
Quoted 1 line
4 GiB of RAM on 32bit system ...
This function is designed to work with 32bit or 64 bits system, for example the argument such as maxsize can be 32bit or 64 bit, if value
larger than 4GiB is passed as maxsize argument with 32bit system, the
whole thing will go wrong.
And what do you do when you identify a problem in mainline ? :-)

I have no idea at this moment, how about fixing the issue for save array in 64-bit 1st?

Tom Rini

2018-07-11 12:42 UTC #5 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

In reply to tien.fong.chee at intel.com

Quoted 6 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>
In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger memory.
Signed-off-by Tien Fong Chee <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Marek Vasut

2018-07-11 12:48 UTC #6 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

Quoted 10 lines · Tom Rini

Quoted 6 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger memory.
Signed-off-by Tien Fong Chee <[email protected]>
Applied to u-boot/master, thanks!

There were review comments on this patch which were not addressed, please drop.

Signature · 2 lines

Best regards,
Marek Vasut

Tom Rini

2018-07-11 12:50 UTC #7 lore raw

PATCH v2 1/1 common/memsize.c: Increase save array for supporting memory size > 4GB

Quoted 8 lines · Marek Vasut

Quoted 7 lines · Tom Rini
Quoted 5 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
In ARM 64-bits, memory size can be supported is more than 4GB, hence increasing save array is needed to cope with testing larger memory.

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Signed-off-by Tien Fong Chee <[email protected]>
Applied to u-boot/master, thanks!
There were review comments on this patch which were not addressed, please drop.

I thought I had put them in my message here, sorry. I agree with Tien that we should fix the issue we have now and address the enhancement in a follow up patch.

Signature · 8 lines

Tom
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