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add Mali-450 support to MT7623 SoC

PATCH Applied [email protected] 4 participants 17 messages Apr 27, 2018 – Jul 16, 2018

Subsystems (6)
Device tree bindings DRM drivers DRM misc Arm MediaTek +2 more subsystems
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#0 lore raw

v2 cover add Mali-450 support to MT7623 SoC

From: Sean Wang <[email protected]>

v2:
changes from v1 to v2:
- Add Reviewed-by tag from v1 result
- Split out the changes for dt-bindings .h from the changes for driver
- Fix up the typo in g3dsys dt-bindings documentation
v1:

Hi,

The series adds a required resource setup to allow Mali-450 to work on MT7623. This also can benefits other MediaTek SoCs having Mali-450 device.

In order to prove the setup is proper, I also have added mediatek port to linux-lima at [1] and make a few of tests along with off-screen rendering [2][3][4][5][6][7] through mesa-lima [8]. All work correctly.

[1] https://github.com/objelf/linux-lima/tree/mediatek-lima-4.16-rc5
[2] simple triangle: https://github.com/yuq/gfx/tree/master/gbm-surface
[3] vertex shader uniform: https://github.com/yuq/gfx/tree/master/gbm-surface-move
[4] multi varying: https://github.com/yuq/gfx/tree/master/gbm-surface-color
[5] multi draw: https://github.com/yuq/gfx/tree/master/gbm-surface-draw
[6] FBO: https://github.com/yuq/gfx/tree/master/gbm-surface-fbo
[7] kmscube: https://github.com/yuq/kmscube
[8] https://github.com/yuq/mesa-lima

Hope these patches can help people working on BPI-R2.

Sean

Sean Wang (6):
dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible
dt-bindings: clock: mediatek: add g3dsys bindings
dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
clk: mediatek: add g3dsys support for MT2701 and MT7623
arm: dts: mt7623: add Mali-450 and related device nodes

 .../bindings/arm/mediatek/mediatek,g3dsys.txt      | 30 +++++++
 .../devicetree/bindings/gpu/arm,mali-utgard.txt    |  9 ++
 arch/arm/boot/dts/mt7623.dtsi                      | 70 ++++++++++++++++
 arch/arm/boot/dts/mt7623a.dtsi                     |  4 +
 drivers/clk/mediatek/Kconfig                       |  6 ++
 drivers/clk/mediatek/Makefile                      |  1 +
 drivers/clk/mediatek/clk-mt2701-g3d.c              | 95 ++++++++++++++++++++++
 include/dt-bindings/clock/mt2701-clk.h             |  4 +
 include/dt-bindings/reset/mt2701-resets.h          |  3 +
 9 files changed, 222 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
 create mode 100644 drivers/clk/mediatek/clk-mt2701-g3d.c
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH v2 1/6 dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible

From: Sean Wang <[email protected]>

The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it and define its own vendor-specific properties.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Sean Wang <[email protected]>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++
 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +9 -0
index 99d1c0a..656068f 100644
@@ -19,6 +19,7 @@ Required properties:
       + rockchip,rk3228-mali
       + rockchip,rk3328-mali
       + stericsson,db8500-mali
+      + mediatek,mt7623-mali
 
   - reg: Physical base address and length of the GPU registers
 

@@ -89,6 +90,14 @@ to specify one more vendor-specific compatible, among:
       * interrupt-names and interrupts:
         + combined: combined interrupt of all of the above lines
 
+  - mediatek,mt7623-mali
+     Required properties:
+      * resets: phandle to the reset line for the GPU
+      * mediatek,larb: phandle pointed to the local arbiter used to control the
+	access to external memory on the SoC.
+	see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+	for details
+
 Example:
 
 mali: gpu at 1c40000 {
Signature · 1 line
2.7.4
maintainer
#2 lore raw

Re: [PATCH v2 1/6] dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible

Quoted 8 lines · sean.wang at mediatek.com

From: Sean Wang <[email protected]>

The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it and define its own vendor-specific properties.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Sean Wang <[email protected]>

---

Hi Rob,

Any comments regarding this patch?

Regards,
Matthias

Quoted 31 lines
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++
 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +9 -0
index 99d1c0a..656068f 100644
@@ -19,6 +19,7 @@ Required properties:
       + rockchip,rk3228-mali
       + rockchip,rk3328-mali
       + stericsson,db8500-mali
+      + mediatek,mt7623-mali
 
   - reg: Physical base address and length of the GPU registers
 

@@ -89,6 +90,14 @@ to specify one more vendor-specific compatible, among:
       * interrupt-names and interrupts:
         + combined: combined interrupt of all of the above lines
 
+  - mediatek,mt7623-mali
+     Required properties:
+      * resets: phandle to the reset line for the GPU
+      * mediatek,larb: phandle pointed to the local arbiter used to control the
+	access to external memory on the SoC.
+	see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+	for details
+
 Example:
 
 mali: gpu at 1c40000 {
author
#3 lore raw

Re: [PATCH v2 1/6] dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible

Quoted 11 lines · Matthias Brugger
Quoted 8 lines · sean.wang at mediatek.com

From: Sean Wang <[email protected]>

The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it and define its own vendor-specific properties.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Sean Wang <[email protected]>

---

Quoted 7 lines

Hi Rob,

Any comments regarding this patch?

Regards,
Matthias

Hi, Matthias

I've already got a Reviewed-by tag from Rob.

Is it possible that this patch go through your tree ?

Sean

Quoted 31 lines
Quoted 31 lines
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++
 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +9 -0
index 99d1c0a..656068f 100644
@@ -19,6 +19,7 @@ Required properties:
       + rockchip,rk3228-mali
       + rockchip,rk3328-mali
       + stericsson,db8500-mali
+      + mediatek,mt7623-mali
 
   - reg: Physical base address and length of the GPU registers
 

@@ -89,6 +90,14 @@ to specify one more vendor-specific compatible, among:
       * interrupt-names and interrupts:
         + combined: combined interrupt of all of the above lines
 
+  - mediatek,mt7623-mali
+     Required properties:
+      * resets: phandle to the reset line for the GPU
+      * mediatek,larb: phandle pointed to the local arbiter used to control the
+	access to external memory on the SoC.
+	see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+	for details
+
 Example:
 
 mali: gpu at 1c40000 {
maintainer
#4 lore raw

Re: [PATCH v2 1/6] dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible

Quoted 20 lines · Sean Wang
Quoted 11 lines · Matthias Brugger
Quoted 8 lines · sean.wang at mediatek.com

From: Sean Wang <[email protected]>

The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it and define its own vendor-specific properties.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Sean Wang <[email protected]>

---

Quoted 7 lines

Hi Rob,

Any comments regarding this patch?

Regards,
Matthias

Quoted 6 lines

Hi, Matthias

I've already got a Reviewed-by tag from Rob.

Is it possible that this patch go through your tree ?

Basically yes, I just want to get the mmsys problem fixed first. Sorry I know it is on my plate. I'll try to send a new version this week.

Regards,
Matthias

Quoted 35 lines

Sean

Quoted 31 lines
Quoted 31 lines
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++
 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +9 -0
index 99d1c0a..656068f 100644
@@ -19,6 +19,7 @@ Required properties:
       + rockchip,rk3228-mali
       + rockchip,rk3328-mali
       + stericsson,db8500-mali
+      + mediatek,mt7623-mali
 
   - reg: Physical base address and length of the GPU registers
 

@@ -89,6 +90,14 @@ to specify one more vendor-specific compatible, among:
       * interrupt-names and interrupts:
         + combined: combined interrupt of all of the above lines
 
+  - mediatek,mt7623-mali
+     Required properties:
+      * resets: phandle to the reset line for the GPU
+      * mediatek,larb: phandle pointed to the local arbiter used to control the
+	access to external memory on the SoC.
+	see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+	for details
+
 Example:
 
 mali: gpu at 1c40000 {
author
#5 lore raw

PATCH v2 2/6 dt-bindings: clock: mediatek: add g3dsys bindings

In reply to [email protected]

From: Sean Wang <[email protected]>

Add bindings to g3dsys providing necessary clock and reset control to Mali-450.

Signed-off-by Sean Wang <[email protected]>
---
 .../bindings/arm/mediatek/mediatek,g3dsys.txt      | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt new file +30 -0
new file mode 100644
index 0000000..7de43bf
@@ -0,0 +1,30 @@
+MediaTek g3dsys controller
+============================
+
+The MediaTek g3dsys controller provides various clocks and reset controller to
+the GPU.
+
+Required Properties:
+
+- compatible: Should be:
+	- "mediatek,mt2701-g3dsys", "syscon":
+		for MT2701 SoC
+	- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
+		for MT7623 SoC
+- #clock-cells: Must be 1
+- #reset-cells: Must be 1
+
+The g3dsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+g3dsys: clock-controller at 13000000 {
+	compatible = "mediatek,mt7623-g3dsys",
+		     "mediatek,mt2701-g3dsys",
+		     "syscon";
+	reg = <0 0x13000000 0 0x200>;
+	#clock-cells = <1>;
+	#reset-cells = <1>;
+};
Signature · 1 line
2.7.4
maintainer Reviewed-by on v2 2/6
#6 lore raw

Re: [PATCH v2 2/6] dt-bindings: clock: mediatek: add g3dsys bindings

Quoted 10 lines · sean.wang at mediatek.com

From: Sean Wang <[email protected]>

Add bindings to g3dsys providing necessary clock and reset control to Mali-450.

Signed-off-by Sean Wang <[email protected]>
---
 .../bindings/arm/mediatek/mediatek,g3dsys.txt      | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
Reviewed-by Rob Herring <[email protected]>
author
#8 lore raw

PATCH v2 3/6 dt-bindings: clock: mediatek: add entry for Mali-450 node to refer

In reply to [email protected]

From: Sean Wang <[email protected]>

Just add binding for a required clock referenced by Mali-450 on MT7623 or MT2701 SoC.

Cc devicetree at vger.kernel.org
Signed-off-by Sean Wang <[email protected]>
---
 include/dt-bindings/clock/mt2701-clk.h | 4 ++++
 1 file changed, 4 insertions(+)
include/dt-bindings/clock/mt2701-clk.h +4 -0
index 24e93df..2ac62a6 100644
@@ -431,6 +431,10 @@
 #define CLK_ETHSYS_CRYPTO			8
 #define CLK_ETHSYS_NR				9
 
+/* G3DSYS */
+#define CLK_G3DSYS_CORE				1
+#define CLK_G3DSYS_NR				2
+
 /* BDP */
 
 #define CLK_BDP_BRG_BA				1
Signature · 1 line
2.7.4
maintainer Reviewed-by on v2 3/6
#9 lore raw

Re: [PATCH v2 3/6] dt-bindings: clock: mediatek: add entry for Mali-450 node to refer

Quoted 10 lines · sean.wang at mediatek.com

From: Sean Wang <[email protected]>

Just add binding for a required clock referenced by Mali-450 on MT7623 or MT2701 SoC.

Cc devicetree at vger.kernel.org
Signed-off-by Sean Wang <[email protected]>
---
 include/dt-bindings/clock/mt2701-clk.h | 4 ++++
 1 file changed, 4 insertions(+)
Reviewed-by Rob Herring <[email protected]>
author
#11 lore raw

PATCH v2 4/6 dt-bindings: reset: mediatek: add entry for Mali-450 node to refer

In reply to [email protected]

From: Sean Wang <[email protected]>

Just add binding for a required reset referenced by Mali-450 on MT7623 or MT2701 SoC.

Cc devicetree at vger.kernel.org
Signed-off-by Sean Wang <[email protected]>
---
 include/dt-bindings/reset/mt2701-resets.h | 3 +++
 1 file changed, 3 insertions(+)
include/dt-bindings/reset/mt2701-resets.h +3 -0
index 21deb54..50b7f06 100644
@@ -87,4 +87,7 @@
 #define MT2701_ETHSYS_GMAC_RST			23
 #define MT2701_ETHSYS_PPE_RST			31
 
+/* G3DSYS resets */
+#define MT2701_G3DSYS_CORE_RST			0
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
Signature · 1 line
2.7.4
maintainer Reviewed-by on v2 4/6
#12 lore raw

Re: [PATCH v2 4/6] dt-bindings: reset: mediatek: add entry for Mali-450 node to refer

Quoted 10 lines · sean.wang at mediatek.com

From: Sean Wang <[email protected]>

Just add binding for a required reset referenced by Mali-450 on MT7623 or MT2701 SoC.

Cc devicetree at vger.kernel.org
Signed-off-by Sean Wang <[email protected]>
---
 include/dt-bindings/reset/mt2701-resets.h | 3 +++
 1 file changed, 3 insertions(+)
Reviewed-by Rob Herring <[email protected]>
author
#14 lore raw

PATCH v2 5/6 clk: mediatek: add g3dsys support for MT2701 and MT7623

In reply to [email protected]

From: Sean Wang <[email protected]>

Add clock driver support for g3dsys on MT2701 and MT7623, which is providing essential clock gate and reset controller to Mali-450.

Signed-off-by Sean Wang <[email protected]>
---
 drivers/clk/mediatek/Kconfig          |  6 +++
 drivers/clk/mediatek/Makefile         |  1 +
 drivers/clk/mediatek/clk-mt2701-g3d.c | 95 +++++++++++++++++++++++++++++++++++
 3 files changed, 102 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-g3d.c
drivers/clk/mediatek/Kconfig +6 -0
index 92afe59..3dd1dab 100644
@@ -60,6 +60,12 @@ config COMMON_CLK_MT2701_AUDSYS
 	---help---
 	  This driver supports Mediatek MT2701 audsys clocks.
 
+config COMMON_CLK_MT2701_G3DSYS
+	bool "Clock driver for MediaTek MT2701 g3dsys"
+	depends on COMMON_CLK_MT2701
+	---help---
+	  This driver supports MediaTek MT2701 g3dsys clocks.
+
 config COMMON_CLK_MT2712
 	bool "Clock driver for MediaTek MT2712"
 	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
drivers/clk/mediatek/Makefile +1 -0
index b80eff2..844b55d 100644
@@ -9,6 +9,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
 obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
 obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
 obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
 obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
 obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
 obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
drivers/clk/mediatek/clk-mt2701-g3d.c new file +95 -0

95 lines not on this page · raw message

Signature · 1 line
2.7.4
maintainer Applied
#15 lore raw

Re: [PATCH v2 5/6] clk: mediatek: add g3dsys support for MT2701 and MT7623

Quoting sean.wang at mediatek.com (2018-04-27 01:14:46)

Quoted 7 lines

From: Sean Wang <[email protected]>

Add clock driver support for g3dsys on MT2701 and MT7623, which is providing essential clock gate and reset controller to Mali-450.

Signed-off-by Sean Wang <[email protected]>

---

Applied to clk-next

author
#16 lore raw

PATCH v2 6/6 arm: dts: mt7623: add Mali-450 and related device nodes

In reply to [email protected]

From: Sean Wang <[email protected]>

Add nodes for Mali-450 device, g3dsys device providing required clock gate and reset control and larb3 offering an arbiter through iommu for controlling access to external memory requested from Mali-450.

Signed-off-by Sean Wang <[email protected]>
---
 arch/arm/boot/dts/mt7623.dtsi  | 70 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mt7623a.dtsi |  4 +++
 2 files changed, 74 insertions(+)
arch/arm/boot/dts/mt7623.dtsi +70 -0
index 59139dd..1cd8208 100644
@@ -276,6 +276,17 @@
 		clock-names = "system-clk", "rtc-clk";
 	};
 
+	smi_common: smi at 1000c000 {
+		compatible = "mediatek,mt7623-smi-common",
+			     "mediatek,mt2701-smi-common";
+		reg = <0 0x1000c000 0 0x1000>;
+		clocks = <&infracfg CLK_INFRA_SMI>,
+			 <&mmsys CLK_MM_SMI_COMMON>,
+			 <&infracfg CLK_INFRA_SMI>;
+		clock-names = "apb", "smi", "async";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	pwrap: pwrap at 1000d000 {
 		compatible = "mediatek,mt7623-pwrap",
 			     "mediatek,mt2701-pwrap";

@@ -307,6 +318,17 @@
 		reg = <0 0x10200100 0 0x1c>;
 	};
 
+	iommu: iommu at 10205000 {
+		compatible = "mediatek,mt7623-m4u",
+			     "mediatek,mt2701-m4u";
+		reg = <0 0x10205000 0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_M4U>;
+		clock-names = "bclk";
+		mediatek,larbs = <&larb3>;
+		#iommu-cells = <1>;
+	};
+
 	efuse: efuse at 10206000 {
 		compatible = "mediatek,mt7623-efuse",
 			     "mediatek,mt8173-efuse";

@@ -682,6 +704,54 @@
 		status = "disabled";
 	};
 
+	g3dsys: clock-controller at 13000000 {
+		compatible = "mediatek,mt7623-g3dsys",
+			     "mediatek,mt2701-g3dsys",
+			     "syscon";
+		reg = <0 0x13000000 0 0x200>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	larb3: larb at 13010000 {
+		compatible = "mediatek,mt7623-smi-larb",
+			     "mediatek,mt2701-smi-larb";
+		reg = <0 0x13010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larb-id = <3>;
+		clocks = <&clk26m>, <&clk26m>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+	};
+
+	mali: gpu at 13040000 {
+		compatible = "mediatek,mt7623-mali", "arm,mali-450";
+		reg = <0 0x13040000 0 0x30000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
+				  "ppmmu1", "pp2", "ppmmu2", "pp";
+		clocks = <&topckgen CLK_TOP_MMPLL>,
+			 <&g3dsys CLK_G3DSYS_CORE>;
+		clock-names = "bus", "core";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+		mediatek,larb = <&larb3>;
+		resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
+	};
+
+	mmsys: syscon at 14000000 {
+		compatible = "mediatek,mt2701-mmsys", "syscon";
+		reg = <0 0x14000000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
 	hifsys: syscon at 1a000000 {
 		compatible = "mediatek,mt7623-hifsys",
 			     "mediatek,mt2701-hifsys",
arch/arm/boot/dts/mt7623a.dtsi +4 -0
index 0735a1fb8..a42fd46 100644
@@ -21,6 +21,10 @@
 	power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>;
 };
 
+&mali {
+	status = "disabled";
+};
+
 &nandc {
 	power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
 };
Signature · 1 line
2.7.4