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arm: dts: socfpga: stratix10: Fix memory node

PATCH New Ley Foon Tan 2 participants 4 messages Jul 12, 2018

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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Ley Foon Tan

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#0 lore raw

PATCH 1/1 arm: dts: socfpga: stratix10: Fix memory node

Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get memory size from DT. So, we need to update memory size in memory node. Otherwise, it cause U-boot hang.

Signed-off-by Ley Foon Tan <[email protected]>
---
 arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/dts/socfpga_stratix10_socdk.dts +2 -2
index c6ab0ae..6e8ddcd 100644
@@ -36,8 +36,8 @@
 
 	memory {
 		device_type = "memory";
-		/* We expect the bootloader to fill in the reg */
-		reg = <0 0 0 0>;
+		reg = <0 0 0 0x80000000>; /* 2GB */
+		u-boot,dm-pre-reloc;
 	};
 };
Signature · 1 line
2.7.4
Applied
#1 lore raw

PATCH 1/1 arm: dts: socfpga: stratix10: Fix memory node

Quoted 15 lines · Ley Foon Tan

Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get memory size from DT. So, we need to update memory size in memory node. Otherwise, it cause U-boot hang.

Signed-off-by Ley Foon Tan <[email protected]>
---
 arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/dts/socfpga_stratix10_socdk.dts +0 -0
index c6ab0ae..6e8ddcd 100644

arch/arm/dts/socfpga_stratix10_socdk.dts line 43

Quoted 10 lines
arch/arm/dts/socfpga_stratix10_socdk.dts +2 -2
@@ -36,8 +36,8 @@
 
 	memory {
 		device_type = "memory";
-		/* We expect the bootloader to fill in the reg */
-		reg = <0 0 0 0>;
+		reg = <0 0 0 0x80000000>; /* 2GB */
+		u-boot,dm-pre-reloc;
 	};
 };

Applied, thanks

Signature · 2 lines
Best regards,
Marek Vasut
author
#2 lore raw

PATCH 1/1 arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only

In reply to Ley Foon Tan

MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled.

Signed-off-by Ley Foon Tan <[email protected]>
---
 arch/arm/mach-socfpga/board.c | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/mach-socfpga/board.c +2 -0
index cb6530f..26d84be 100644
@@ -19,6 +19,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {
+#ifndef CONFIG_ARM64
 	/*
 	 * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled.
 	 * This is optional on CycloneV / ArriaV.

@@ -29,6 +30,7 @@ void s_init(void) {
 		"isb\n"
 		"dsb\n"
 	::"r"(0x0));
+#endif
 }
 
 /*
Signature · 1 line
2.7.4
Applied
#3 lore raw

PATCH 1/1 arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only

Quoted 22 lines · Ley Foon Tan

MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled.

Signed-off-by Ley Foon Tan <[email protected]>
---
 arch/arm/mach-socfpga/board.c | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/mach-socfpga/board.c +1 -0
index cb6530f..26d84be 100644
@@ -19,6 +19,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 void s_init(void) {
+#ifndef CONFIG_ARM64
 	/*
 	 * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled.
 	 * This is optional on CycloneV / ArriaV.

arch/arm/mach-socfpga/board.c void s_init(void) { · line 36

Quoted 7 lines
arch/arm/mach-socfpga/board.c +1 -0
@@ -29,6 +30,7 @@ void s_init(void) {
 		"isb\n"
 		"dsb\n"
 	::"r"(0x0));
+#endif
 }
 
 /*

Applied, thanks

Signature · 2 lines
Best regards,
Marek Vasut