ddr: altera: Add ECC DRAM scrubbing support for Stratix 10
PATCH 1/1 ddr: altera: Add ECC DRAM scrubbing support for Stratix 10
From: Tien Fong Chee <[email protected]>
The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance.
--- drivers/ddr/altera/sdram_s10.c | 44 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 44 insertions(+), 0 deletions(-)
drivers/ddr/altera/sdram_s10.c +44 -0
@@ -8,6 +8,7 @@#include <errno.h> #include <div64.h> #include <asm/io.h> +#include <linux/sizes.h> #include <wait_bit.h> #include <asm/arch/firewall_s10.h> #include <asm/arch/sdram_s10.h>
@@ -134,6 +135,47 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } +/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits (unsigned long long size) +{ +/* 1GB per chunk */ +unsigned long long size_byte =SZ_1G ; +unsigned long long remaining_size; +unsigned long long dst_addr =0x8000 ; +unsigned int start =get_timer (0 ); + +icache_enable (); + +memset (0 ,0 , dst_addr); + gd->arch.tlb_addr =0x4000 ; + gd->arch.tlb_size =PGTABLE_SIZE ; + +dcache_enable (); + + remaining_size = size - dst_addr; +printf ("DDRCAL: Scrubbing ECC RAM (%d MiB).\n" , (u32)(size >>20 )); + +while (remaining_size) { +if (remaining_size <= size_byte) { +memset ((void *)dst_addr,0 , remaining_size); +break ; + }else { +memset ((void *)dst_addr,0 , size_byte); + dst_addr += size_byte; + } + +WATCHDOG_RESET (); + remaining_size -= size_byte; + } + +flush_dcache_all (); +printf ("DDRCAL: Scrubbing ECC RAM done.\n" ); +dcache_disable (); + +printf ("SDRAM-ECC: Initialized success with %d ms\n" , + (unsigned )get_timer (start)); +} +/** * sdram_mmr_init_full() - Function to initialize SDRAM MMR *
@@ -351,6 +393,8 @@ int sdram_mmr_init_full(unsigned int unused)setbits_le32 (SOCFPGA_SDR_ADDRESS +ECCCTRL2 , (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |DDR_HMC_ECCCTL2_AWB_EN_SET_MSK )); + +sdram_init_ecc_bits (gd->ram_size); }else { clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
Signature · 1 line
1.7.7.4
PATCH 1/1 ddr: altera: Add ECC DRAM scrubbing support for Stratix 10
Quoted 33 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance.
Signed-off-by Tien Fong Chee <[email protected]>--- drivers/ddr/altera/sdram_s10.c | 44 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 44 insertions(+), 0 deletions(-)drivers/ddr/altera/sdram_s10.c +5
-0@@ -8,6 +8,7 @@#include <errno.h> #include <div64.h> #include <asm/io.h> +#include <linux/sizes.h> #include <wait_bit.h> #include <asm/arch/firewall_s10.h> #include <asm/arch/sdram_s10.h> @@ -134,6 +135,47 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } +/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits (unsigned long long size) +{ +/* 1GB per chunk */
drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 151
Quoted 10 lines
drivers/ddr/altera/sdram_s10.c +10
-0+unsigned long long size_byte =SZ_1G ; +unsigned long long remaining_size; +unsigned long long dst_addr =0x8000 ; +unsigned int start =get_timer (0 ); + +icache_enable (); + +memset (0 ,0 , dst_addr); + gd->arch.tlb_addr =0x4000 ; + gd->arch.tlb_size =PGTABLE_SIZE ;
Are you sure this is valid on arm64 ? It looks like something copies from arria10.
Quoted 7 lines
drivers/ddr/altera/sdram_s10.c +7
-0+dcache_enable (); + + remaining_size = size - dst_addr; +printf ("DDRCAL: Scrubbing ECC RAM (%d MiB).\n" , (u32)(size >>20 )); + +while (remaining_size) { +if (remaining_size <= size_byte) {
drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 169
Quoted 10 lines
drivers/ddr/altera/sdram_s10.c +10
-0+memset ((void *)dst_addr,0 , remaining_size); +break ; + }else { +memset ((void *)dst_addr,0 , size_byte); + dst_addr += size_byte; + } + +WATCHDOG_RESET (); + remaining_size -= size_byte; + }
How long does this take ?
Quoted 21 lines
drivers/ddr/altera/sdram_s10.c +10
-0+flush_dcache_all (); +printf ("DDRCAL: Scrubbing ECC RAM done.\n" ); +dcache_disable (); + +printf ("SDRAM-ECC: Initialized success with %d ms\n" , + (unsigned )get_timer (start)); +} +/** * sdram_mmr_init_full() - Function to initialize SDRAM MMR * @@ -351,6 +393,8 @@ int sdram_mmr_init_full(unsigned int unused)setbits_le32 (SOCFPGA_SDR_ADDRESS +ECCCTRL2 , (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |DDR_HMC_ECCCTL2_AWB_EN_SET_MSK )); + +sdram_init_ecc_bits (gd->ram_size); }else { clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 1/1 ddr: altera: Add ECC DRAM scrubbing support for Stratix 10
Quoted 46 lines · Marek Vasut
Quoted 45 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.Signed-off-by Tien Fong Chee <[email protected]>---
drivers/ddr/altera/sdram_s10.c | 44
++++++++++++++++++++++++++++++++++++++++1 files changed, 44 insertions(+), 0 deletions(-)drivers/ddr/altera/sdram_s10.c +1
-0@@ -8,6 +8,7 @@ #include <errno.h> #include <div64.h> #include <asm/io.h> +#include <linux/sizes.h> #include <wait_bit.h> #include <asm/arch/firewall_s10.h> #include <asm/arch/sdram_s10.h>@@ -134,6 +135,47 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); }drivers/ddr/altera/sdram_s10.c +8
-0+/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits (unsigned long long size) +{ +/* 1GB per chunk */ +unsigned long long size_byte =SZ_1G ; +unsigned long long remaining_size; +unsigned long long dst_addr =0x8000 ; +unsigned int start =get_timer (0 );
Quoted 8 lines
drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 151
Quoted 6 lines
drivers/ddr/altera/sdram_s10.c +6
-0+ +icache_enable (); + +memset (0 ,0 , dst_addr); + gd->arch.tlb_addr =0x4000 ; + gd->arch.tlb_size =PGTABLE_SIZE ;Are you sure this is valid on arm64 ? It looks like something copies from arria10.
The cache on/off is copied from your implementation on Arria 10. Yes, i have tested it, it is working on Stratix 10 board.
Quoted 7 lines
Quoted 7 lines
drivers/ddr/altera/sdram_s10.c +4
-0+dcache_enable (); + + remaining_size = size - dst_addr; + printf("DDRCAL: Scrubbing ECC RAM (%d MiB).\n", (u32)(sizeQuoted 1 line
Quoted 1 line
20));
Quoted 15 lines
Quoted 5 lines
drivers/ddr/altera/sdram_s10.c +4
-0+ +while (remaining_size) { +if (remaining_size <= size_byte) { + memset((void *)dst_addr, 0,
remaining_size);drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 169
Quoted 9 lines
drivers/ddr/altera/sdram_s10.c +9
-0+break ; + }else { +memset ((void *)dst_addr,0 , size_byte); + dst_addr += size_byte; + } + +WATCHDOG_RESET (); + remaining_size -= size_byte; + }How long does this take ?
1359ms for 2GB. But I have no idea why Arria 10 board can't achieve the same result. Could you try again on your Arria 10 ES board?
Quoted 24 lines
Quoted 23 lines
drivers/ddr/altera/sdram_s10.c +8
-0+flush_dcache_all (); +printf ("DDRCAL: Scrubbing ECC RAM done.\n" ); +dcache_disable (); + +printf ("SDRAM-ECC: Initialized success with %d ms\n" , + (unsigned )get_timer (start)); +} +/**
*sdram_mmr_init_full()- Function to initialize SDRAM MMR *drivers/ddr/altera/sdram_s10.c +0
-0@@ -351,6 +393,8 @@ int sdram_mmr_init_full(unsigned int unused) setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));drivers/ddr/altera/sdram_s10.c +2
-0+ +sdram_init_ecc_bits (gd->ram_size);} else {
clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK|
PATCH 1/1 ddr: altera: Add ECC DRAM scrubbing support for Stratix 10
Quoted 55 lines · Tien Fong
Quoted 46 lines · Marek Vasut
Quoted 45 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.Signed-off-by Tien Fong Chee <[email protected]>---
drivers/ddr/altera/sdram_s10.c | 44
++++++++++++++++++++++++++++++++++++++++1 files changed, 44 insertions(+), 0 deletions(-)drivers/ddr/altera/sdram_s10.c +1
-0@@ -8,6 +8,7 @@ #include <errno.h> #include <div64.h> #include <asm/io.h> +#include <linux/sizes.h> #include <wait_bit.h> #include <asm/arch/firewall_s10.h> #include <asm/arch/sdram_s10.h>@@ -134,6 +135,47 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); }drivers/ddr/altera/sdram_s10.c +8
-0+/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits (unsigned long long size) +{ +/* 1GB per chunk */ +unsigned long long size_byte =SZ_1G ; +unsigned long long remaining_size; +unsigned long long dst_addr =0x8000 ; +unsigned int start =get_timer (0 );Quoted 8 lines
drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 151
Quoted 6 lines
drivers/ddr/altera/sdram_s10.c +6
-0+ +icache_enable (); + +memset (0 ,0 , dst_addr); + gd->arch.tlb_addr =0x4000 ; + gd->arch.tlb_size =PGTABLE_SIZE ;Are you sure this is valid on arm64 ? It looks like something copies from arria10.
Quoted 2 lines
The cache on/off is copied from your implementation on Arria 10. Yes, i have tested it, it is working on Stratix 10 board.
Right, except S10 is arm64, A10 is arm32, which is why I wonder whether careless copying is enough.
Quoted 21 lines
Quoted 6 lines
Quoted 6 lines
drivers/ddr/altera/sdram_s10.c +4
-0+dcache_enable (); + + remaining_size = size - dst_addr; + printf("DDRCAL: Scrubbing ECC RAM (%d MiB).\n", (u32)(sizeQuoted 1 line
Quoted 1 line
20));
Quoted 15 lines
Quoted 5 lines
drivers/ddr/altera/sdram_s10.c +4
-0+ +while (remaining_size) { +if (remaining_size <= size_byte) { + memset((void *)dst_addr, 0,
remaining_size);drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 169
Quoted 9 lines
drivers/ddr/altera/sdram_s10.c +9
-0+break ; + }else { +memset ((void *)dst_addr,0 , size_byte); + dst_addr += size_byte; + } + +WATCHDOG_RESET (); + remaining_size -= size_byte; + }How long does this take ?
Quoted 1 line
1359ms for 2GB.
So why do you need this watchdog reset hack ?
Quoted 2 lines
But I have no idea why Arria 10 board can't achieve the same result. Could you try again on your Arria 10 ES board?
There's nothing to try, the scrubbing works fine on A10.
Quoted 22 lines
Quoted 22 lines
Quoted 22 lines
drivers/ddr/altera/sdram_s10.c +8
-0+flush_dcache_all (); +printf ("DDRCAL: Scrubbing ECC RAM done.\n" ); +dcache_disable (); + +printf ("SDRAM-ECC: Initialized success with %d ms\n" , + (unsigned )get_timer (start)); +} +/**
*sdram_mmr_init_full()- Function to initialize SDRAM MMR *drivers/ddr/altera/sdram_s10.c +0
-0@@ -351,6 +393,8 @@ int sdram_mmr_init_full(unsigned int unused) setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));drivers/ddr/altera/sdram_s10.c +2
-0+ +sdram_init_ecc_bits (gd->ram_size);} else {
clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK|
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 1/1 ddr: altera: Add ECC DRAM scrubbing support for Stratix 10
Quoted 63 lines · Marek Vasut
Quoted 62 lines · Tien Fong
Quoted 60 lines · Marek Vasut
Quoted 45 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in
such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns
them
off again. This provides satisfactory performance.Signed-off-by Tien Fong Chee <[email protected]>---
drivers/ddr/altera/sdram_s10.c | 44
++++++++++++++++++++++++++++++++++++++++1 files changed, 44 insertions(+), 0 deletions(-)drivers/ddr/altera/sdram_s10.c +1
-0@@ -8,6 +8,7 @@ #include <errno.h> #include <div64.h> #include <asm/io.h> +#include <linux/sizes.h> #include <wait_bit.h> #include <asm/arch/firewall_s10.h> #include <asm/arch/sdram_s10.h>@@ -134,6 +135,47 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); }drivers/ddr/altera/sdram_s10.c +4
-0+/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits (unsigned long long size) +{ +/* 1GB per chunk */ drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 151
Quoted 10 lines
drivers/ddr/altera/sdram_s10.c +10
-0+unsigned long long size_byte =SZ_1G ; +unsigned long long remaining_size; +unsigned long long dst_addr =0x8000 ; +unsigned int start =get_timer (0 ); + +icache_enable (); + +memset (0 ,0 , dst_addr); + gd->arch.tlb_addr =0x4000 ; + gd->arch.tlb_size =PGTABLE_SIZE ;Are you sure this is valid on arm64 ? It looks like something copies
from arria10.
Quoted 6 lines
Quoted 3 lines
The cache on/off is copied from your implementation on Arria 10. Yes, i
have tested it, it is working on Stratix 10 board.Right, except S10 is arm64, A10 is arm32, which is why I wonder whether
careless copying is enough.
The PGTABLE_SIZE is getting from the function get_page_table_size() which is specific for armv8 architecture. I'm also testing it on board to ensure sufficient RAM for the page table.
Quoted 29 lines
Quoted 29 lines
Quoted 29 lines
Quoted 22 lines
drivers/ddr/altera/sdram_s10.c +4
-0+dcache_enable (); + + remaining_size = size - dst_addr; + printf("DDRCAL: Scrubbing ECC RAM (%d MiB).\n",(u32)(size
Quoted 3 lines
Quoted 3 lines
20));
drivers/ddr/altera/sdram_s10.c +4
-0+ +while (remaining_size) { +if (remaining_size <= size_byte) { + memset((void *)dst_addr, 0,
remaining_size);drivers/ddr/altera/sdram_s10.c +3
-0+break ; + }else { + memset((void *)dst_addr, 0,
size_byte);drivers/ddr/altera/sdram_s10.c static int poll_hmc_clock_status(void) · line 169
Quoted 6 lines
drivers/ddr/altera/sdram_s10.c +6
-0+ dst_addr += size_byte; + } + +WATCHDOG_RESET (); + remaining_size -= size_byte; + }How long does this take ?
Quoted 2 lines
Quoted 1 line
1359ms for 2GB.
So why do you need this watchdog reset hack ?
Yeah, for size scalable. When size growing up, it would take longer to scrub. Without watchdog reset on time, it might be causing system to reset.
Quoted 5 lines
Quoted 4 lines
But I have no idea why Arria 10 board can't achieve the same result. Could you try again on your Arria 10 ES board?
There's nothing to try, the scrubbing works fine on A10.
Then, that really weird it took so long to finish scrubbing.
Quoted 30 lines
Quoted 29 lines
Quoted 29 lines
Quoted 29 lines
drivers/ddr/altera/sdram_s10.c +8
-0+flush_dcache_all (); +printf ("DDRCAL: Scrubbing ECC RAM done.\n" ); +dcache_disable (); + +printf ("SDRAM-ECC: Initialized success with %d ms\n" , + (unsigned )get_timer (start)); +} +/**
*sdram_mmr_init_full()- Function to initialize SDRAM MMR *drivers/ddr/altera/sdram_s10.c +0
-0@@ -351,6 +393,8 @@ int sdram_mmr_init_full(unsigned int unused) setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)) ;drivers/ddr/altera/sdram_s10.c +2
-0+ +sdram_init_ecc_bits (gd->ram_size);} else {
clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |